Add description to support Axis, ARTPEC-8 SoC.
ARTPEC-8 is the SoC platform of Axis Communications
and PCIe controller is designed based on Design-Ware PCIe controller.
changes since v1 :
-'make dt_binding_check' result improvement
-Add the missing property list
-Align the indentation of continued lines/entries
Signed-off-by: Wangseok Lee <[email protected]>
---
.../bindings/pci/axis,artpec8-pcie-ep.yaml | 108 ++++++++++++++++++
.../devicetree/bindings/pci/axis,artpec8-pcie.yaml | 123 +++++++++++++++++++++
2 files changed, 231 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/axis,artpec8-pcie-ep.yaml
create mode 100644 Documentation/devicetree/bindings/pci/axis,artpec8-pcie.yaml
diff --git a/Documentation/devicetree/bindings/pci/axis,artpec8-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/axis,artpec8-pcie-ep.yaml
new file mode 100644
index 0000000..3512e38
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/axis,artpec8-pcie-ep.yaml
@@ -0,0 +1,108 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/axis,artpec8-pcie-ep.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARTPEC-8 SoC PCIe Controller Device Tree Bindings
+
+maintainers:
+ - Jesper Nilsson <[email protected]>
+
+description: |+
+ This PCIe end-point controller is based on the Synopsys DesignWare PCIe IP
+ and thus inherits all the common properties defined in snps,dw-pcie-ep.yaml.
+
+allOf:
+ - $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
+
+properties:
+ compatible:
+ const: axis,artpec8-pcie-ep
+
+ reg:
+ items:
+ - description: Data Bus Interface (DBI) registers.
+ - description: Data Bus Interface (DBI2) registers.
+ - description: PCIe address space region.
+
+ reg-names:
+ items:
+ - const: dbi
+ - const: dbi2
+ - const: addr_space
+
+ interrupts:
+ maxItems: 1
+
+ interrupts-names:
+ items:
+ - const: intr
+
+ clocks:
+ items:
+ - description: PIPE clock, used by the controller to clock the PIPE
+ - description: PCIe dbi clock, ungated version
+ - description: PCIe master clock, ungated version
+ - description: PCIe slave clock, ungated version
+
+ clock-names:
+ items:
+ - const: pipe_clk
+ - const: dbi_clk
+ - const: mstr_clk
+ - const: slv_clk
+
+ phys:
+ maxItems: 1
+
+ phy-names:
+ items:
+ - const: pcie_phy
+
+ num-lanes:
+ const: 2
+
+required:
+ - reg
+ - reg-names
+ - interrupts
+ - interrupt-names
+ - clocks
+ - clock-names
+ - phys
+ - num-lanes
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ artpec8 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ pcie_ep: pcie-ep@17200000 {
+ compatible = "axis,artpec8-pcie-ep";
+ reg = <0x0 0x17200000 0x0 0x1000>,
+ <0x0 0x17201000 0x0 0x1000>,
+ <0x2 0x00000000 0x6 0x00000000>;
+ reg-names = "dbi", "dbi2", "addr_space";
+ #interrupt-cells = <1>;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "intr";
+ clocks = <&clock_cmu_fsys 39>,
+ <&clock_cmu_fsys 38>,
+ <&clock_cmu_fsys 37>,
+ <&clock_cmu_fsys 36>;
+ clock-names = "pipe_clk", "dbi_clk", "mstr_clk", "slv_clk";
+ phys = <&pcie_phy>;
+ phy-names = "pcie_phy";
+ num-lanes = <2>;
+ bus-range = <0x00 0xff>;
+ num-ib-windows = <16>;
+ num-ob-windows = <16>;
+ };
+ };
+...
diff --git a/Documentation/devicetree/bindings/pci/axis,artpec8-pcie.yaml b/Documentation/devicetree/bindings/pci/axis,artpec8-pcie.yaml
new file mode 100644
index 0000000..945a061
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/axis,artpec8-pcie.yaml
@@ -0,0 +1,123 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/axis,artpec8-pcie.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Artpec-8 SoC PCIe Controller Device Tree Bindings
+
+maintainers:
+ - Jesper Nilsson <[email protected]>
+
+description: |+
+ This PCIe host controller is based on the Synopsys DesignWare PCIe IP
+ and thus inherits all the common properties defined in snps,dw-pcie.yaml.
+
+allOf:
+ - $ref: /schemas/pci/snps,dw-pcie.yaml#
+
+properties:
+ compatible:
+ const: axis,artpec8-pcie
+
+ reg:
+ items:
+ - description: Data Bus Interface (DBI) registers.
+ - description: External Local Bus interface (ELBI) registers.
+ - description: PCIe configuration space region.
+
+ reg-names:
+ items:
+ - const: dbi
+ - const: elbi
+ - const: config
+
+ device_type:
+ items:
+ - const: pci
+
+ ranges:
+ maxItems: 2
+
+ num-lanes:
+ const: 2
+
+ interrupts:
+ maxItems: 1
+
+ interrupts-names:
+ items:
+ - const: intr
+
+ clocks:
+ items:
+ - description: PIPE clock, used by the controller to clock the PIPE
+ - description: PCIe dbi clock, ungated version
+ - description: PCIe master clock, ungated version
+ - description: PCIe slave clock, ungated version
+
+ clock-names:
+ items:
+ - const: pipe_clk
+ - const: dbi_clk
+ - const: mstr_clk
+ - const: slv_clk
+
+ phys:
+ maxItems: 1
+
+ phy-names:
+ items:
+ - const: pcie_phy
+
+required:
+ - reg
+ - reg-names
+ - device_type
+ - ranges
+ - num-lanes
+ - interrupts
+ - interrupt-names
+ - clocks
+ - clock-names
+ - phys
+ - phy-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ artpec8 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ pcie: pcie@17200000 {
+ compatible = "axis,artpec8-pcie";
+ reg = <0x0 0x17200000 0x0 0x1000>,
+ <0x0 0x16ca0000 0x0 0x2000>,
+ <0x7 0x0001e000 0x0 0x2000>;
+ reg-names = "dbi", "elbi", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = </* non-prefetchable memory */
+ 0x83000000 0x0 0x0000000 0x2 0x00000000 0x5 0x00000000
+ /* downstream I/O */
+ 0x81000000 0x0 0x0000000 0x7 0x00000000 0x0 0x00010000>;
+ num-lanes = <2>;
+ bus-range = <0x00 0xff>;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "intr";
+ #interrupt-cells = <1>;
+ clocks = <&cmu_fsys 39>,
+ <&cmu_fsys 38>,
+ <&cmu_fsys 37>,
+ <&cmu_fsys 36>;
+ clock-names = "pipe_clk", "dbi_clk", "mstr_clk", "slv_clk";
+ phys = <&pcie_phy>;
+ phy-names = "pcie_phy";
+ };
+ };
+...
--
2.9.5
On 03/06/2022 04:23, Wangseok Lee wrote:
> Add description to support Axis, ARTPEC-8 SoC.
> ARTPEC-8 is the SoC platform of Axis Communications
> and PCIe controller is designed based on Design-Ware PCIe controller.
>
> changes since v1 :
Changelog goes after --- .
> -'make dt_binding_check' result improvement
> -Add the missing property list
> -Align the indentation of continued lines/entries
>
> Signed-off-by: Wangseok Lee <[email protected]>
> ---
> .../bindings/pci/axis,artpec8-pcie-ep.yaml | 108 ++++++++++++++++++
> .../devicetree/bindings/pci/axis,artpec8-pcie.yaml | 123 +++++++++++++++++++++
> 2 files changed, 231 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pci/axis,artpec8-pcie-ep.yaml
> create mode 100644 Documentation/devicetree/bindings/pci/axis,artpec8-pcie.yaml
>
> diff --git a/Documentation/devicetree/bindings/pci/axis,artpec8-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/axis,artpec8-pcie-ep.yaml
> new file mode 100644
> index 0000000..3512e38
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/axis,artpec8-pcie-ep.yaml
> @@ -0,0 +1,108 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pci/axis,artpec8-pcie-ep.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: ARTPEC-8 SoC PCIe Controller Device Tree Bindings
s/Device Tree Bindings//
> +
> +maintainers:
> + - Jesper Nilsson <[email protected]>
> +
> +description: |+
> + This PCIe end-point controller is based on the Synopsys DesignWare PCIe IP
> + and thus inherits all the common properties defined in snps,dw-pcie-ep.yaml.
> +
> +allOf:
> + - $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
> +
> +properties:
> + compatible:
> + const: axis,artpec8-pcie-ep
> +
> + reg:
> + items:
> + - description: Data Bus Interface (DBI) registers.
> + - description: Data Bus Interface (DBI2) registers.
> + - description: PCIe address space region.
> +
> + reg-names:
> + items:
> + - const: dbi
> + - const: dbi2
> + - const: addr_space
> +
> + interrupts:
> + maxItems: 1
> +
> + interrupts-names:
> + items:
> + - const: intr
Remove the interrupts-names entirely, no need for single item with
generic name.
> +
> + clocks:
> + items:
> + - description: PIPE clock, used by the controller to clock the PIPE
> + - description: PCIe dbi clock, ungated version
> + - description: PCIe master clock, ungated version
> + - description: PCIe slave clock, ungated version
> +
> + clock-names:
> + items:
> + - const: pipe_clk
> + - const: dbi_clk
> + - const: mstr_clk
> + - const: slv_clk
Remove "_clk" suffix from all entries.
> +
> + phys:
> + maxItems: 1
> +
> + phy-names:
> + items:
> + - const: pcie_phy
Remove the phy-names entirely, no need for single item with generic name.
> +
> + num-lanes:
> + const: 2
> +
> +required:
My comment was not applied here, so please fix it.
> + - reg
> + - reg-names
> + - interrupts
> + - interrupt-names
> + - clocks
> + - clock-names
> + - phys
> + - num-lanes
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/irq.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + artpec8 {
Generic nodes please. Did you see "artpec8" or something like this in
any DTS?
> + #address-cells = <2>;
> + #size-cells = <2>;
> + pcie_ep: pcie-ep@17200000 {
> + compatible = "axis,artpec8-pcie-ep";
> + reg = <0x0 0x17200000 0x0 0x1000>,
> + <0x0 0x17201000 0x0 0x1000>,
> + <0x2 0x00000000 0x6 0x00000000>;
> + reg-names = "dbi", "dbi2", "addr_space";
> + #interrupt-cells = <1>;
> + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "intr";
> + clocks = <&clock_cmu_fsys 39>,
> + <&clock_cmu_fsys 38>,
> + <&clock_cmu_fsys 37>,
> + <&clock_cmu_fsys 36>;
> + clock-names = "pipe_clk", "dbi_clk", "mstr_clk", "slv_clk";
> + phys = <&pcie_phy>;
> + phy-names = "pcie_phy";
> + num-lanes = <2>;
> + bus-range = <0x00 0xff>;
> + num-ib-windows = <16>;
> + num-ob-windows = <16>;
> + };
> + };
> +...
> diff --git a/Documentation/devicetree/bindings/pci/axis,artpec8-pcie.yaml b/Documentation/devicetree/bindings/pci/axis,artpec8-pcie.yaml
> new file mode 100644
> index 0000000..945a061
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/axis,artpec8-pcie.yaml
> @@ -0,0 +1,123 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pci/axis,artpec8-pcie.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Artpec-8 SoC PCIe Controller Device Tree Bindings
Ditto
> +
> +maintainers:
> + - Jesper Nilsson <[email protected]>
> +
> +description: |+
> + This PCIe host controller is based on the Synopsys DesignWare PCIe IP
> + and thus inherits all the common properties defined in snps,dw-pcie.yaml.
> +
> +allOf:
> + - $ref: /schemas/pci/snps,dw-pcie.yaml#
> +
> +properties:
> + compatible:
> + const: axis,artpec8-pcie
> +
> + reg:
> + items:
> + - description: Data Bus Interface (DBI) registers.
> + - description: External Local Bus interface (ELBI) registers.
> + - description: PCIe configuration space region.
> +
> + reg-names:
> + items:
> + - const: dbi
> + - const: elbi
> + - const: config
> +
> + device_type:
> + items:
It's not a list, but just a string. No need for items.
> + - const: pci
> +
> + ranges:
> + maxItems: 2
> +
> + num-lanes:
> + const: 2
> +
> + interrupts:
> + maxItems: 1
> +
> + interrupts-names:
> + items:
> + - const: intr
Remove entire property.
> +
> + clocks:
> + items:
> + - description: PIPE clock, used by the controller to clock the PIPE
> + - description: PCIe dbi clock, ungated version
> + - description: PCIe master clock, ungated version
> + - description: PCIe slave clock, ungated version
> +
> + clock-names:
> + items:
> + - const: pipe_clk
> + - const: dbi_clk
> + - const: mstr_clk
> + - const: slv_clk
Remove suffix.
> +
> + phys:
> + maxItems: 1
> +
> + phy-names:
> + items:
> + - const: pcie_phy
Remove entire property.
> +
> +required:
Previous comment not applied.
> + - reg
> + - reg-names
> + - device_type
> + - ranges
> + - num-lanes
> + - interrupts
> + - interrupt-names
> + - clocks
> + - clock-names
> + - phys
> + - phy-names
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/irq.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + artpec8 {
Same as previous patch.
> + #address-cells = <2>;
> + #size-cells = <2>;
> + pcie: pcie@17200000 {
> + compatible = "axis,artpec8-pcie";
> + reg = <0x0 0x17200000 0x0 0x1000>,
> + <0x0 0x16ca0000 0x0 0x2000>,
> + <0x7 0x0001e000 0x0 0x2000>;
> + reg-names = "dbi", "elbi", "config";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + device_type = "pci";
> + ranges = </* non-prefetchable memory */
> + 0x83000000 0x0 0x0000000 0x2 0x00000000 0x5 0x00000000
> + /* downstream I/O */
> + 0x81000000 0x0 0x0000000 0x7 0x00000000 0x0 0x00010000>;
> + num-lanes = <2>;
> + bus-range = <0x00 0xff>;
> + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "intr";
> + #interrupt-cells = <1>;
> + clocks = <&cmu_fsys 39>,
> + <&cmu_fsys 38>,
> + <&cmu_fsys 37>,
> + <&cmu_fsys 36>;
> + clock-names = "pipe_clk", "dbi_clk", "mstr_clk", "slv_clk";
> + phys = <&pcie_phy>;
> + phy-names = "pcie_phy";
> + };
> + };
> +...
Best regards,
Krzysztof
On 06/06/2022 19:12, Krzysztof Kozlowski wrote:
> On 03/06/2022 04:23, Wangseok Lee wrote:
>> Add description to support Axis, ARTPEC-8 SoC.
>> ARTPEC-8 is the SoC platform of Axis Communications
>> and PCIe controller is designed based on Design-Ware PCIe controller.
>>
>> changes since v1 :
>
> Changelog goes after --- .
>
Ok, i check the linux commit style.
I will fix it.
>> -'make dt_binding_check' result improvement
>> -Add the missing property list
>> -Align the indentation of continued lines/entries
>>
>> Signed-off-by: Wangseok Lee <[email protected]>
>> ---
>> .../bindings/pci/axis,artpec8-pcie-ep.yaml | 108 ++++++++++++++++++
>> .../devicetree/bindings/pci/axis,artpec8-pcie.yaml | 123 +++++++++++++++++++++
>> 2 files changed, 231 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/pci/axis,artpec8-pcie-ep.yaml
>> create mode 100644 Documentation/devicetree/bindings/pci/axis,artpec8-pcie.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/pci/axis,artpec8-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/axis,artpec8-pcie-ep.yaml
>> new file mode 100644
>> index 0000000..3512e38
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pci/axis,artpec8-pcie-ep.yaml
>> @@ -0,0 +1,108 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: https://protect2.fireeye.com/v1/url?k=6948615e-08c37447-6949ea11-74fe485cbfec-fea93affd4665d88&q=1&e=501044d4-19cb-42be-bca2-b59852a39c26&u=http%3A%2F%2Fdevicetree.org%2Fschemas%2Fpci%2Faxis%2Cartpec8-pcie-ep.yaml%23
>> +$schema: https://protect2.fireeye.com/v1/url?k=629fe254-0314f74d-629e691b-74fe485cbfec-f3d83f3fca174eef&q=1&e=501044d4-19cb-42be-bca2-b59852a39c26&u=http%3A%2F%2Fdevicetree.org%2Fmeta-schemas%2Fcore.yaml%23
>> +
>> +title: ARTPEC-8 SoC PCIe Controller Device Tree Bindings
>
> s/Device Tree Bindings//
>
I will remove it.
>> +
>> +maintainers:
>> + - Jesper Nilsson <[email protected]>
>> +
>> +description: |+
>> + This PCIe end-point controller is based on the Synopsys DesignWare PCIe IP
>> + and thus inherits all the common properties defined in snps,dw-pcie-ep.yaml.
>> +
>> +allOf:
>> + - $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
>> +
>> +properties:
>> + compatible:
>> + const: axis,artpec8-pcie-ep
>> +
>> + reg:
>> + items:
>> + - description: Data Bus Interface (DBI) registers.
>> + - description: Data Bus Interface (DBI2) registers.
>> + - description: PCIe address space region.
>> +
>> + reg-names:
>> + items:
>> + - const: dbi
>> + - const: dbi2
>> + - const: addr_space
>> +
>> + interrupts:
>> + maxItems: 1
>> +
>> + interrupts-names:
>> + items:
>> + - const: intr
>
> Remove the interrupts-names entirely, no need for single item with
> generic name.
>
>
I will remove it.
>> +
>> + clocks:
> + items:
>> + - description: PIPE clock, used by the controller to clock the PIPE
>> + - description: PCIe dbi clock, ungated version
>> + - description: PCIe master clock, ungated version
>> + - description: PCIe slave clock, ungated version
>> +
>> + clock-names:
>> + items:
>> + - const: pipe_clk
>> + - const: dbi_clk
>> + - const: mstr_clk
>> + - const: slv_clk
>
> Remove "_clk" suffix from all entries.
>
Ok.
>> +
>> + phys:
>> + maxItems: 1
>> +
>> + phy-names:
>> + items:
>> + - const: pcie_phy
>
> Remove the phy-names entirely, no need for single item with generic name.
>
Ok.
>> +
>> + num-lanes:
>> + const: 2
>> +
>> +required:
>
> My comment was not applied here, so please fix it.
>
>
Ok, i miss compatible..
>> + - reg
>> + - reg-names
>> + - interrupts
>> + - interrupt-names
>> + - clocks
>> + - clock-names
>> + - phys
>> + - num-lanes
>> +
>> +unevaluatedProperties: false
>> +
>> +examples:
>> + - |
>> + #include <dt-bindings/interrupt-controller/irq.h>
>> + #include <dt-bindings/interrupt-controller/arm-gic.h>
>> +
>> + artpec8 {
>
> Generic nodes please. Did you see "artpec8" or something like this in
> any DTS?
>
Ok, i will modify to 'soc'.
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + pcie_ep: pcie-ep@17200000 {
>> + compatible = "axis,artpec8-pcie-ep";
>> + reg = <0x0 0x17200000 0x0 0x1000>,
>> + <0x0 0x17201000 0x0 0x1000>,
>> + <0x2 0x00000000 0x6 0x00000000>;
>> + reg-names = "dbi", "dbi2", "addr_space";
>> + #interrupt-cells = <1>;
>> + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
>> + interrupt-names = "intr";
>> + clocks = <&clock_cmu_fsys 39>,
>> + <&clock_cmu_fsys 38>,
>> + <&clock_cmu_fsys 37>,
>> + <&clock_cmu_fsys 36>;
>> + clock-names = "pipe_clk", "dbi_clk", "mstr_clk", "slv_clk";
>> + phys = <&pcie_phy>;
>> + phy-names = "pcie_phy";
>> + num-lanes = <2>;
>> + bus-range = <0x00 0xff>;
>> + num-ib-windows = <16>;
>> + num-ob-windows = <16>;
>> + };
>> + };
>
>
>> +...
>> diff --git a/Documentation/devicetree/bindings/pci/axis,artpec8-pcie.yaml b/Documentation/devicetree/bindings/pci/axis,artpec8-pcie.yaml
>> new file mode 100644
>> index 0000000..945a061
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pci/axis,artpec8-pcie.yaml
>> @@ -0,0 +1,123 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: https://protect2.fireeye.com/v1/url?k=1de15b04-7c6a4e1d-1de0d04b-74fe485cbfec-aaaa8e4e3891e6f9&q=1&e=501044d4-19cb-42be-bca2-b59852a39c26&u=http%3A%2F%2Fdevicetree.org%2Fschemas%2Fpci%2Faxis%2Cartpec8-pcie.yaml%23
>> +$schema: https://protect2.fireeye.com/v1/url?k=66c233a3-074926ba-66c3b8ec-74fe485cbfec-9eadff8200c7df97&q=1&e=501044d4-19cb-42be-bca2-b59852a39c26&u=http%3A%2F%2Fdevicetree.org%2Fmeta-schemas%2Fcore.yaml%23
>> +
>> +title: Artpec-8 SoC PCIe Controller Device Tree Bindings
>
> Ditto
>
Ok.
>> +
>> +maintainers:
>> + - Jesper Nilsson <[email protected]>
>> +
>> +description: |+
>> + This PCIe host controller is based on the Synopsys DesignWare PCIe IP
>> + and thus inherits all the common properties defined in snps,dw-pcie.yaml.
>> +
>> +allOf:
>> + - $ref: /schemas/pci/snps,dw-pcie.yaml#
>> +
>> +properties:
>> + compatible:
>> + const: axis,artpec8-pcie
>> +
>> + reg:
>> + items:
>> + - description: Data Bus Interface (DBI) registers.
>> + - description: External Local Bus interface (ELBI) registers.
>> + - description: PCIe configuration space region.
>> +
>> + reg-names:
>> + items:
>> + - const: dbi
>> + - const: elbi
>> + - const: config
>> +
>> + device_type:
>> + items:
>
> It's not a list, but just a string. No need for items.
>
Ok.
>> + - const: pci
>> +
>> + ranges:
>> + maxItems: 2
>> +
>> + num-lanes:
>> + const: 2
>> +
>> + interrupts:
>> + maxItems: 1
>> +
>> + interrupts-names:
>> + items:
>> + - const: intr
>
> Remove entire property.
>
Ok.
>> +
>> + clocks:
>> + items:
>> + - description: PIPE clock, used by the controller to clock the PIPE
>> + - description: PCIe dbi clock, ungated version
>> + - description: PCIe master clock, ungated version
>> + - description: PCIe slave clock, ungated version
>> +
>> + clock-names:
>> + items:
>> + - const: pipe_clk
>> + - const: dbi_clk
>> + - const: mstr_clk
>> + - const: slv_clk
>
> Remove suffix.
>
Ok.
>> +
>> + phys:
>> + maxItems: 1
>> +
>> + phy-names:
>> + items:
>> + - const: pcie_phy
>
> Remove entire property.
>
Ok.
>> +
>> +required:
>
> Previous comment not applied.
>
Ok.
>> + - reg
>> + - reg-names
>> + - device_type
>> + - ranges
>> + - num-lanes
>> + - interrupts
>> + - interrupt-names
>> + - clocks
>> + - clock-names
>> + - phys
>> + - phy-names
>> +
>> +unevaluatedProperties: false
>> +
>> +examples:
>> + - |
>> + #include <dt-bindings/interrupt-controller/irq.h>
>> + #include <dt-bindings/interrupt-controller/arm-gic.h>
>> +
>> + artpec8 {
>
> Same as previous patch.
>
I will modify to 'soc'.
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + pcie: pcie@17200000 {
>> + compatible = "axis,artpec8-pcie";
>> + reg = <0x0 0x17200000 0x0 0x1000>,
>> + <0x0 0x16ca0000 0x0 0x2000>,
>> + <0x7 0x0001e000 0x0 0x2000>;
>> + reg-names = "dbi", "elbi", "config";
>> + #address-cells = <3>;
>> + #size-cells = <2>;
>> + device_type = "pci";
>> + ranges = </* non-prefetchable memory */
>> + 0x83000000 0x0 0x0000000 0x2 0x00000000 0x5 0x00000000
>> + /* downstream I/O */
>> + 0x81000000 0x0 0x0000000 0x7 0x00000000 0x0 0x00010000>;
>> + num-lanes = <2>;
>> + bus-range = <0x00 0xff>;
>> + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
>> + interrupt-names = "intr";
>> + #interrupt-cells = <1>;
>> + clocks = <&cmu_fsys 39>,
>> + <&cmu_fsys 38>,
>> + <&cmu_fsys 37>,
>> + <&cmu_fsys 36>;
>> + clock-names = "pipe_clk", "dbi_clk", "mstr_clk", "slv_clk";
>> + phys = <&pcie_phy>;
>> + phy-names = "pcie_phy";
>> + };
>> + };
>> +...
>
>
> Best regards,
> Krzysztof
Thank you for kindness reivew.
Best regards,
Wangseok Lee