Allwinner F1C100s has the most simple USB PHY among all Allwinner SoCs,
because it has only one OTG USB controller, no host-only OHCI/EHCI
controllers.
Add a binding document for it.
Signed-off-by: Icenowy Zheng <[email protected]>
---
.../phy/allwinner,suniv-f1c100s-usb-phy.yaml | 83 +++++++++++++++++++
1 file changed, 83 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml b/Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml
new file mode 100644
index 000000000000..180fa8840bf7
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml
@@ -0,0 +1,83 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/allwinner,suniv-f1c100s-usb-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Allwinner F1C100s USB PHY Device Tree Bindings
+
+maintainers:
+ - Chen-Yu Tsai <[email protected]>
+ - Maxime Ripard <[email protected]>
+
+properties:
+ "#phy-cells":
+ const: 1
+
+ compatible:
+ const: allwinner,suniv-f1c100s-usb-phy
+
+ reg:
+ maxItems: 1
+ description: PHY Control registers
+
+ reg-names:
+ const: phy_ctrl
+
+ clocks:
+ maxItems: 1
+ description: USB OTG PHY bus clock
+
+ clock-names:
+ const: usb0_phy
+
+ resets:
+ maxItems: 1
+ description: USB OTG reset
+
+ reset-names:
+ const: usb0_reset
+
+ usb0_id_det-gpios:
+ maxItems: 1
+ description: GPIO to the USB OTG ID pin
+
+ usb0_vbus_det-gpios:
+ maxItems: 1
+ description: GPIO to the USB OTG VBUS detect pin
+
+ usb0_vbus_power-supply:
+ description: Power supply to detect the USB OTG VBUS
+
+ usb0_vbus-supply:
+ description: Regulator controlling USB OTG VBUS
+
+required:
+ - "#phy-cells"
+ - compatible
+ - clocks
+ - clock-names
+ - reg
+ - reg-names
+ - resets
+ - reset-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/clock/suniv-f1c100s-ccu.h>
+ #include <dt-bindings/reset/suniv-f1c100s-ccu.h>
+
+ phy@1c13400 {
+ compatible = "allwinner,suniv-f1c100s-usb-phy";
+ reg = <0x01c13400 0x10>;
+ reg-names = "phy_ctrl";
+ clocks = <&ccu CLK_USB_PHY0>;
+ clock-names = "usb0_phy";
+ resets = <&ccu RST_USB_PHY0>;
+ reset-names = "usb0_reset";
+ #phy-cells = <1>;
+ usb0_id_det-gpios = <&pio 4 2 GPIO_ACTIVE_HIGH>;
+ };
--
2.36.0
On Wed, 08 Jun 2022 15:04:47 +0800, Icenowy Zheng wrote:
> Allwinner F1C100s has the most simple USB PHY among all Allwinner SoCs,
> because it has only one OTG USB controller, no host-only OHCI/EHCI
> controllers.
>
> Add a binding document for it.
>
> Signed-off-by: Icenowy Zheng <[email protected]>
> ---
> .../phy/allwinner,suniv-f1c100s-usb-phy.yaml | 83 +++++++++++++++++++
> 1 file changed, 83 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.example.dts:19:18: fatal error: dt-bindings/clock/suniv-f1c100s-ccu.h: No such file or directory
19 | #include <dt-bindings/clock/suniv-f1c100s-ccu.h>
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
make[1]: *** [scripts/Makefile.lib:383: Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.example.dtb] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [Makefile:1404: dt_binding_check] Error 2
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
On Wed, Jun 08, 2022 at 03:04:47PM +0800, Icenowy Zheng wrote:
> Allwinner F1C100s has the most simple USB PHY among all Allwinner SoCs,
> because it has only one OTG USB controller, no host-only OHCI/EHCI
> controllers.
>
> Add a binding document for it.
>
> Signed-off-by: Icenowy Zheng <[email protected]>
> ---
> .../phy/allwinner,suniv-f1c100s-usb-phy.yaml | 83 +++++++++++++++++++
> 1 file changed, 83 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml
>
> diff --git a/Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml b/Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml
> new file mode 100644
> index 000000000000..180fa8840bf7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml
> @@ -0,0 +1,83 @@
> +# SPDX-License-Identifier: GPL-2.0
Dual license please.
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/allwinner,suniv-f1c100s-usb-phy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Allwinner F1C100s USB PHY Device Tree Bindings
> +
> +maintainers:
> + - Chen-Yu Tsai <[email protected]>
> + - Maxime Ripard <[email protected]>
> +
> +properties:
> + "#phy-cells":
> + const: 1
> +
> + compatible:
> + const: allwinner,suniv-f1c100s-usb-phy
> +
> + reg:
> + maxItems: 1
> + description: PHY Control registers
> +
> + reg-names:
> + const: phy_ctrl
> +
> + clocks:
> + maxItems: 1
> + description: USB OTG PHY bus clock
> +
> + clock-names:
> + const: usb0_phy
*-names is not needed with only one entry. Plus, just using the module
name is not a great choice.
> +
> + resets:
> + maxItems: 1
> + description: USB OTG reset
> +
> + reset-names:
> + const: usb0_reset
Same here.
> + usb0_id_det-gpios:
> + maxItems: 1
> + description: GPIO to the USB OTG ID pin
> +
> + usb0_vbus_det-gpios:
> + maxItems: 1
> + description: GPIO to the USB OTG VBUS detect pin
> +
> + usb0_vbus_power-supply:
> + description: Power supply to detect the USB OTG VBUS
> +
> + usb0_vbus-supply:
> + description: Regulator controlling USB OTG VBUS
Why the 'usb0_' prefix?
Are these GPIOs and Vbus supply connected to the phy? If not, these all
belong in a connector node (as that is where they are connected to in
h/w).
> +
> +required:
> + - "#phy-cells"
> + - compatible
> + - clocks
> + - clock-names
> + - reg
> + - reg-names
> + - resets
> + - reset-names
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/gpio/gpio.h>
> + #include <dt-bindings/clock/suniv-f1c100s-ccu.h>
> + #include <dt-bindings/reset/suniv-f1c100s-ccu.h>
> +
> + phy@1c13400 {
> + compatible = "allwinner,suniv-f1c100s-usb-phy";
> + reg = <0x01c13400 0x10>;
> + reg-names = "phy_ctrl";
> + clocks = <&ccu CLK_USB_PHY0>;
> + clock-names = "usb0_phy";
> + resets = <&ccu RST_USB_PHY0>;
> + reset-names = "usb0_reset";
> + #phy-cells = <1>;
> + usb0_id_det-gpios = <&pio 4 2 GPIO_ACTIVE_HIGH>;
> + };
> --
> 2.36.0
>
>
在 2022-06-08星期三的 08:49 -0600，Rob Herring写道：
> On Wed, Jun 08, 2022 at 03:04:47PM +0800, Icenowy Zheng wrote:
> > Allwinner F1C100s has the most simple USB PHY among all Allwinner
> > SoCs,
> > because it has only one OTG USB controller, no host-only OHCI/EHCI
> > controllers.
> >
> > Add a binding document for it.
> >
> > Signed-off-by: Icenowy Zheng <[email protected]>
> > ---
> > .../phy/allwinner,suniv-f1c100s-usb-phy.yaml | 83
> > +++++++++++++++++++
> > 1 file changed, 83 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-
> > phy.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/phy/allwinner,suniv-
> > f1c100s-usb-phy.yaml
> > b/Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-
> > usb-phy.yaml
> > new file mode 100644
> > index 000000000000..180fa8840bf7
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/phy/allwinner,suniv-
> > f1c100s-usb-phy.yaml
> > @@ -0,0 +1,83 @@
> > +# SPDX-License-Identifier: GPL-2.0
>
> Dual license please.
I am based on another Allwinner USB PHY binding file in the same
directory, and that file is single licensed. I created a new file
because each variant of the PHY has a single file now.
>
> > +%YAML 1.2
> > +---
> > +$id:
> > http://devicetree.org/schemas/phy/allwinner,suniv-f1c100s-usb-phy.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Allwinner F1C100s USB PHY Device Tree Bindings
> > +
> > +maintainers:
> > + - Chen-Yu Tsai <[email protected]>
> > + - Maxime Ripard <[email protected]>
> > +
> > +properties:
> > + "#phy-cells":
> > + const: 1
> > +
> > + compatible:
> > + const: allwinner,suniv-f1c100s-usb-phy
> > +
> > + reg:
> > + maxItems: 1
> > + description: PHY Control registers
> > +
> > + reg-names:
> > + const: phy_ctrl
> > +
> > + clocks:
> > + maxItems: 1
> > + description: USB OTG PHY bus clock
> > +
> > + clock-names:
> > + const: usb0_phy
>
> *-names is not needed with only one entry. Plus, just using the
> module
> name is not a great choice.
However the driver expects it...
Should I patch the driver to use no name on F1C100s?
>
> > +
> > + resets:
> > + maxItems: 1
> > + description: USB OTG reset
> > +
> > + reset-names:
> > + const: usb0_reset
>
> Same here.
>
> > + usb0_id_det-gpios:
> > + maxItems: 1
> > + description: GPIO to the USB OTG ID pin
> > +
> > + usb0_vbus_det-gpios:
> > + maxItems: 1
> > + description: GPIO to the USB OTG VBUS detect pin
> > +
> > + usb0_vbus_power-supply:
> > + description: Power supply to detect the USB OTG VBUS
> > +
> > + usb0_vbus-supply:
> > + description: Regulator controlling USB OTG VBUS
>
> Why the 'usb0_' prefix?
>
> Are these GPIOs and Vbus supply connected to the phy? If not, these
> all
> belong in a connector node (as that is where they are connected to in
> h/w).
Well these are historical things of phy-sun4i-usb driver too.
>
> > +
> > +required:
> > + - "#phy-cells"
> > + - compatible
> > + - clocks
> > + - clock-names
> > + - reg
> > + - reg-names
> > + - resets
> > + - reset-names
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/gpio/gpio.h>
> > + #include <dt-bindings/clock/suniv-f1c100s-ccu.h>
> > + #include <dt-bindings/reset/suniv-f1c100s-ccu.h>
> > +
> > + phy@1c13400 {
> > + compatible = "allwinner,suniv-f1c100s-usb-phy";
> > + reg = <0x01c13400 0x10>;
> > + reg-names = "phy_ctrl";
> > + clocks = <&ccu CLK_USB_PHY0>;
> > + clock-names = "usb0_phy";
> > + resets = <&ccu RST_USB_PHY0>;
> > + reset-names = "usb0_reset";
> > + #phy-cells = <1>;
> > + usb0_id_det-gpios = <&pio 4 2 GPIO_ACTIVE_HIGH>;
> > + };
> > --
> > 2.36.0
> >
> >
On Wed, Jun 08, 2022 at 10:52:52PM +0800, Icenowy Zheng wrote:
> 在 2022-06-08星期三的 08:49 -0600，Rob Herring写道：
> > On Wed, Jun 08, 2022 at 03:04:47PM +0800, Icenowy Zheng wrote:
> > > Allwinner F1C100s has the most simple USB PHY among all Allwinner
> > > SoCs,
> > > because it has only one OTG USB controller, no host-only OHCI/EHCI
> > > controllers.
> > >
> > > Add a binding document for it.
> > >
> > > Signed-off-by: Icenowy Zheng <[email protected]>
> > > ---
> > > .../phy/allwinner,suniv-f1c100s-usb-phy.yaml | 83
> > > +++++++++++++++++++
> > > 1 file changed, 83 insertions(+)
> > > create mode 100644
> > > Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-
> > > phy.yaml
> > >
> > > diff --git a/Documentation/devicetree/bindings/phy/allwinner,suniv-
> > > f1c100s-usb-phy.yaml
> > > b/Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-
> > > usb-phy.yaml
> > > new file mode 100644
> > > index 000000000000..180fa8840bf7
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/phy/allwinner,suniv-
> > > f1c100s-usb-phy.yaml
> > > @@ -0,0 +1,83 @@
> > > +# SPDX-License-Identifier: GPL-2.0
> >
> > Dual license please.
>
> I am based on another Allwinner USB PHY binding file in the same
> directory, and that file is single licensed. I created a new file
> because each variant of the PHY has a single file now.
Okay, describing the source and the differences in the commit message
would be helpful.
>
> >
> > > +%YAML 1.2
> > > +---
> > > +$id:
> > > http://devicetree.org/schemas/phy/allwinner,suniv-f1c100s-usb-phy.yaml#
> > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > +
> > > +title: Allwinner F1C100s USB PHY Device Tree Bindings
> > > +
> > > +maintainers:
> > > + - Chen-Yu Tsai <[email protected]>
> > > + - Maxime Ripard <[email protected]>
> > > +
> > > +properties:
> > > + "#phy-cells":
> > > + const: 1
> > > +
> > > + compatible:
> > > + const: allwinner,suniv-f1c100s-usb-phy
> > > +
> > > + reg:
> > > + maxItems: 1
> > > + description: PHY Control registers
> > > +
> > > + reg-names:
> > > + const: phy_ctrl
> > > +
> > > + clocks:
> > > + maxItems: 1
> > > + description: USB OTG PHY bus clock
> > > +
> > > + clock-names:
> > > + const: usb0_phy
> >
> > *-names is not needed with only one entry. Plus, just using the
> > module
> > name is not a great choice.
>
> However the driver expects it...
>
> Should I patch the driver to use no name on F1C100s?
>
> >
> > > +
> > > + resets:
> > > + maxItems: 1
> > > + description: USB OTG reset
> > > +
> > > + reset-names:
> > > + const: usb0_reset
> >
> > Same here.
> >
> > > + usb0_id_det-gpios:
> > > + maxItems: 1
> > > + description: GPIO to the USB OTG ID pin
> > > +
> > > + usb0_vbus_det-gpios:
> > > + maxItems: 1
> > > + description: GPIO to the USB OTG VBUS detect pin
> > > +
> > > + usb0_vbus_power-supply:
> > > + description: Power supply to detect the USB OTG VBUS
> > > +
> > > + usb0_vbus-supply:
> > > + description: Regulator controlling USB OTG VBUS
> >
> > Why the 'usb0_' prefix?
> >
> > Are these GPIOs and Vbus supply connected to the phy? If not, these
> > all
> > belong in a connector node (as that is where they are connected to in
> > h/w).
>
> Well these are historical things of phy-sun4i-usb driver too.
Okay, there should perhaps be a common schema so this sharing is clear.
Though longer term there should be a move to the common way of handling
these for new platforms.
So I guess in summary:
Reviewed-by: Rob Herring <[email protected]>