Add device tree bindings for graphics clock controller for
Qualcomm Technology Inc's SM8350 SoCs.
Signed-off-by: Robert Foss <[email protected]>
Reviewed-by: Dmitry Baryshkov <[email protected]>
---
Changes since v3
- Separate from qcom,gpucc
- Remove clock-names
- Make example sm8350 based
- Changed author to me due to size of changes
.../bindings/clock/qcom,gpucc-sm8350.yaml | 72 +++++++++++++++++++
include/dt-bindings/clock/qcom,gpucc-sm8350.h | 52 ++++++++++++++
2 files changed, 124 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,gpucc-sm8350.yaml
create mode 100644 include/dt-bindings/clock/qcom,gpucc-sm8350.h
diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc-sm8350.yaml b/Documentation/devicetree/bindings/clock/qcom,gpucc-sm8350.yaml
new file mode 100644
index 000000000000..0a0546c079a9
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,gpucc-sm8350.yaml
@@ -0,0 +1,72 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,gpucc-sm8350.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Graphics Clock & Reset Controller Binding
+
+maintainers:
+ - Robert Foss <[email protected]>
+
+description: |
+ Qualcomm graphics clock control module which supports the clocks, resets and
+ power domains on Qualcomm SoCs.
+
+ See also:
+ dt-bindings/clock/qcom,gpucc-sm8350.h
+
+properties:
+ compatible:
+ enum:
+ - qcom,sm8350-gpucc
+
+ clocks:
+ items:
+ - description: Board XO source
+ - description: GPLL0 main branch source
+ - description: GPLL0 div branch source
+
+ '#clock-cells':
+ const: 1
+
+ '#reset-cells':
+ const: 1
+
+ '#power-domain-cells':
+ const: 1
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - '#clock-cells'
+ - '#reset-cells'
+ - '#power-domain-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-sm8350.h>
+ #include <dt-bindings/clock/qcom,rpmh.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ clock-controller@3d90000 {
+ compatible = "qcom,sm8350-gpucc";
+ reg = <0 0x03d90000 0 0x9000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_GPU_GPLL0_CLK_SRC>,
+ <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+ };
+...
diff --git a/include/dt-bindings/clock/qcom,gpucc-sm8350.h b/include/dt-bindings/clock/qcom,gpucc-sm8350.h
new file mode 100644
index 000000000000..2ca857f5bfd2
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gpucc-sm8350.h
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2022, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8350_H
+#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8350_H
+
+/* GPU_CC clocks */
+#define GPU_CC_AHB_CLK 0
+#define GPU_CC_CB_CLK 1
+#define GPU_CC_CRC_AHB_CLK 2
+#define GPU_CC_CX_APB_CLK 3
+#define GPU_CC_CX_GMU_CLK 4
+#define GPU_CC_CX_QDSS_AT_CLK 5
+#define GPU_CC_CX_QDSS_TRIG_CLK 6
+#define GPU_CC_CX_QDSS_TSCTR_CLK 7
+#define GPU_CC_CX_SNOC_DVM_CLK 8
+#define GPU_CC_CXO_AON_CLK 9
+#define GPU_CC_CXO_CLK 10
+#define GPU_CC_FREQ_MEASURE_CLK 11
+#define GPU_CC_GMU_CLK_SRC 12
+#define GPU_CC_GX_GMU_CLK 13
+#define GPU_CC_GX_QDSS_TSCTR_CLK 14
+#define GPU_CC_GX_VSENSE_CLK 15
+#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 16
+#define GPU_CC_HUB_AHB_DIV_CLK_SRC 17
+#define GPU_CC_HUB_AON_CLK 18
+#define GPU_CC_HUB_CLK_SRC 19
+#define GPU_CC_HUB_CX_INT_CLK 20
+#define GPU_CC_HUB_CX_INT_DIV_CLK_SRC 21
+#define GPU_CC_MND1X_0_GFX3D_CLK 22
+#define GPU_CC_MND1X_1_GFX3D_CLK 23
+#define GPU_CC_PLL0 24
+#define GPU_CC_PLL1 25
+#define GPU_CC_SLEEP_CLK 26
+
+/* GPU_CC resets */
+#define GPUCC_GPU_CC_ACD_BCR 0
+#define GPUCC_GPU_CC_CB_BCR 1
+#define GPUCC_GPU_CC_CX_BCR 2
+#define GPUCC_GPU_CC_FAST_HUB_BCR 3
+#define GPUCC_GPU_CC_GFX3D_AON_BCR 4
+#define GPUCC_GPU_CC_GMU_BCR 5
+#define GPUCC_GPU_CC_GX_BCR 6
+#define GPUCC_GPU_CC_XO_BCR 7
+
+/* GPU_CC GDSCRs */
+#define GPU_CX_GDSC 0
+#define GPU_GX_GDSC 1
+
+#endif
--
2.34.1
Hi Robert,
I love your patch! Yet something to improve:
[auto build test ERROR on clk/clk-next]
[also build test ERROR on robh/for-next v5.19-rc1 next-20220610]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/intel-lab-lkp/linux/commits/Robert-Foss/SM8350-Display-GPU-clock-enablement/20220609-173149
base: https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next
config: arm64-buildonly-randconfig-r005-20220611 (https://download.01.org/0day-ci/archive/20220612/[email protected]/config)
compiler: clang version 15.0.0 (https://github.com/llvm/llvm-project ff4abe755279a3a47cc416ef80dbc900d9a98a19)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install arm64 cross compiling tool for clang build
# apt-get install binutils-aarch64-linux-gnu
# https://github.com/intel-lab-lkp/linux/commit/e7acd4b7cc95e3f3ffaa4782f09245b44d4faa31
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Robert-Foss/SM8350-Display-GPU-clock-enablement/20220609-173149
git checkout e7acd4b7cc95e3f3ffaa4782f09245b44d4faa31
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=arm64 SHELL=/bin/bash drivers/clk/qcom/
If you fix the issue, kindly add following tag where applicable
Reported-by: kernel test robot <[email protected]>
All errors (new ones prefixed by >>):
>> drivers/clk/qcom/gpucc-sm8350.c:111:2: error: initializer element is not a compile-time constant
gpu_cc_parent,
^~~~~~~~~~~~~
drivers/clk/qcom/gpucc-sm8350.c:126:2: error: initializer element is not a compile-time constant
gpu_cc_parent,
^~~~~~~~~~~~~
2 errors generated.
vim +111 drivers/clk/qcom/gpucc-sm8350.c
05334fe2099d9b Robert Foss 2022-06-09 109
05334fe2099d9b Robert Foss 2022-06-09 110 static const struct clk_parent_data gpu_cc_parent_data_0[] = {
05334fe2099d9b Robert Foss 2022-06-09 @111 gpu_cc_parent,
05334fe2099d9b Robert Foss 2022-06-09 112 { .hw = &gpu_cc_pll0.clkr.hw },
05334fe2099d9b Robert Foss 2022-06-09 113 { .hw = &gpu_cc_pll1.clkr.hw },
05334fe2099d9b Robert Foss 2022-06-09 114 { .fw_name = "gcc_gpu_gpll0_clk_src" },
05334fe2099d9b Robert Foss 2022-06-09 115 { .fw_name = "gcc_gpu_gpll0_div_clk_src" },
05334fe2099d9b Robert Foss 2022-06-09 116 };
05334fe2099d9b Robert Foss 2022-06-09 117
--
0-DAY CI Kernel Test Service
https://01.org/lkp
On Thu, 09 Jun 2022 11:29:37 +0200, Robert Foss wrote:
> Add device tree bindings for graphics clock controller for
> Qualcomm Technology Inc's SM8350 SoCs.
>
> Signed-off-by: Robert Foss <[email protected]>
> Reviewed-by: Dmitry Baryshkov <[email protected]>
> ---
>
> Changes since v3
> - Separate from qcom,gpucc
> - Remove clock-names
> - Make example sm8350 based
> - Changed author to me due to size of changes
>
>
>
> .../bindings/clock/qcom,gpucc-sm8350.yaml | 72 +++++++++++++++++++
> include/dt-bindings/clock/qcom,gpucc-sm8350.h | 52 ++++++++++++++
> 2 files changed, 124 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/qcom,gpucc-sm8350.yaml
> create mode 100644 include/dt-bindings/clock/qcom,gpucc-sm8350.h
>
Reviewed-by: Rob Herring <[email protected]>