This series is based on top of Jernej series: "media: hantro: Add 10-bit
support" v2.
Jernej series is focusing on VP9 and hardware block with legacy regs.
This one add 10bits support for newer hardware blocks (i.e without
legacy regs) and for HEVC codec.
It based tested on IMX8MQ with HEVC conformance tests.
The results are that all 10bits bitstreams are OK.
Benjamin Gaignard (7):
media: hantro: Store HEVC bit depth in context
media: hantro: HEVC: Fix auxilary buffer size calculation
media: hantro: HEVC: Fix chroma offset computation
media: hantro: postproc: Configure output regs to support 10bit
media: Hantro: HEVC: Allows 10-bit bitstream
media: hantro: imx8m: Enable 10bit decoding
media: hantro: Allows luma and chroma depth to be different
.../staging/media/hantro/hantro_g2_hevc_dec.c | 4 +--
drivers/staging/media/hantro/hantro_hevc.c | 13 +++++----
.../staging/media/hantro/hantro_postproc.c | 7 ++++-
drivers/staging/media/hantro/imx8m_vpu_hw.c | 27 +++++++++++++++++++
4 files changed, 40 insertions(+), 11 deletions(-)
--
2.32.0
Stop limiting HEVC support to 8-bits bitstreams also
accept 10-bits bitstreams.
Signed-off-by: Benjamin Gaignard <[email protected]>
---
drivers/staging/media/hantro/hantro_hevc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/staging/media/hantro/hantro_hevc.c b/drivers/staging/media/hantro/hantro_hevc.c
index e06837108a09..85688a4df166 100644
--- a/drivers/staging/media/hantro/hantro_hevc.c
+++ b/drivers/staging/media/hantro/hantro_hevc.c
@@ -159,8 +159,8 @@ int hantro_hevc_validate_sps(struct hantro_ctx *ctx, const struct v4l2_ctrl_hevc
if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8)
/* Luma and chroma bit depth mismatch */
return -EINVAL;
- if (sps->bit_depth_luma_minus8 != 0)
- /* Only 8-bit is supported */
+ if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2)
+ /* Only 8-bit and 10-bit is supported */
return -EINVAL;
ctx->bit_depth = sps->bit_depth_luma_minus8 + 8;
--
2.32.0
Store HEVC bit depth in context.
Bit depth is equal to hevc sps bit_depth_luma_minus8 + 8.
Signed-off-by: Benjamin Gaignard <[email protected]>
---
drivers/staging/media/hantro/hantro_hevc.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/staging/media/hantro/hantro_hevc.c b/drivers/staging/media/hantro/hantro_hevc.c
index 5984c5fa6f83..dcb5c8703b6e 100644
--- a/drivers/staging/media/hantro/hantro_hevc.c
+++ b/drivers/staging/media/hantro/hantro_hevc.c
@@ -163,6 +163,8 @@ int hantro_hevc_validate_sps(struct hantro_ctx *ctx, const struct v4l2_ctrl_hevc
/* Only 8-bit is supported */
return -EINVAL;
+ ctx->bit_depth = sps->bit_depth_luma_minus8 + 8;
+
/*
* for tile pixel format check if the width and height match
* hardware constraints
--
2.32.0
SAO and FILTER buffers size depend of the bit depth.
Make sure we have enough space for 10bit bitstreams.
Signed-off-by: Benjamin Gaignard <[email protected]>
---
drivers/staging/media/hantro/hantro_hevc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/staging/media/hantro/hantro_hevc.c b/drivers/staging/media/hantro/hantro_hevc.c
index dcb5c8703b6e..e06837108a09 100644
--- a/drivers/staging/media/hantro/hantro_hevc.c
+++ b/drivers/staging/media/hantro/hantro_hevc.c
@@ -104,7 +104,7 @@ static int tile_buffer_reallocate(struct hantro_ctx *ctx)
hevc_dec->tile_bsd.cpu = NULL;
}
- size = VERT_FILTER_RAM_SIZE * height64 * (num_tile_cols - 1);
+ size = (VERT_FILTER_RAM_SIZE * height64 * (num_tile_cols - 1) * ctx->bit_depth) / 8;
hevc_dec->tile_filter.cpu = dma_alloc_coherent(vpu->dev, size,
&hevc_dec->tile_filter.dma,
GFP_KERNEL);
@@ -112,7 +112,7 @@ static int tile_buffer_reallocate(struct hantro_ctx *ctx)
goto err_free_tile_buffers;
hevc_dec->tile_filter.size = size;
- size = VERT_SAO_RAM_SIZE * height64 * (num_tile_cols - 1);
+ size = (VERT_SAO_RAM_SIZE * height64 * (num_tile_cols - 1) * ctx->bit_depth) / 8;
hevc_dec->tile_sao.cpu = dma_alloc_coherent(vpu->dev, size,
&hevc_dec->tile_sao.dma,
GFP_KERNEL);
--
2.32.0
Expose 10bit pixel formats to enable 10bit decoding in IMX8M SoCs.
Signed-off-by: Benjamin Gaignard <[email protected]>
---
drivers/staging/media/hantro/imx8m_vpu_hw.c | 27 +++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/drivers/staging/media/hantro/imx8m_vpu_hw.c b/drivers/staging/media/hantro/imx8m_vpu_hw.c
index 77f574fdfa77..b390228fd3b4 100644
--- a/drivers/staging/media/hantro/imx8m_vpu_hw.c
+++ b/drivers/staging/media/hantro/imx8m_vpu_hw.c
@@ -162,12 +162,39 @@ static const struct hantro_fmt imx8m_vpu_g2_postproc_fmts[] = {
.step_height = MB_DIM,
},
},
+ {
+ .fourcc = V4L2_PIX_FMT_P010,
+ .codec_mode = HANTRO_MODE_NONE,
+ .postprocessed = true,
+ .frmsize = {
+ .min_width = FMT_MIN_WIDTH,
+ .max_width = FMT_UHD_WIDTH,
+ .step_width = MB_DIM,
+ .min_height = FMT_MIN_HEIGHT,
+ .max_height = FMT_UHD_HEIGHT,
+ .step_height = MB_DIM,
+ },
+ },
};
static const struct hantro_fmt imx8m_vpu_g2_dec_fmts[] = {
{
.fourcc = V4L2_PIX_FMT_NV12_4L4,
.codec_mode = HANTRO_MODE_NONE,
+ .match_depth = true,
+ .frmsize = {
+ .min_width = FMT_MIN_WIDTH,
+ .max_width = FMT_UHD_WIDTH,
+ .step_width = TILE_MB_DIM,
+ .min_height = FMT_MIN_HEIGHT,
+ .max_height = FMT_UHD_HEIGHT,
+ .step_height = TILE_MB_DIM,
+ },
+ },
+ {
+ .fourcc = V4L2_PIX_FMT_P010_4L4,
+ .codec_mode = HANTRO_MODE_NONE,
+ .match_depth = true,
.frmsize = {
.min_width = FMT_MIN_WIDTH,
.max_width = FMT_UHD_WIDTH,
--
2.32.0
The chroma offset depends of the bitstream depth.
Make sure that ctx->bit_depth is used to compute it.
Signed-off-by: Benjamin Gaignard <[email protected]>
---
drivers/staging/media/hantro/hantro_g2_hevc_dec.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/staging/media/hantro/hantro_g2_hevc_dec.c b/drivers/staging/media/hantro/hantro_g2_hevc_dec.c
index 9eac133bda68..8407ad45b7b7 100644
--- a/drivers/staging/media/hantro/hantro_g2_hevc_dec.c
+++ b/drivers/staging/media/hantro/hantro_g2_hevc_dec.c
@@ -12,7 +12,7 @@
static size_t hantro_hevc_chroma_offset(struct hantro_ctx *ctx)
{
- return ctx->dst_fmt.width * ctx->dst_fmt.height;
+ return ctx->dst_fmt.width * ctx->dst_fmt.height * ctx->bit_depth / 8;
}
static size_t hantro_hevc_motion_vectors_offset(struct hantro_ctx *ctx)
--
2.32.0
Hi Benjamin,
On Fri, Jun 17, 2022 at 01:57:58PM +0200, Benjamin Gaignard wrote:
> The chroma offset depends of the bitstream depth.
> Make sure that ctx->bit_depth is used to compute it.
>
> Signed-off-by: Benjamin Gaignard <[email protected]>
Reviewed-by: Ezequiel Garcia <[email protected]>
Thanks,
Ezequiel
> ---
> drivers/staging/media/hantro/hantro_g2_hevc_dec.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/staging/media/hantro/hantro_g2_hevc_dec.c b/drivers/staging/media/hantro/hantro_g2_hevc_dec.c
> index 9eac133bda68..8407ad45b7b7 100644
> --- a/drivers/staging/media/hantro/hantro_g2_hevc_dec.c
> +++ b/drivers/staging/media/hantro/hantro_g2_hevc_dec.c
> @@ -12,7 +12,7 @@
>
> static size_t hantro_hevc_chroma_offset(struct hantro_ctx *ctx)
> {
> - return ctx->dst_fmt.width * ctx->dst_fmt.height;
> + return ctx->dst_fmt.width * ctx->dst_fmt.height * ctx->bit_depth / 8;
> }
>
> static size_t hantro_hevc_motion_vectors_offset(struct hantro_ctx *ctx)
> --
> 2.32.0
>
Hi Benjamin,
On Fri, Jun 17, 2022 at 01:57:57PM +0200, Benjamin Gaignard wrote:
> SAO and FILTER buffers size depend of the bit depth.
> Make sure we have enough space for 10bit bitstreams.
>
> Signed-off-by: Benjamin Gaignard <[email protected]>
Reviewed-by: Ezequiel Garcia <[email protected]>
Thanks,
Ezequiel
> ---
> drivers/staging/media/hantro/hantro_hevc.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/staging/media/hantro/hantro_hevc.c b/drivers/staging/media/hantro/hantro_hevc.c
> index dcb5c8703b6e..e06837108a09 100644
> --- a/drivers/staging/media/hantro/hantro_hevc.c
> +++ b/drivers/staging/media/hantro/hantro_hevc.c
> @@ -104,7 +104,7 @@ static int tile_buffer_reallocate(struct hantro_ctx *ctx)
> hevc_dec->tile_bsd.cpu = NULL;
> }
>
> - size = VERT_FILTER_RAM_SIZE * height64 * (num_tile_cols - 1);
> + size = (VERT_FILTER_RAM_SIZE * height64 * (num_tile_cols - 1) * ctx->bit_depth) / 8;
> hevc_dec->tile_filter.cpu = dma_alloc_coherent(vpu->dev, size,
> &hevc_dec->tile_filter.dma,
> GFP_KERNEL);
> @@ -112,7 +112,7 @@ static int tile_buffer_reallocate(struct hantro_ctx *ctx)
> goto err_free_tile_buffers;
> hevc_dec->tile_filter.size = size;
>
> - size = VERT_SAO_RAM_SIZE * height64 * (num_tile_cols - 1);
> + size = (VERT_SAO_RAM_SIZE * height64 * (num_tile_cols - 1) * ctx->bit_depth) / 8;
> hevc_dec->tile_sao.cpu = dma_alloc_coherent(vpu->dev, size,
> &hevc_dec->tile_sao.dma,
> GFP_KERNEL);
> --
> 2.32.0
>
Hi Benjamin,
On Fri, Jun 17, 2022 at 01:58:00PM +0200, Benjamin Gaignard wrote:
> Stop limiting HEVC support to 8-bits bitstreams also
> accept 10-bits bitstreams.
>
> Signed-off-by: Benjamin Gaignard <[email protected]>
> ---
> drivers/staging/media/hantro/hantro_hevc.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/staging/media/hantro/hantro_hevc.c b/drivers/staging/media/hantro/hantro_hevc.c
> index e06837108a09..85688a4df166 100644
> --- a/drivers/staging/media/hantro/hantro_hevc.c
> +++ b/drivers/staging/media/hantro/hantro_hevc.c
> @@ -159,8 +159,8 @@ int hantro_hevc_validate_sps(struct hantro_ctx *ctx, const struct v4l2_ctrl_hevc
I'd like to go back to checking the SPS control directly
in hantro_try_ctrl. I believe the best and most reasonable
place to validate the controls would be TRY_CTRL.
See https://patchwork.linuxtv.org/project/linux-media/patch/[email protected]/.
> if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8)
> /* Luma and chroma bit depth mismatch */
> return -EINVAL;
> - if (sps->bit_depth_luma_minus8 != 0)
> - /* Only 8-bit is supported */
> + if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2)
> + /* Only 8-bit and 10-bit is supported */
Having said that, the change looks good:
Reviewed-by: Ezequiel Garcia <[email protected]>
Thanks,
Ezequiel
> return -EINVAL;
>
> ctx->bit_depth = sps->bit_depth_luma_minus8 + 8;
> --
> 2.32.0
>
Hi Benjamin,
Thanks for the patch.
On Fri, Jun 17, 2022 at 01:57:56PM +0200, Benjamin Gaignard wrote:
> Store HEVC bit depth in context.
> Bit depth is equal to hevc sps bit_depth_luma_minus8 + 8.
>
> Signed-off-by: Benjamin Gaignard <[email protected]>
> ---
> drivers/staging/media/hantro/hantro_hevc.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/staging/media/hantro/hantro_hevc.c b/drivers/staging/media/hantro/hantro_hevc.c
> index 5984c5fa6f83..dcb5c8703b6e 100644
> --- a/drivers/staging/media/hantro/hantro_hevc.c
> +++ b/drivers/staging/media/hantro/hantro_hevc.c
> @@ -163,6 +163,8 @@ int hantro_hevc_validate_sps(struct hantro_ctx *ctx, const struct v4l2_ctrl_hevc
> /* Only 8-bit is supported */
> return -EINVAL;
>
> + ctx->bit_depth = sps->bit_depth_luma_minus8 + 8;
> +
This should set in hantro_hevc_s_ctrl.
Thanks!
Ezequiel
> /*
> * for tile pixel format check if the width and height match
> * hardware constraints
> --
> 2.32.0
>
Hi Benjamin,
On Fri, Jun 17, 2022 at 01:58:01PM +0200, Benjamin Gaignard wrote:
> Expose 10bit pixel formats to enable 10bit decoding in IMX8M SoCs.
>
> Signed-off-by: Benjamin Gaignard <[email protected]>
Looks good to me.
Reviewed-by: Ezequiel Garcia <[email protected]>
Have you checked Fluster tests passess using both P010 and P010_4L4?
It would be good to double-check.
Thanks a lot,
Ezequiel
> ---
> drivers/staging/media/hantro/imx8m_vpu_hw.c | 27 +++++++++++++++++++++
> 1 file changed, 27 insertions(+)
>
> diff --git a/drivers/staging/media/hantro/imx8m_vpu_hw.c b/drivers/staging/media/hantro/imx8m_vpu_hw.c
> index 77f574fdfa77..b390228fd3b4 100644
> --- a/drivers/staging/media/hantro/imx8m_vpu_hw.c
> +++ b/drivers/staging/media/hantro/imx8m_vpu_hw.c
> @@ -162,12 +162,39 @@ static const struct hantro_fmt imx8m_vpu_g2_postproc_fmts[] = {
> .step_height = MB_DIM,
> },
> },
> + {
> + .fourcc = V4L2_PIX_FMT_P010,
> + .codec_mode = HANTRO_MODE_NONE,
> + .postprocessed = true,
> + .frmsize = {
> + .min_width = FMT_MIN_WIDTH,
> + .max_width = FMT_UHD_WIDTH,
> + .step_width = MB_DIM,
> + .min_height = FMT_MIN_HEIGHT,
> + .max_height = FMT_UHD_HEIGHT,
> + .step_height = MB_DIM,
> + },
> + },
> };
>
> static const struct hantro_fmt imx8m_vpu_g2_dec_fmts[] = {
> {
> .fourcc = V4L2_PIX_FMT_NV12_4L4,
> .codec_mode = HANTRO_MODE_NONE,
> + .match_depth = true,
> + .frmsize = {
> + .min_width = FMT_MIN_WIDTH,
> + .max_width = FMT_UHD_WIDTH,
> + .step_width = TILE_MB_DIM,
> + .min_height = FMT_MIN_HEIGHT,
> + .max_height = FMT_UHD_HEIGHT,
> + .step_height = TILE_MB_DIM,
> + },
> + },
> + {
> + .fourcc = V4L2_PIX_FMT_P010_4L4,
> + .codec_mode = HANTRO_MODE_NONE,
> + .match_depth = true,
> .frmsize = {
> .min_width = FMT_MIN_WIDTH,
> .max_width = FMT_UHD_WIDTH,
> --
> 2.32.0
>
Le 30/06/2022 à 19:40, Ezequiel Garcia a écrit :
> Hi Benjamin,
>
> On Fri, Jun 17, 2022 at 01:58:01PM +0200, Benjamin Gaignard wrote:
>> Expose 10bit pixel formats to enable 10bit decoding in IMX8M SoCs.
>>
>> Signed-off-by: Benjamin Gaignard <[email protected]>
> Looks good to me.
>
> Reviewed-by: Ezequiel Garcia <[email protected]>
>
> Have you checked Fluster tests passess using both P010 and P010_4L4?
> It would be good to double-check.
It isn't possible to check P010_4L4 with fluster because GStreamer
videoconvert element doesn't support this format.
Regards,
Benjamin
>
> Thanks a lot,
> Ezequiel
>
>> ---
>> drivers/staging/media/hantro/imx8m_vpu_hw.c | 27 +++++++++++++++++++++
>> 1 file changed, 27 insertions(+)
>>
>> diff --git a/drivers/staging/media/hantro/imx8m_vpu_hw.c b/drivers/staging/media/hantro/imx8m_vpu_hw.c
>> index 77f574fdfa77..b390228fd3b4 100644
>> --- a/drivers/staging/media/hantro/imx8m_vpu_hw.c
>> +++ b/drivers/staging/media/hantro/imx8m_vpu_hw.c
>> @@ -162,12 +162,39 @@ static const struct hantro_fmt imx8m_vpu_g2_postproc_fmts[] = {
>> .step_height = MB_DIM,
>> },
>> },
>> + {
>> + .fourcc = V4L2_PIX_FMT_P010,
>> + .codec_mode = HANTRO_MODE_NONE,
>> + .postprocessed = true,
>> + .frmsize = {
>> + .min_width = FMT_MIN_WIDTH,
>> + .max_width = FMT_UHD_WIDTH,
>> + .step_width = MB_DIM,
>> + .min_height = FMT_MIN_HEIGHT,
>> + .max_height = FMT_UHD_HEIGHT,
>> + .step_height = MB_DIM,
>> + },
>> + },
>> };
>>
>> static const struct hantro_fmt imx8m_vpu_g2_dec_fmts[] = {
>> {
>> .fourcc = V4L2_PIX_FMT_NV12_4L4,
>> .codec_mode = HANTRO_MODE_NONE,
>> + .match_depth = true,
>> + .frmsize = {
>> + .min_width = FMT_MIN_WIDTH,
>> + .max_width = FMT_UHD_WIDTH,
>> + .step_width = TILE_MB_DIM,
>> + .min_height = FMT_MIN_HEIGHT,
>> + .max_height = FMT_UHD_HEIGHT,
>> + .step_height = TILE_MB_DIM,
>> + },
>> + },
>> + {
>> + .fourcc = V4L2_PIX_FMT_P010_4L4,
>> + .codec_mode = HANTRO_MODE_NONE,
>> + .match_depth = true,
>> .frmsize = {
>> .min_width = FMT_MIN_WIDTH,
>> .max_width = FMT_UHD_WIDTH,
>> --
>> 2.32.0
>>
Hi Benjamin,
On Fri 17 Jun 22, 13:57, Benjamin Gaignard wrote:
> The chroma offset depends of the bitstream depth.
> Make sure that ctx->bit_depth is used to compute it.
>
> Signed-off-by: Benjamin Gaignard <[email protected]>
> ---
> drivers/staging/media/hantro/hantro_g2_hevc_dec.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/staging/media/hantro/hantro_g2_hevc_dec.c b/drivers/staging/media/hantro/hantro_g2_hevc_dec.c
> index 9eac133bda68..8407ad45b7b7 100644
> --- a/drivers/staging/media/hantro/hantro_g2_hevc_dec.c
> +++ b/drivers/staging/media/hantro/hantro_g2_hevc_dec.c
> @@ -12,7 +12,7 @@
>
> static size_t hantro_hevc_chroma_offset(struct hantro_ctx *ctx)
> {
> - return ctx->dst_fmt.width * ctx->dst_fmt.height;
> + return ctx->dst_fmt.width * ctx->dst_fmt.height * ctx->bit_depth / 8;
Is this a case for DIV_ROUND_UP or are you sure the rounded-down size is always
sufficient?
Cheers,
Paul
> }
>
> static size_t hantro_hevc_motion_vectors_offset(struct hantro_ctx *ctx)
> --
> 2.32.0
>
--
Paul Kocialkowski, Bootlin
Embedded Linux and kernel engineering
https://bootlin.com
Le 01/07/2022 à 10:47, Paul Kocialkowski a écrit :
> Hi Benjamin,
>
> On Fri 17 Jun 22, 13:57, Benjamin Gaignard wrote:
>> The chroma offset depends of the bitstream depth.
>> Make sure that ctx->bit_depth is used to compute it.
>>
>> Signed-off-by: Benjamin Gaignard <[email protected]>
>> ---
>> drivers/staging/media/hantro/hantro_g2_hevc_dec.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/staging/media/hantro/hantro_g2_hevc_dec.c b/drivers/staging/media/hantro/hantro_g2_hevc_dec.c
>> index 9eac133bda68..8407ad45b7b7 100644
>> --- a/drivers/staging/media/hantro/hantro_g2_hevc_dec.c
>> +++ b/drivers/staging/media/hantro/hantro_g2_hevc_dec.c
>> @@ -12,7 +12,7 @@
>>
>> static size_t hantro_hevc_chroma_offset(struct hantro_ctx *ctx)
>> {
>> - return ctx->dst_fmt.width * ctx->dst_fmt.height;
>> + return ctx->dst_fmt.width * ctx->dst_fmt.height * ctx->bit_depth / 8;
> Is this a case for DIV_ROUND_UP or are you sure the rounded-down size is always
> sufficient?
No need of DIV_ROUND_UP here because it could affect the chroma offset when
using decoder tiled format and add extra bytes between luma and chroma planes.
Regards,
Benjamin
> Cheers,
>
> Paul
>
>> }
>>
>> static size_t hantro_hevc_motion_vectors_offset(struct hantro_ctx *ctx)
>> --
>> 2.32.0
>>
Le vendredi 01 juillet 2022 à 09:01 +0200, Benjamin Gaignard a écrit :
> Le 30/06/2022 à 19:40, Ezequiel Garcia a écrit :
> > Hi Benjamin,
> >
> > On Fri, Jun 17, 2022 at 01:58:01PM +0200, Benjamin Gaignard wrote:
> > > Expose 10bit pixel formats to enable 10bit decoding in IMX8M SoCs.
> > >
> > > Signed-off-by: Benjamin Gaignard <[email protected]>
> > Looks good to me.
> >
> > Reviewed-by: Ezequiel Garcia <[email protected]>
> >
> > Have you checked Fluster tests passess using both P010 and P010_4L4?
> > It would be good to double-check.
>
> It isn't possible to check P010_4L4 with fluster because GStreamer
> videoconvert element doesn't support this format.
I can offert to work on this. If you can send me offline some picture dump, so I
can validate, that would help.
>
> Regards,
> Benjamin
>
> >
> > Thanks a lot,
> > Ezequiel
> >
> > > ---
> > > drivers/staging/media/hantro/imx8m_vpu_hw.c | 27 +++++++++++++++++++++
> > > 1 file changed, 27 insertions(+)
> > >
> > > diff --git a/drivers/staging/media/hantro/imx8m_vpu_hw.c b/drivers/staging/media/hantro/imx8m_vpu_hw.c
> > > index 77f574fdfa77..b390228fd3b4 100644
> > > --- a/drivers/staging/media/hantro/imx8m_vpu_hw.c
> > > +++ b/drivers/staging/media/hantro/imx8m_vpu_hw.c
> > > @@ -162,12 +162,39 @@ static const struct hantro_fmt imx8m_vpu_g2_postproc_fmts[] = {
> > > .step_height = MB_DIM,
> > > },
> > > },
> > > + {
> > > + .fourcc = V4L2_PIX_FMT_P010,
> > > + .codec_mode = HANTRO_MODE_NONE,
> > > + .postprocessed = true,
> > > + .frmsize = {
> > > + .min_width = FMT_MIN_WIDTH,
> > > + .max_width = FMT_UHD_WIDTH,
> > > + .step_width = MB_DIM,
> > > + .min_height = FMT_MIN_HEIGHT,
> > > + .max_height = FMT_UHD_HEIGHT,
> > > + .step_height = MB_DIM,
> > > + },
> > > + },
> > > };
> > >
> > > static const struct hantro_fmt imx8m_vpu_g2_dec_fmts[] = {
> > > {
> > > .fourcc = V4L2_PIX_FMT_NV12_4L4,
> > > .codec_mode = HANTRO_MODE_NONE,
> > > + .match_depth = true,
> > > + .frmsize = {
> > > + .min_width = FMT_MIN_WIDTH,
> > > + .max_width = FMT_UHD_WIDTH,
> > > + .step_width = TILE_MB_DIM,
> > > + .min_height = FMT_MIN_HEIGHT,
> > > + .max_height = FMT_UHD_HEIGHT,
> > > + .step_height = TILE_MB_DIM,
> > > + },
> > > + },
> > > + {
> > > + .fourcc = V4L2_PIX_FMT_P010_4L4,
> > > + .codec_mode = HANTRO_MODE_NONE,
> > > + .match_depth = true,
> > > .frmsize = {
> > > .min_width = FMT_MIN_WIDTH,
> > > .max_width = FMT_UHD_WIDTH,
> > > --
> > > 2.32.0
> > >