This patch series converts atmel-flexcom bindings into json-schema format.
Adds support for lan966x flexcom chip-select configurations and its
DT bindings.
v4 -> v5:
- Fix indentations of DT example.
- Fix dt-schema errors - removed minItems, maxItems for allOf:if:then
"reg" property as it is not required.
v3 -> v4:
- Fix dtschema errors.
- Add a condition to flexcom chip-selects configuration as chip-select
lines are optional.
v2 -> v3:
- changed IRQ flag in dt-bindings example.
- added reg property specific to lan66x which is missed in v2.
- used goto label for clk_disable in error cases.
v1 -> v2:
- minor fix in title of dt-bindings.
- Modified new dt properties usage in atmel,flexcom.yaml.
- Used GENMASK and macros for maximum allowed values.
- Use u32 values for flexcom chipselects instead of strings.
- disable clock in case of errors.
Kavyasree Kotagiri (3):
dt-bindings: mfd: atmel,flexcom: Convert to json-schema
dt-bindings: mfd: atmel,flexcom: Add new compatible string for lan966x
mfd: atmel-flexcom: Add support for lan966x flexcom chip-select
configuration
.../bindings/mfd/atmel,flexcom.yaml | 180 ++++++++++++++++++
.../devicetree/bindings/mfd/atmel-flexcom.txt | 63 ------
drivers/mfd/atmel-flexcom.c | 94 ++++++++-
3 files changed, 273 insertions(+), 64 deletions(-)
create mode 100644 Documentation/devicetree/bindings/mfd/atmel,flexcom.yaml
delete mode 100644 Documentation/devicetree/bindings/mfd/atmel-flexcom.txt
--
2.17.1
LAN966x SoC flexcoms has two optional I/O lines. Namely, CS0 and CS1
in flexcom SPI mode. CTS and RTS in flexcom USART mode. These pins
can be mapped to lan966x FLEXCOM_SHARED[0-20] pins and usage depends on
functions being configured.
Signed-off-by: Kavyasree Kotagiri <[email protected]>
---
v4 -> v5:
- Fixed indentations and dt-schema errors.
- No errors seen with 'make dt_binding_check'.
v3 -> v4:
- Added else condition to allOf:if:then.
v2 -> v3:
- Add reg property of lan966x missed in v2.
v1 -> v2:
- Use allOf:if:then for lan966x dt properties
.../bindings/mfd/atmel,flexcom.yaml | 78 ++++++++++++++++++-
1 file changed, 77 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/mfd/atmel,flexcom.yaml b/Documentation/devicetree/bindings/mfd/atmel,flexcom.yaml
index fc5af946b568..216d08b44bb3 100644
--- a/Documentation/devicetree/bindings/mfd/atmel,flexcom.yaml
+++ b/Documentation/devicetree/bindings/mfd/atmel,flexcom.yaml
@@ -18,9 +18,11 @@ properties:
compatible:
enum:
- atmel,sama5d2-flexcom
+ - microchip,lan966x-flexcom
reg:
- maxItems: 1
+ minItems: 1
+ maxItems: 2
clocks:
maxItems: 1
@@ -47,6 +49,27 @@ properties:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [1, 2, 3]
+ microchip,flx-shrd-pins:
+ description: Specify the Flexcom shared pins to be used for flexcom
+ chip-selects.
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ minItems: 1
+ maxItems: 2
+ items:
+ minimum: 0
+ maximum: 20
+
+ microchip,flx-cs:
+ description: Flexcom chip selects. Here, value of '0' represents "cts" line
+ of flexcom USART or "cs0" line of flexcom SPI and value of '1' represents
+ "rts" line of flexcom USART or "cs1" line of flexcom SPI.
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ minItems: 1
+ maxItems: 2
+ items:
+ minimum: 0
+ maximum: 1
+
patternProperties:
"^serial@[0-9a-f]+$":
description: See atmel-usart.txt for details of USART bindings.
@@ -73,6 +96,31 @@ required:
- ranges
- atmel,flexcom-mode
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: microchip,lan966x-flexcom
+
+ then:
+ properties:
+ reg:
+ items:
+ - description: Flexcom base registers map
+ - description: Flexcom shared registers map
+ required:
+ - microchip,flx-shrd-pins
+ - microchip,flx-cs
+
+ else:
+ properties:
+ reg:
+ items:
+ - description: Flexcom base registers map
+ microchip,flx-shrd-pins: false
+ microchip,flx-cs: false
+
additionalProperties: false
examples:
@@ -101,4 +149,32 @@ examples:
atmel,fifo-size = <32>;
};
};
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ flx3: flexcom@e0064000 {
+ compatible = "microchip,lan966x-flexcom";
+ reg = <0xe0064000 0x100>,
+ <0xe2004180 0x8>;
+ clocks = <&flx0_clk>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xe0040000 0x800>;
+ atmel,flexcom-mode = <2>;
+ microchip,flx-shrd-pins = <9>;
+ microchip,flx-cs = <0>;
+
+ spi3: spi@400 {
+ compatible = "atmel,at91rm9200-spi";
+ reg = <0x400 0x200>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flx3_default>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&nic_clk>;
+ clock-names = "spi_clk";
+ atmel,fifo-size = <32>;
+ };
+ };
...
--
2.17.1
On 20/06/2022 16:46, Kavyasree Kotagiri wrote:
> LAN966x SoC flexcoms has two optional I/O lines. Namely, CS0 and CS1
> in flexcom SPI mode. CTS and RTS in flexcom USART mode. These pins
> can be mapped to lan966x FLEXCOM_SHARED[0-20] pins and usage depends on
> functions being configured.
>
> Signed-off-by: Kavyasree Kotagiri <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof