2022-06-21 11:53:59

by Bharat Kumar Gogada

[permalink] [raw]
Subject: [PATCH v5 0/2] Add support for Xilinx Versal CPM5 Root Port

Xilinx Versal Premium series has CPM5 block which supports Root Port
functioning at Gen5 speed.

Xilinx Versal CPM5 has few changes with existing CPM block.
- CPM5 has dedicated register space for control and status registers.
- CPM5 legacy interrupt handling needs additonal register bit
to enable and handle legacy interrupts.

Changes in v5:
- Added of_device_get_match_data to identify CPM version.


Bharat Kumar Gogada (2):
dt-bindings: PCI: xilinx-cpm: Add Versal CPM5 Root Port
PCI: xilinx-cpm: Add support for Versal CPM5 Root Port

.../bindings/pci/xilinx-versal-cpm.yaml | 48 ++++++++++++--
drivers/pci/controller/pcie-xilinx-cpm.c | 62 ++++++++++++++++++-
2 files changed, 103 insertions(+), 7 deletions(-)

--
2.17.1


2022-06-21 11:58:41

by Bharat Kumar Gogada

[permalink] [raw]
Subject: [PATCH v5 1/2] dt-bindings: PCI: xilinx-cpm: Add Versal CPM5 Root Port

Xilinx Versal Premium series has CPM5 block which supports Root Port
functionality at Gen5 speed.

Add support for YAML schemas documentation for Versal CPM5 Root Port driver.

Signed-off-by: Bharat Kumar Gogada <[email protected]>
---
.../bindings/pci/xilinx-versal-cpm.yaml | 38 ++++++++++++++++++-
1 file changed, 37 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
index cca395317a4c..24ddc2855b94 100644
--- a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
+++ b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
@@ -14,17 +14,23 @@ allOf:

properties:
compatible:
- const: xlnx,versal-cpm-host-1.00
+ enum:
+ - xlnx,versal-cpm-host-1.00
+ - xlnx,versal-cpm5-host

reg:
items:
- description: CPM system level control and status registers.
- description: Configuration space region and bridge registers.
+ - description: CPM5 control and status registers.
+ minItems: 2

reg-names:
items:
- const: cpm_slcr
- const: cfg
+ - const: cpm_csr
+ minItems: 2

interrupts:
maxItems: 1
@@ -95,4 +101,34 @@ examples:
interrupt-controller;
};
};
+
+ cpm5_pcie: pcie@fcdd0000 {
+ compatible = "xlnx,versal-cpm5-host";
+ device_type = "pci";
+ #address-cells = <3>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ interrupts = <0 72 4>;
+ interrupt-parent = <&gic>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc_1 0>,
+ <0 0 0 2 &pcie_intc_1 1>,
+ <0 0 0 3 &pcie_intc_1 2>,
+ <0 0 0 4 &pcie_intc_1 3>;
+ bus-range = <0x00 0xff>;
+ ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>,
+ <0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 0x80000000>;
+ msi-map = <0x0 &its_gic 0x0 0x10000>;
+ reg = <0x00 0xfcdd0000 0x00 0x1000>,
+ <0x06 0x00000000 0x00 0x1000000>,
+ <0x00 0xfce20000 0x00 0x1000000>;
+ reg-names = "cpm_slcr", "cfg", "cpm_csr";
+
+ pcie_intc_1: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
};
--
2.25.1

2022-06-21 22:47:09

by Bjorn Helgaas

[permalink] [raw]
Subject: Re: [PATCH v5 0/2] Add support for Xilinx Versal CPM5 Root Port

On Tue, Jun 21, 2022 at 05:06:51PM +0530, Bharat Kumar Gogada wrote:
> Xilinx Versal Premium series has CPM5 block which supports Root Port
> functioning at Gen5 speed.
>
> Xilinx Versal CPM5 has few changes with existing CPM block.
> - CPM5 has dedicated register space for control and status registers.
> - CPM5 legacy interrupt handling needs additonal register bit
> to enable and handle legacy interrupts.
>
> Changes in v5:
> - Added of_device_get_match_data to identify CPM version.
>
>
> Bharat Kumar Gogada (2):
> dt-bindings: PCI: xilinx-cpm: Add Versal CPM5 Root Port
> PCI: xilinx-cpm: Add support for Versal CPM5 Root Port
>
> .../bindings/pci/xilinx-versal-cpm.yaml | 48 ++++++++++++--
> drivers/pci/controller/pcie-xilinx-cpm.c | 62 ++++++++++++++++++-
> 2 files changed, 103 insertions(+), 7 deletions(-)

This is the third "v5" posting:

#1 Jun 16 https://lore.kernel.org/r/[email protected]
#2 Jun 18 https://lore.kernel.org/r/[email protected]
#3 Jun 21 https://lore.kernel.org/r/[email protected]

This makes things harder than necessary.

I commented on a couple things in #2, and you said you were going to
fix them, but they aren't fixed in #3.

It will also make things easier if you include the MAINTAINERS patch
in the same series. There's no reason for it to be separate.

Can you please post a v6 with the updates?

Bjorn

2022-06-28 20:13:25

by Rob Herring (Arm)

[permalink] [raw]
Subject: Re: [PATCH v5 1/2] dt-bindings: PCI: xilinx-cpm: Add Versal CPM5 Root Port

On Tue, 21 Jun 2022 17:06:52 +0530, Bharat Kumar Gogada wrote:
> Xilinx Versal Premium series has CPM5 block which supports Root Port
> functionality at Gen5 speed.
>
> Add support for YAML schemas documentation for Versal CPM5 Root Port driver.
>
> Signed-off-by: Bharat Kumar Gogada <[email protected]>
> ---
> .../bindings/pci/xilinx-versal-cpm.yaml | 38 ++++++++++++++++++-
> 1 file changed, 37 insertions(+), 1 deletion(-)
>

Reviewed-by: Rob Herring <[email protected]>