This patchset adds initial support for the Nuvoton
Arbel NPCM8XX Board Management controller (BMC) SoC family.
The Nuvoton Arbel NPCM8XX SoC is a fourth-generation BMC.
The NPCM8XX computing subsystem comprises a quadcore ARM
Cortex A35 ARM-V8 architecture.
This patchset adds minimal architecture and drivers such as:
Clocksource, Clock, Reset, and WD.
Some of the Arbel NPCM8XX peripherals are based on Poleg NPCM7XX.
This patchset was tested on the Arbel NPCM8XX evaluation board.
Addressed comments from:
- Krzysztof Kozlowski: https://www.spinics.net/lists/arm-kernel/msg990506.html
Changes since version 4:
- NPCM8XX clock driver
- Use the same quote in the dt-binding file.
Changes since version 3:
- NPCM8XX clock driver
- Rename NPCM8xx clock dt-binding header file.
- Remove unused structures.
- Improve Handling the clocks registration.
- NPCM reset driver
- Add ref phandle to dt-binding.
Changes since version 2:
- Remove NPCM8xx WDT compatible patch.
- Remove NPCM8xx UART compatible patch.
- NPCM8XX clock driver
- Add debug new line.
- Add 25M fixed rate clock.
- Remove unused clocks and clock name from dt-binding.
- NPCM reset driver
- Revert to npcm7xx dt-binding.
- Skip dt binding quotes.
- Adding DTS backward compatibility.
- Remove NPCM8xx binding include file.
- Warp commit message.
- NPCM8XX device tree:
- Remove unused clock nodes (used in the clock driver)
- Modify gcr and rst node names.
Changes since version 1:
- NPCM8XX clock driver
- Modify dt-binding.
- Remove unsed definition and include.
- Include alphabetically.
- Use clock devm.
- NPCM reset driver
- Modify dt-binding.
- Modify syscon name.
- Add syscon support to NPCM7XX dts reset node.
- use data structure.
- NPCM8XX device tree:
- Modify evb compatible name.
- Add NPCM7xx compatible.
- Remove disable nodes from the EVB DTS.
Tomer Maimon (18):
dt-bindings: timer: npcm: Add npcm845 compatible string
clocksource: timer-npcm7xx: Add NPCM845 timer support
dt-bindings: serial: 8250: Add npcm845 compatible string
dt-bindings: watchdog: npcm: Add npcm845 compatible string
dt-binding: clk: npcm845: Add binding for Nuvoton NPCM8XX Clock
clk: npcm8xx: add clock controller
dt-bindings: reset: npcm: add GCR syscon property
ARM: dts: nuvoton: add reset syscon property
reset: npcm: using syscon instead of device data
dt-bindings: reset: npcm: Add support for NPCM8XX
reset: npcm: Add NPCM8XX support
dt-bindings: arm: npcm: Add maintainer
dt-bindings: arm: npcm: Add nuvoton,npcm845 compatible string
dt-bindings: arm: npcm: Add nuvoton,npcm845 GCR compatible string
arm64: npcm: Add support for Nuvoton NPCM8XX BMC SoC
arm64: dts: nuvoton: Add initial NPCM8XX device tree
arm64: dts: nuvoton: Add initial NPCM845 EVB device tree
arm64: defconfig: Add Nuvoton NPCM family support
.../devicetree/bindings/arm/npcm/npcm.yaml | 7 +
.../bindings/arm/npcm/nuvoton,gcr.yaml | 2 +
.../bindings/clock/nuvoton,npcm845-clk.yaml | 49 ++
.../bindings/reset/nuvoton,npcm750-reset.yaml | 10 +-
.../devicetree/bindings/serial/8250.yaml | 1 +
.../bindings/timer/nuvoton,npcm7xx-timer.yaml | 2 +
.../bindings/watchdog/nuvoton,npcm-wdt.txt | 3 +-
MAINTAINERS | 2 +
arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi | 1 +
arch/arm64/Kconfig.platforms | 11 +
arch/arm64/boot/dts/Makefile | 1 +
arch/arm64/boot/dts/nuvoton/Makefile | 2 +
.../dts/nuvoton/nuvoton-common-npcm8xx.dtsi | 170 +++++
.../boot/dts/nuvoton/nuvoton-npcm845-evb.dts | 30 +
.../boot/dts/nuvoton/nuvoton-npcm845.dtsi | 76 +++
arch/arm64/configs/defconfig | 3 +
drivers/clk/Kconfig | 6 +
drivers/clk/Makefile | 1 +
drivers/clk/clk-npcm8xx.c | 594 ++++++++++++++++++
drivers/clocksource/timer-npcm7xx.c | 1 +
drivers/reset/reset-npcm.c | 206 +++++-
.../dt-bindings/clock/nuvoton,npcm845-clk.h | 49 ++
22 files changed, 1191 insertions(+), 36 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/nuvoton,npcm845-clk.yaml
create mode 100644 arch/arm64/boot/dts/nuvoton/Makefile
create mode 100644 arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
create mode 100644 arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts
create mode 100644 arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi
create mode 100644 drivers/clk/clk-npcm8xx.c
create mode 100644 include/dt-bindings/clock/nuvoton,npcm845-clk.h
--
2.33.0
Add a compatible string for Nuvoton BMC NPCM845 SoC and a board specific
device tree for the NPCM845 (Arbel) evaluation board.
Signed-off-by: Tomer Maimon <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
---
Documentation/devicetree/bindings/arm/npcm/npcm.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/npcm/npcm.yaml b/Documentation/devicetree/bindings/arm/npcm/npcm.yaml
index ea9c3103761d..43409e5721d5 100644
--- a/Documentation/devicetree/bindings/arm/npcm/npcm.yaml
+++ b/Documentation/devicetree/bindings/arm/npcm/npcm.yaml
@@ -27,4 +27,10 @@ properties:
- nuvoton,npcm750-evb # NPCM750 evaluation board
- const: nuvoton,npcm750
+ - description: NPCM845 based boards
+ items:
+ - enum:
+ - nuvoton,npcm845-evb # NPCM845 evaluation board
+ - const: nuvoton,npcm845
+
additionalProperties: true
--
2.33.0
Add initial Nuvoton NPCM845 evaluation board device tree.
Signed-off-by: Tomer Maimon <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
---
arch/arm64/boot/dts/nuvoton/Makefile | 2 ++
.../boot/dts/nuvoton/nuvoton-npcm845-evb.dts | 30 +++++++++++++++++++
2 files changed, 32 insertions(+)
create mode 100644 arch/arm64/boot/dts/nuvoton/Makefile
create mode 100644 arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts
diff --git a/arch/arm64/boot/dts/nuvoton/Makefile b/arch/arm64/boot/dts/nuvoton/Makefile
new file mode 100644
index 000000000000..a99dab90472a
--- /dev/null
+++ b/arch/arm64/boot/dts/nuvoton/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_NPCM) += nuvoton-npcm845-evb.dtb
diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts
new file mode 100644
index 000000000000..a5ab2bc0f835
--- /dev/null
+++ b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2021 Nuvoton Technology [email protected]
+
+/dts-v1/;
+#include "nuvoton-npcm845.dtsi"
+
+/ {
+ model = "Nuvoton npcm845 Development Board (Device Tree)";
+ compatible = "nuvoton,npcm845-evb", "nuvoton,npcm845";
+
+ aliases {
+ serial0 = &serial0;
+ };
+
+ chosen {
+ stdout-path = &serial0;
+ };
+
+ memory {
+ reg = <0x0 0x0 0x0 0x40000000>;
+ };
+};
+
+&serial0 {
+ status = "okay";
+};
+
+&watchdog1 {
+ status = "okay";
+};
--
2.33.0
This adds initial device tree support for the Nuvoton NPCM845 Board
Management controller (BMC) SoC family.
The NPCM845 based quad-core Cortex-A35 ARMv8 architecture and have
various peripheral IPs.
Signed-off-by: Tomer Maimon <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
---
arch/arm64/boot/dts/Makefile | 1 +
.../dts/nuvoton/nuvoton-common-npcm8xx.dtsi | 170 ++++++++++++++++++
.../boot/dts/nuvoton/nuvoton-npcm845.dtsi | 76 ++++++++
3 files changed, 247 insertions(+)
create mode 100644 arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
create mode 100644 arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index 1ba04e31a438..7b107fa7414b 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -19,6 +19,7 @@ subdir-y += lg
subdir-y += marvell
subdir-y += mediatek
subdir-y += microchip
+subdir-y += nuvoton
subdir-y += nvidia
subdir-y += qcom
subdir-y += realtek
diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
new file mode 100644
index 000000000000..aa7aac8c3774
--- /dev/null
+++ b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
@@ -0,0 +1,170 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2021 Nuvoton Technology [email protected]
+
+#include <dt-bindings/clock/nuvoton,npcm845-clk.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&gic>;
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ ranges;
+
+ gcr: system-controller@f0800000 {
+ compatible = "nuvoton,npcm845-gcr", "syscon";
+ reg = <0x0 0xf0800000 0x0 0x1000>;
+ };
+
+ gic: interrupt-controller@dfff9000 {
+ compatible = "arm,gic-400";
+ reg = <0x0 0xdfff9000 0x0 0x1000>,
+ <0x0 0xdfffa000 0x0 0x2000>,
+ <0x0 0xdfffc000 0x0 0x2000>,
+ <0x0 0xdfffe000 0x0 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ #address-cells = <0>;
+ ppi-partitions {
+ ppi_cluster0: interrupt-partition-0 {
+ affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
+ };
+ };
+ };
+ };
+
+ ahb {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ ranges;
+
+ rstc: reset-controller@f0801000 {
+ compatible = "nuvoton,npcm845-reset";
+ reg = <0x0 0xf0801000 0x0 0x78>;
+ #reset-cells = <2>;
+ nuvoton,sysgcr = <&gcr>;
+ };
+
+ clk: clock-controller@f0801000 {
+ compatible = "nuvoton,npcm845-clk";
+ #clock-cells = <1>;
+ reg = <0x0 0xf0801000 0x0 0x1000>;
+ };
+
+ apb {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ ranges = <0x0 0x0 0xf0000000 0x00300000>,
+ <0xfff00000 0x0 0xfff00000 0x00016000>;
+
+ timer0: timer@8000 {
+ compatible = "nuvoton,npcm845-timer";
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x8000 0x1C>;
+ clocks = <&clk NPCM8XX_CLK_REFCLK>;
+ clock-names = "refclk";
+ };
+
+ serial0: serial@0 {
+ compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
+ reg = <0x0 0x1000>;
+ clocks = <&clk NPCM8XX_CLK_UART>;
+ interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ serial1: serial@1000 {
+ compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
+ reg = <0x1000 0x1000>;
+ clocks = <&clk NPCM8XX_CLK_UART>;
+ interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ serial2: serial@2000 {
+ compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
+ reg = <0x2000 0x1000>;
+ clocks = <&clk NPCM8XX_CLK_UART>;
+ interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ serial3: serial@3000 {
+ compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
+ reg = <0x3000 0x1000>;
+ clocks = <&clk NPCM8XX_CLK_UART>;
+ interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ serial4: serial@4000 {
+ compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
+ reg = <0x4000 0x1000>;
+ clocks = <&clk NPCM8XX_CLK_UART>;
+ interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ serial5: serial@5000 {
+ compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
+ reg = <0x5000 0x1000>;
+ clocks = <&clk NPCM8XX_CLK_UART>;
+ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ serial6: serial@6000 {
+ compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
+ reg = <0x6000 0x1000>;
+ clocks = <&clk NPCM8XX_CLK_UART>;
+ interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ watchdog0: watchdog@801c {
+ compatible = "nuvoton,npcm845-wdt", "nuvoton,npcm750-wdt";
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x801c 0x4>;
+ status = "disabled";
+ clocks = <&clk NPCM8XX_CLK_REFCLK>;
+ syscon = <&gcr>;
+ };
+
+ watchdog1: watchdog@901c {
+ compatible = "nuvoton,npcm845-wdt", "nuvoton,npcm750-wdt";
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x901c 0x4>;
+ status = "disabled";
+ clocks = <&clk NPCM8XX_CLK_REFCLK>;
+ syscon = <&gcr>;
+ };
+
+ watchdog2: watchdog@a01c {
+ compatible = "nuvoton,npcm845-wdt", "nuvoton,npcm750-wdt";
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xa01c 0x4>;
+ status = "disabled";
+ clocks = <&clk NPCM8XX_CLK_REFCLK>;
+ syscon = <&gcr>;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi
new file mode 100644
index 000000000000..12118b75c0e6
--- /dev/null
+++ b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2021 Nuvoton Technology [email protected]
+
+#include "nuvoton-common-npcm8xx.dtsi"
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35";
+ clocks = <&clk NPCM8XX_CLK_CPU>;
+ reg = <0x0 0x0>;
+ next-level-cache = <&l2>;
+ enable-method = "psci";
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35";
+ clocks = <&clk NPCM8XX_CLK_CPU>;
+ reg = <0x0 0x1>;
+ next-level-cache = <&l2>;
+ enable-method = "psci";
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35";
+ clocks = <&clk NPCM8XX_CLK_CPU>;
+ reg = <0x0 0x2>;
+ next-level-cache = <&l2>;
+ enable-method = "psci";
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35";
+ clocks = <&clk NPCM8XX_CLK_CPU>;
+ reg = <0x0 0x3>;
+ next-level-cache = <&l2>;
+ enable-method = "psci";
+ };
+
+ l2: l2-cache {
+ compatible = "cache";
+ };
+ };
+
+ arm-pmu {
+ compatible = "arm,cortex-a35-pmu";
+ interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+};
--
2.33.0
Nuvoton Arbel BMC NPCM8XX contains an integrated clock controller which
generates and supplies clocks to all modules within the BMC.
Signed-off-by: Tomer Maimon <[email protected]>
---
drivers/clk/Kconfig | 6 +
drivers/clk/Makefile | 1 +
drivers/clk/clk-npcm8xx.c | 594 ++++++++++++++++++++++++++++++++++++++
3 files changed, 601 insertions(+)
create mode 100644 drivers/clk/clk-npcm8xx.c
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 48f8f4221e21..9aa915f6e233 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -428,6 +428,12 @@ config COMMON_CLK_K210
help
Support for the Canaan Kendryte K210 RISC-V SoC clocks.
+config COMMON_CLK_NPCM8XX
+ tristate "Clock driver for the NPCM8XX SoC Family"
+ depends on ARCH_NPCM || COMPILE_TEST
+ help
+ This driver supports the clocks on the Nuvoton BMC NPCM8XX SoC Family.
+
source "drivers/clk/actions/Kconfig"
source "drivers/clk/analogbits/Kconfig"
source "drivers/clk/baikal-t1/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index d5db170d38d2..b0ec1184a744 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -49,6 +49,7 @@ obj-$(CONFIG_ARCH_MILBEAUT_M10V) += clk-milbeaut.o
obj-$(CONFIG_ARCH_MOXART) += clk-moxart.o
obj-$(CONFIG_ARCH_NOMADIK) += clk-nomadik.o
obj-$(CONFIG_ARCH_NPCM7XX) += clk-npcm7xx.o
+obj-$(CONFIG_COMMON_CLK_NPCM8XX) += clk-npcm8xx.o
obj-$(CONFIG_ARCH_NSPIRE) += clk-nspire.o
obj-$(CONFIG_COMMON_CLK_OXNAS) += clk-oxnas.o
obj-$(CONFIG_COMMON_CLK_PALMAS) += clk-palmas.o
diff --git a/drivers/clk/clk-npcm8xx.c b/drivers/clk/clk-npcm8xx.c
new file mode 100644
index 000000000000..7512d14db839
--- /dev/null
+++ b/drivers/clk/clk-npcm8xx.c
@@ -0,0 +1,594 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Nuvoton NPCM8xx Clock Generator
+ * All the clocks are initialized by the bootloader, so this driver allow only
+ * reading of current settings directly from the hardware.
+ *
+ * Copyright (C) 2020 Nuvoton Technologies
+ * Author: Tomer Maimon <[email protected]>
+ */
+
+#include <linux/bitfield.h>
+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include <dt-bindings/clock/nuvoton,npcm845-clk.h>
+
+#define NPCM8XX_REF_CLK 25000000
+
+struct npcm8xx_clk_pll {
+ struct clk_hw hw;
+ void __iomem *pllcon;
+ u8 flags;
+};
+
+#define to_npcm8xx_clk_pll(_hw) container_of(_hw, struct npcm8xx_clk_pll, hw)
+
+#define PLLCON_LOKI BIT(31)
+#define PLLCON_LOKS BIT(30)
+#define PLLCON_FBDV GENMASK(27, 16)
+#define PLLCON_OTDV2 GENMASK(15, 13)
+#define PLLCON_PWDEN BIT(12)
+#define PLLCON_OTDV1 GENMASK(10, 8)
+#define PLLCON_INDV GENMASK(5, 0)
+
+static unsigned long npcm8xx_clk_pll_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct npcm8xx_clk_pll *pll = to_npcm8xx_clk_pll(hw);
+ unsigned long fbdv, indv, otdv1, otdv2;
+ unsigned int val;
+ u64 ret;
+
+ if (parent_rate == 0) {
+ pr_debug("%s: parent rate is zero\n", __func__);
+ return 0;
+ }
+
+ val = readl_relaxed(pll->pllcon);
+
+ indv = FIELD_GET(PLLCON_INDV, val);
+ fbdv = FIELD_GET(PLLCON_FBDV, val);
+ otdv1 = FIELD_GET(PLLCON_OTDV1, val);
+ otdv2 = FIELD_GET(PLLCON_OTDV2, val);
+
+ ret = (u64)parent_rate * fbdv;
+ do_div(ret, indv * otdv1 * otdv2);
+
+ return ret;
+}
+
+static const struct clk_ops npcm8xx_clk_pll_ops = {
+ .recalc_rate = npcm8xx_clk_pll_recalc_rate,
+};
+
+static struct clk_hw *
+npcm8xx_clk_register_pll(struct device *dev, void __iomem *pllcon,
+ const char *name, const char *parent_name,
+ unsigned long flags)
+{
+ struct npcm8xx_clk_pll *pll;
+ struct clk_init_data init;
+ struct clk_hw *hw;
+ int ret;
+
+ pll = devm_kzalloc(dev, sizeof(*pll), GFP_KERNEL);
+ if (!pll)
+ return ERR_PTR(-ENOMEM);
+
+ pr_debug("%s reg, name=%s, p=%s\n", __func__, name, parent_name);
+
+ init.name = name;
+ init.ops = &npcm8xx_clk_pll_ops;
+ init.parent_names = &parent_name;
+ init.num_parents = 1;
+ init.flags = flags;
+
+ pll->pllcon = pllcon;
+ pll->hw.init = &init;
+
+ hw = &pll->hw;
+
+ ret = devm_clk_hw_register(dev, hw);
+ if (ret)
+ return ERR_PTR(ret);
+
+ return hw;
+}
+
+#define NPCM8XX_CLKEN1 (0x00)
+#define NPCM8XX_CLKEN2 (0x28)
+#define NPCM8XX_CLKEN3 (0x30)
+#define NPCM8XX_CLKEN4 (0x70)
+#define NPCM8XX_CLKSEL (0x04)
+#define NPCM8XX_CLKDIV1 (0x08)
+#define NPCM8XX_CLKDIV2 (0x2C)
+#define NPCM8XX_CLKDIV3 (0x58)
+#define NPCM8XX_CLKDIV4 (0x7C)
+#define NPCM8XX_PLLCON0 (0x0C)
+#define NPCM8XX_PLLCON1 (0x10)
+#define NPCM8XX_PLLCON2 (0x54)
+#define NPCM8XX_SWRSTR (0x14)
+#define NPCM8XX_IRQWAKECON (0x18)
+#define NPCM8XX_IRQWAKEFLAG (0x1C)
+#define NPCM8XX_IPSRST1 (0x20)
+#define NPCM8XX_IPSRST2 (0x24)
+#define NPCM8XX_IPSRST3 (0x34)
+#define NPCM8XX_WD0RCR (0x38)
+#define NPCM8XX_WD1RCR (0x3C)
+#define NPCM8XX_WD2RCR (0x40)
+#define NPCM8XX_SWRSTC1 (0x44)
+#define NPCM8XX_SWRSTC2 (0x48)
+#define NPCM8XX_SWRSTC3 (0x4C)
+#define NPCM8XX_SWRSTC4 (0x50)
+#define NPCM8XX_CORSTC (0x5C)
+#define NPCM8XX_PLLCONG (0x60)
+#define NPCM8XX_AHBCKFI (0x64)
+#define NPCM8XX_SECCNT (0x68)
+#define NPCM8XX_CNTR25M (0x6C)
+#define NPCM8XX_THRTL_CNT (0xC0)
+
+struct npcm8xx_clk_mux_data {
+ u8 shift;
+ u8 mask;
+ u32 *table;
+ const char *name;
+ const char * const *parent_names;
+ u8 num_parents;
+ unsigned long flags;
+ /*
+ * If this clock is exported via DT, set onecell_idx to constant
+ * defined in include/dt-bindings/clock/nuvoton, NPCM8XX-clock.h for
+ * this specific clock. Otherwise, set to -1.
+ */
+ int onecell_idx;
+};
+
+struct npcm8xx_clk_div_data {
+ u32 reg;
+ u8 shift;
+ u8 width;
+ const char *name;
+ const char *parent_name;
+ u8 clk_divider_flags;
+ unsigned long flags;
+ /*
+ * If this clock is exported via DT, set onecell_idx to constant
+ * defined in include/dt-bindings/clock/nuvoton, NPCM8XX-clock.h for
+ * this specific clock. Otherwise, set to -1.
+ */
+ int onecell_idx;
+};
+
+struct npcm8xx_clk_pll_data {
+ u32 reg;
+ const char *name;
+ const char *parent_name;
+ unsigned long flags;
+ /*
+ * If this clock is exported via DT, set onecell_idx to constant
+ * defined in include/dt-bindings/clock/nuvoton, NPCM8XX-clock.h for
+ * this specific clock. Otherwise, set to -1.
+ */
+ int onecell_idx;
+};
+
+/*
+ * Single copy of strings used to refer to clocks within this driver indexed by
+ * above enum.
+ */
+#define NPCM8XX_CLK_S_REFCLK "refclk"
+#define NPCM8XX_CLK_S_SYSBYPCK "sysbypck"
+#define NPCM8XX_CLK_S_MCBYPCK "mcbypck"
+#define NPCM8XX_CLK_S_PLL0 "pll0"
+#define NPCM8XX_CLK_S_PLL1 "pll1"
+#define NPCM8XX_CLK_S_PLL1_DIV2 "pll1_div2"
+#define NPCM8XX_CLK_S_PLL2 "pll2"
+#define NPCM8XX_CLK_S_PLL_GFX "pll_gfx"
+#define NPCM8XX_CLK_S_PLL2_DIV2 "pll2_div2"
+#define NPCM8XX_CLK_S_PIX_MUX "gfx_pixel"
+#define NPCM8XX_CLK_S_MC_MUX "mc_phy"
+#define NPCM8XX_CLK_S_CPU_MUX "cpu" /* AKA system clock */
+#define NPCM8XX_CLK_S_MC "mc"
+#define NPCM8XX_CLK_S_AXI "axi" /* AKA CLK2 */
+#define NPCM8XX_CLK_S_AHB "ahb" /* AKA CLK4 */
+#define NPCM8XX_CLK_S_CLKOUT_MUX "clkout_mux"
+#define NPCM8XX_CLK_S_UART_MUX "uart_mux"
+#define NPCM8XX_CLK_S_SD_MUX "sd_mux"
+#define NPCM8XX_CLK_S_GFXM_MUX "gfxm_mux"
+#define NPCM8XX_CLK_S_SU_MUX "serial_usb_mux"
+#define NPCM8XX_CLK_S_DVC_MUX "dvc_mux"
+#define NPCM8XX_CLK_S_GFX_MUX "gfx_mux"
+#define NPCM8XX_CLK_S_ADC_MUX "adc_mux"
+#define NPCM8XX_CLK_S_SPI0 "spi0"
+#define NPCM8XX_CLK_S_SPI1 "spi1"
+#define NPCM8XX_CLK_S_SPI3 "spi3"
+#define NPCM8XX_CLK_S_SPIX "spix"
+#define NPCM8XX_CLK_S_APB1 "apb1"
+#define NPCM8XX_CLK_S_APB2 "apb2"
+#define NPCM8XX_CLK_S_APB3 "apb3"
+#define NPCM8XX_CLK_S_APB4 "apb4"
+#define NPCM8XX_CLK_S_APB5 "apb5"
+#define NPCM8XX_CLK_S_APB19 "apb19"
+#define NPCM8XX_CLK_S_TOCK "tock"
+#define NPCM8XX_CLK_S_CLKOUT "clkout"
+#define NPCM8XX_CLK_S_PRE_ADC "pre adc"
+#define NPCM8XX_CLK_S_UART "uart"
+#define NPCM8XX_CLK_S_UART2 "uart2"
+#define NPCM8XX_CLK_S_TIMER "timer"
+#define NPCM8XX_CLK_S_MMC "mmc"
+#define NPCM8XX_CLK_S_SDHC "sdhc"
+#define NPCM8XX_CLK_S_ADC "adc"
+#define NPCM8XX_CLK_S_GFX "gfx0_gfx1_mem"
+#define NPCM8XX_CLK_S_USBIF "serial_usbif"
+#define NPCM8XX_CLK_S_USB_HOST "usb_host"
+#define NPCM8XX_CLK_S_USB_BRIDGE "usb_bridge"
+#define NPCM8XX_CLK_S_PCI "pci"
+#define NPCM8XX_CLK_S_TH "th"
+#define NPCM8XX_CLK_S_ATB "atb"
+#define NPCM8XX_CLK_S_PRE_CLK "pre_clk"
+
+#define NPCM8XX_CLK_S_RG_MUX "rg_mux"
+#define NPCM8XX_CLK_S_RCP_MUX "rcp_mux"
+#define NPCM8XX_CLK_S_RG "rg"
+#define NPCM8XX_CLK_S_RCP "rcp"
+
+static u32 pll_mux_table[] = {0, 1, 2, 3};
+static const char * const pll_mux_parents[] = {
+ NPCM8XX_CLK_S_PLL0,
+ NPCM8XX_CLK_S_PLL1,
+ NPCM8XX_CLK_S_REFCLK,
+ NPCM8XX_CLK_S_PLL2_DIV2,
+};
+
+static u32 cpuck_mux_table[] = {0, 1, 2, 3, 7};
+static const char * const cpuck_mux_parents[] = {
+ NPCM8XX_CLK_S_PLL0,
+ NPCM8XX_CLK_S_PLL1,
+ NPCM8XX_CLK_S_REFCLK,
+ NPCM8XX_CLK_S_SYSBYPCK,
+ NPCM8XX_CLK_S_PLL2,
+};
+
+static u32 pixcksel_mux_table[] = {0, 2};
+static const char * const pixcksel_mux_parents[] = {
+ NPCM8XX_CLK_S_PLL_GFX,
+ NPCM8XX_CLK_S_REFCLK,
+};
+
+static u32 sucksel_mux_table[] = {2, 3};
+static const char * const sucksel_mux_parents[] = {
+ NPCM8XX_CLK_S_REFCLK,
+ NPCM8XX_CLK_S_PLL2_DIV2,
+};
+
+static u32 mccksel_mux_table[] = {0, 2, 3};
+static const char * const mccksel_mux_parents[] = {
+ NPCM8XX_CLK_S_PLL1_DIV2,
+ NPCM8XX_CLK_S_REFCLK,
+ NPCM8XX_CLK_S_MCBYPCK,
+};
+
+static u32 clkoutsel_mux_table[] = {0, 1, 2, 3, 4};
+static const char * const clkoutsel_mux_parents[] = {
+ NPCM8XX_CLK_S_PLL0,
+ NPCM8XX_CLK_S_PLL1,
+ NPCM8XX_CLK_S_REFCLK,
+ NPCM8XX_CLK_S_PLL_GFX, // divided by 2
+ NPCM8XX_CLK_S_PLL2_DIV2,
+};
+
+static u32 gfxmsel_mux_table[] = {2, 3};
+static const char * const gfxmsel_mux_parents[] = {
+ NPCM8XX_CLK_S_REFCLK,
+ NPCM8XX_CLK_S_PLL2_DIV2,
+};
+
+static u32 dvcssel_mux_table[] = {2, 3};
+static const char * const dvcssel_mux_parents[] = {
+ NPCM8XX_CLK_S_REFCLK,
+ NPCM8XX_CLK_S_PLL2,
+};
+
+static const struct npcm8xx_clk_pll_data npcm8xx_plls[] = {
+ {NPCM8XX_PLLCON0, NPCM8XX_CLK_S_PLL0, NPCM8XX_CLK_S_REFCLK, 0, -1},
+ {NPCM8XX_PLLCON1, NPCM8XX_CLK_S_PLL1, NPCM8XX_CLK_S_REFCLK, 0, -1},
+ {NPCM8XX_PLLCON2, NPCM8XX_CLK_S_PLL2, NPCM8XX_CLK_S_REFCLK, 0, -1},
+ {NPCM8XX_PLLCONG, NPCM8XX_CLK_S_PLL_GFX, NPCM8XX_CLK_S_REFCLK, 0, -1},
+};
+
+static const struct npcm8xx_clk_mux_data npcm8xx_muxes[] = {
+ {0, GENMASK(1, 0), cpuck_mux_table, NPCM8XX_CLK_S_CPU_MUX,
+ cpuck_mux_parents, ARRAY_SIZE(cpuck_mux_parents), CLK_IS_CRITICAL,
+ NPCM8XX_CLK_CPU},
+
+ {4, GENMASK(1, 0), pixcksel_mux_table, NPCM8XX_CLK_S_PIX_MUX,
+ pixcksel_mux_parents, ARRAY_SIZE(pixcksel_mux_parents), 0,
+ NPCM8XX_CLK_GFX_PIXEL},
+
+ {6, GENMASK(1, 0), pll_mux_table, NPCM8XX_CLK_S_SD_MUX,
+ pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
+
+ {8, GENMASK(1, 0), pll_mux_table, NPCM8XX_CLK_S_UART_MUX,
+ pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
+
+ {10, GENMASK(1, 0), sucksel_mux_table, NPCM8XX_CLK_S_SU_MUX,
+ sucksel_mux_parents, ARRAY_SIZE(sucksel_mux_parents), 0, -1},
+
+ {12, GENMASK(1, 0), mccksel_mux_table, NPCM8XX_CLK_S_MC_MUX,
+ mccksel_mux_parents, ARRAY_SIZE(mccksel_mux_parents), 0, -1},
+
+ {14, GENMASK(1, 0), pll_mux_table, NPCM8XX_CLK_S_ADC_MUX,
+ pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
+
+ {16, GENMASK(1, 0), pll_mux_table, NPCM8XX_CLK_S_GFX_MUX,
+ pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
+
+ {18, GENMASK(2, 0), clkoutsel_mux_table, NPCM8XX_CLK_S_CLKOUT_MUX,
+ clkoutsel_mux_parents, ARRAY_SIZE(clkoutsel_mux_parents), 0, -1},
+
+ {21, GENMASK(1, 0), gfxmsel_mux_table, NPCM8XX_CLK_S_GFXM_MUX,
+ gfxmsel_mux_parents, ARRAY_SIZE(gfxmsel_mux_parents), 0, -1},
+
+ {23, GENMASK(1, 0), dvcssel_mux_table, NPCM8XX_CLK_S_DVC_MUX,
+ dvcssel_mux_parents, ARRAY_SIZE(dvcssel_mux_parents), 0, -1},
+
+ {25, GENMASK(1, 0), pll_mux_table, NPCM8XX_CLK_S_RG_MUX,
+ pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
+
+ {27, GENMASK(1, 0), pll_mux_table, NPCM8XX_CLK_S_RCP_MUX,
+ pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
+};
+
+/* configurable dividers: */
+static const struct npcm8xx_clk_div_data npcm8xx_divs[] = {
+ {NPCM8XX_CLKDIV1, 28, 3, NPCM8XX_CLK_S_ADC, NPCM8XX_CLK_S_PRE_ADC,
+ CLK_DIVIDER_READ_ONLY | CLK_DIVIDER_POWER_OF_TWO, 0,
+ NPCM8XX_CLK_ADC},
+ /* bit 30-28 ADCCKDIV*/
+ {NPCM8XX_CLKDIV1, 26, 2, NPCM8XX_CLK_S_AHB, NPCM8XX_CLK_S_PRE_CLK,
+ CLK_DIVIDER_READ_ONLY, CLK_IS_CRITICAL, NPCM8XX_CLK_AHB},
+ /* bit 28-26 CLK4DIV*/
+ {NPCM8XX_CLKDIV1, 21, 5, NPCM8XX_CLK_S_PRE_ADC,
+ NPCM8XX_CLK_S_ADC_MUX, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_PRE_ADC},
+ /* bit 25-21 PRE-ADCCKDIV*/
+ {NPCM8XX_CLKDIV1, 16, 5, NPCM8XX_CLK_S_UART,
+ NPCM8XX_CLK_S_UART_MUX, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_UART},
+ /* bit 20-16 UARTDIV*/
+ {NPCM8XX_CLKDIV1, 11, 5, NPCM8XX_CLK_S_MMC,
+ NPCM8XX_CLK_S_SD_MUX, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_MMC},
+ /* bit 15-11 MMCCKDIV*/
+ {NPCM8XX_CLKDIV1, 6, 5, NPCM8XX_CLK_S_SPI3,
+ NPCM8XX_CLK_S_AHB, 0, 0, NPCM8XX_CLK_SPI3},
+ /* bit 10-6 AHB3CKDIV*/
+ {NPCM8XX_CLKDIV1, 2, 4, NPCM8XX_CLK_S_PCI,
+ NPCM8XX_CLK_S_GFX_MUX, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_PCI},
+ /* bit 5-2 PCICKDIV*/
+
+ {NPCM8XX_CLKDIV2, 30, 2, NPCM8XX_CLK_S_APB4, NPCM8XX_CLK_S_AHB,
+ CLK_DIVIDER_READ_ONLY | CLK_DIVIDER_POWER_OF_TWO, 0,
+ NPCM8XX_CLK_APB4},
+ /* bit 31-30 APB4CKDIV*/
+ {NPCM8XX_CLKDIV2, 28, 2, NPCM8XX_CLK_S_APB3, NPCM8XX_CLK_S_AHB,
+ CLK_DIVIDER_READ_ONLY | CLK_DIVIDER_POWER_OF_TWO, 0,
+ NPCM8XX_CLK_APB3},
+ /* bit 29-28 APB3CKDIV*/
+ {NPCM8XX_CLKDIV2, 26, 2, NPCM8XX_CLK_S_APB2, NPCM8XX_CLK_S_AHB,
+ CLK_DIVIDER_READ_ONLY | CLK_DIVIDER_POWER_OF_TWO, 0,
+ NPCM8XX_CLK_APB2},
+ /* bit 28-26 APB2CKDIV*/
+ {NPCM8XX_CLKDIV2, 24, 2, NPCM8XX_CLK_S_APB1, NPCM8XX_CLK_S_AHB,
+ CLK_DIVIDER_READ_ONLY | CLK_DIVIDER_POWER_OF_TWO, 0,
+ NPCM8XX_CLK_APB1},
+ /* bit 25-24 APB1CKDIV*/
+ {NPCM8XX_CLKDIV2, 22, 2, NPCM8XX_CLK_S_APB5, NPCM8XX_CLK_S_AHB,
+ CLK_DIVIDER_READ_ONLY | CLK_DIVIDER_POWER_OF_TWO, 0,
+ NPCM8XX_CLK_APB5},
+ /* bit 23-22 APB5CKDIV*/
+ {NPCM8XX_CLKDIV2, 16, 5, NPCM8XX_CLK_S_CLKOUT, NPCM8XX_CLK_S_CLKOUT_MUX,
+ CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_CLKOUT},
+ /* bit 20-16 CLKOUTDIV*/
+ {NPCM8XX_CLKDIV2, 13, 3, NPCM8XX_CLK_S_GFX, NPCM8XX_CLK_S_GFX_MUX,
+ CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_GFX},
+ /* bit 15-13 GFXCKDIV*/
+ {NPCM8XX_CLKDIV2, 8, 5, NPCM8XX_CLK_S_USB_BRIDGE, NPCM8XX_CLK_S_SU_MUX,
+ CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_SU},
+ /* bit 12-8 SUCKDIV*/
+ {NPCM8XX_CLKDIV2, 4, 4, NPCM8XX_CLK_S_USB_HOST, NPCM8XX_CLK_S_SU_MUX,
+ CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_SU48},
+ /* bit 8-4 SU48CKDIV*/
+ {NPCM8XX_CLKDIV2, 0, 4, NPCM8XX_CLK_S_SDHC,
+ NPCM8XX_CLK_S_SD_MUX, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_SDHC}
+ ,/* bit 3-0 SD1CKDIV*/
+
+ {NPCM8XX_CLKDIV3, 16, 8, NPCM8XX_CLK_S_SPI1,
+ NPCM8XX_CLK_S_AHB, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_SPI1},
+ /* bit 23-16 SPI1CKDV*/
+ {NPCM8XX_CLKDIV3, 11, 5, NPCM8XX_CLK_S_UART2,
+ NPCM8XX_CLK_S_UART_MUX, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_UART2},
+ /* bit 15-11 UARTDIV2*/
+ {NPCM8XX_CLKDIV3, 6, 5, NPCM8XX_CLK_S_SPI0,
+ NPCM8XX_CLK_S_AHB, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_SPI0},
+ /* bit 10-6 SPI0CKDV*/
+ {NPCM8XX_CLKDIV3, 1, 5, NPCM8XX_CLK_S_SPIX,
+ NPCM8XX_CLK_S_AHB, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_SPIX},
+ /* bit 5-1 SPIXCKDV*/
+
+ {NPCM8XX_CLKDIV4, 28, 4, NPCM8XX_CLK_S_RG, NPCM8XX_CLK_S_RG_MUX,
+ CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_RG},
+ /* bit 31-28 RGREFDIV*/
+ {NPCM8XX_CLKDIV4, 12, 4, NPCM8XX_CLK_S_RCP, NPCM8XX_CLK_S_RCP_MUX,
+ CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_RCP},
+ /* bit 15-12 RCPREFDIV*/
+ {NPCM8XX_THRTL_CNT, 0, 2, NPCM8XX_CLK_S_TH, NPCM8XX_CLK_S_CPU_MUX,
+ CLK_DIVIDER_READ_ONLY | CLK_DIVIDER_POWER_OF_TWO, 0, NPCM8XX_CLK_TH},
+ /* bit 1-0 TH_DIV*/
+};
+
+static DEFINE_SPINLOCK(npcm8xx_clk_lock);
+
+static int npcm8xx_clk_probe(struct platform_device *pdev)
+{
+ struct clk_hw_onecell_data *npcm8xx_clk_data;
+ struct device *dev = &pdev->dev;
+ void __iomem *clk_base;
+ struct clk_hw *hw;
+ int i;
+
+ npcm8xx_clk_data = devm_kzalloc(dev, struct_size(npcm8xx_clk_data, hws,
+ NPCM8XX_NUM_CLOCKS),
+ GFP_KERNEL);
+ if (!npcm8xx_clk_data)
+ return -ENOMEM;
+
+ clk_base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(clk_base))
+ return PTR_ERR(clk_base);
+
+ npcm8xx_clk_data->num = NPCM8XX_NUM_CLOCKS;
+
+ for (i = 0; i < NPCM8XX_NUM_CLOCKS; i++)
+ npcm8xx_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
+
+ /* Reference 25MHz clock */
+ hw = clk_hw_register_fixed_rate(dev, "refclk", NULL, 0, NPCM8XX_REF_CLK);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+ npcm8xx_clk_data->hws[NPCM8XX_CLK_REFCLK] = hw;
+
+ /* Register plls */
+ for (i = 0; i < ARRAY_SIZE(npcm8xx_plls); i++) {
+ const struct npcm8xx_clk_pll_data *pll_data = &npcm8xx_plls[i];
+
+ hw = npcm8xx_clk_register_pll(dev, clk_base + pll_data->reg,
+ pll_data->name,
+ pll_data->parent_name,
+ pll_data->flags);
+ if (IS_ERR(hw)) {
+ dev_err(dev, "npcm8xx_clk: Can't register pll\n");
+ goto unregister_refclk;
+ }
+
+ if (pll_data->onecell_idx >= 0)
+ npcm8xx_clk_data->hws[pll_data->onecell_idx] = hw;
+ }
+
+ /* Register fixed dividers */
+ hw = devm_clk_hw_register_fixed_factor(dev, NPCM8XX_CLK_S_PLL1_DIV2,
+ NPCM8XX_CLK_S_PLL1, 0, 1, 2);
+ if (IS_ERR(hw)) {
+ dev_err(dev, "npcm8xx_clk: Can't register fixed div\n");
+ goto unregister_refclk;
+ }
+
+ hw = devm_clk_hw_register_fixed_factor(dev, NPCM8XX_CLK_S_PLL2_DIV2,
+ NPCM8XX_CLK_S_PLL2, 0, 1, 2);
+ if (IS_ERR(hw)) {
+ dev_err(dev, "npcm8xx_clk: Can't register pll div2\n");
+ goto unregister_refclk;
+ }
+
+ hw = devm_clk_hw_register_fixed_factor(dev, NPCM8XX_CLK_S_PRE_CLK,
+ NPCM8XX_CLK_S_CPU_MUX, 0, 1, 2);
+ if (IS_ERR(hw)) {
+ dev_err(dev, "npcm8xx_clk: Can't register ckclk div2\n");
+ goto unregister_refclk;
+ }
+
+ hw = devm_clk_hw_register_fixed_factor(dev, NPCM8XX_CLK_S_AXI,
+ NPCM8XX_CLK_S_TH, 0, 1, 2);
+ if (IS_ERR(hw)) {
+ dev_err(dev, "npcm8xx_clk: Can't register axi div2\n");
+ goto unregister_refclk;
+ }
+
+ hw = devm_clk_hw_register_fixed_factor(dev, NPCM8XX_CLK_S_ATB,
+ NPCM8XX_CLK_S_AXI, 0, 1, 2);
+ if (IS_ERR(hw)) {
+ dev_err(dev, "npcm8xx_clk: Can't register atb div2\n");
+ goto unregister_refclk;
+ }
+
+ /* Register clock dividers specified in npcm8xx_divs */
+ for (i = 0; i < ARRAY_SIZE(npcm8xx_divs); i++) {
+ const struct npcm8xx_clk_div_data *div_data = &npcm8xx_divs[i];
+
+ hw = devm_clk_hw_register_divider(dev, div_data->name,
+ div_data->parent_name,
+ div_data->flags,
+ clk_base + div_data->reg,
+ div_data->shift,
+ div_data->width,
+ div_data->clk_divider_flags,
+ &npcm8xx_clk_lock);
+ if (IS_ERR(hw)) {
+ dev_err(dev, "npcm8xx_clk: Can't register div table\n");
+ goto unregister_refclk;
+ }
+
+ if (div_data->onecell_idx >= 0)
+ npcm8xx_clk_data->hws[div_data->onecell_idx] = hw;
+ }
+
+ /* Register muxes */
+ for (i = 0; i < ARRAY_SIZE(npcm8xx_muxes); i++) {
+ const struct npcm8xx_clk_mux_data *mux_data = &npcm8xx_muxes[i];
+
+ hw = clk_hw_register_mux_table(dev, mux_data->name,
+ mux_data->parent_names,
+ mux_data->num_parents,
+ mux_data->flags,
+ clk_base + NPCM8XX_CLKSEL,
+ mux_data->shift,
+ mux_data->mask, 0,
+ mux_data->table,
+ &npcm8xx_clk_lock);
+
+ if (IS_ERR(hw)) {
+ dev_err(dev, "npcm8xx_clk: Can't register mux\n");
+ goto err_mux_clk;
+ }
+
+ if (mux_data->onecell_idx >= 0)
+ npcm8xx_clk_data->hws[mux_data->onecell_idx] = hw;
+ }
+
+ return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
+ npcm8xx_clk_data);
+
+err_mux_clk:
+ while (i--) {
+ if (npcm8xx_muxes[i].onecell_idx >= 0)
+ clk_hw_unregister_mux(npcm8xx_clk_data->hws[npcm8xx_muxes[i].onecell_idx]);
+ }
+unregister_refclk:
+ clk_hw_unregister(npcm8xx_clk_data->hws[NPCM8XX_CLK_REFCLK]);
+ return PTR_ERR(hw);
+}
+
+static const struct of_device_id npcm8xx_clk_dt_ids[] = {
+ { .compatible = "nuvoton,npcm845-clk", },
+ { }
+};
+MODULE_DEVICE_TABLE(of, npcm8xx_clk_dt_ids);
+
+static struct platform_driver npcm8xx_clk_driver = {
+ .probe = npcm8xx_clk_probe,
+ .driver = {
+ .name = "npcm8xx_clk",
+ .of_match_table = npcm8xx_clk_dt_ids,
+ },
+};
+
+static int __init npcm8xx_clk_driver_init(void)
+{
+ return platform_driver_register(&npcm8xx_clk_driver);
+}
+arch_initcall(npcm8xx_clk_driver_init);
+
--
2.33.0
Add binding for the Arbel BMC NPCM8XX Clock controller.
Signed-off-by: Tomer Maimon <[email protected]>
---
.../bindings/clock/nuvoton,npcm845-clk.yaml | 49 +++++++++++++++++++
.../dt-bindings/clock/nuvoton,npcm845-clk.h | 49 +++++++++++++++++++
2 files changed, 98 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/nuvoton,npcm845-clk.yaml
create mode 100644 include/dt-bindings/clock/nuvoton,npcm845-clk.h
diff --git a/Documentation/devicetree/bindings/clock/nuvoton,npcm845-clk.yaml b/Documentation/devicetree/bindings/clock/nuvoton,npcm845-clk.yaml
new file mode 100644
index 000000000000..771db2ddf026
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/nuvoton,npcm845-clk.yaml
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/nuvoton,npcm845-clk.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Nuvoton NPCM8XX Clock Controller Binding
+
+maintainers:
+ - Tomer Maimon <[email protected]>
+
+description: |
+ Nuvoton Arbel BMC NPCM8XX contains an integrated clock controller, which
+ generates and supplies clocks to all modules within the BMC.
+
+properties:
+ compatible:
+ enum:
+ - nuvoton,npcm845-clk
+
+ reg:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+ description:
+ See include/dt-bindings/clock/nuvoton,npcm8xx-clock.h for the full
+ list of NPCM8XX clock IDs.
+
+required:
+ - compatible
+ - reg
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ ahb {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ clock-controller@f0801000 {
+ compatible = "nuvoton,npcm845-clk";
+ reg = <0x0 0xf0801000 0x0 0x1000>;
+ #clock-cells = <1>;
+ };
+ };
+...
diff --git a/include/dt-bindings/clock/nuvoton,npcm845-clk.h b/include/dt-bindings/clock/nuvoton,npcm845-clk.h
new file mode 100644
index 000000000000..e5cce08b00e1
--- /dev/null
+++ b/include/dt-bindings/clock/nuvoton,npcm845-clk.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2021 Nuvoton Technologies.
+ * Author: Tomer Maimon <[email protected]>
+ *
+ * Device Tree binding constants for NPCM8XX clock controller.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_NPCM8XX_H
+#define __DT_BINDINGS_CLOCK_NPCM8XX_H
+
+#define NPCM8XX_CLK_CPU 0
+#define NPCM8XX_CLK_GFX_PIXEL 1
+#define NPCM8XX_CLK_MC 2
+#define NPCM8XX_CLK_ADC 3
+#define NPCM8XX_CLK_AHB 4
+#define NPCM8XX_CLK_TIMER 5
+#define NPCM8XX_CLK_UART 6
+#define NPCM8XX_CLK_UART2 7
+#define NPCM8XX_CLK_MMC 8
+#define NPCM8XX_CLK_SPI3 9
+#define NPCM8XX_CLK_PCI 10
+#define NPCM8XX_CLK_AXI 11
+#define NPCM8XX_CLK_APB4 12
+#define NPCM8XX_CLK_APB3 13
+#define NPCM8XX_CLK_APB2 14
+#define NPCM8XX_CLK_APB1 15
+#define NPCM8XX_CLK_APB5 16
+#define NPCM8XX_CLK_CLKOUT 17
+#define NPCM8XX_CLK_GFX 18
+#define NPCM8XX_CLK_SU 19
+#define NPCM8XX_CLK_SU48 20
+#define NPCM8XX_CLK_SDHC 21
+#define NPCM8XX_CLK_SPI0 22
+#define NPCM8XX_CLK_SPI1 23
+#define NPCM8XX_CLK_SPIX 24
+#define NPCM8XX_CLK_RG 25
+#define NPCM8XX_CLK_RCP 26
+#define NPCM8XX_CLK_PRE_ADC 27
+#define NPCM8XX_CLK_ATB 28
+#define NPCM8XX_CLK_PRE_CLK 29
+#define NPCM8XX_CLK_TH 30
+#define NPCM8XX_CLK_REFCLK 31
+#define NPCM8XX_CLK_SYSBYPCK 32
+#define NPCM8XX_CLK_MCBYPCK 33
+
+#define NPCM8XX_NUM_CLOCKS (NPCM8XX_CLK_MCBYPCK + 1)
+
+#endif
--
2.33.0
Add a compatible string for Nuvoton BMC NPCM845 timer.
Signed-off-by: Tomer Maimon <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
---
.../devicetree/bindings/timer/nuvoton,npcm7xx-timer.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/timer/nuvoton,npcm7xx-timer.yaml b/Documentation/devicetree/bindings/timer/nuvoton,npcm7xx-timer.yaml
index 0cbc26a72151..737af78ad70c 100644
--- a/Documentation/devicetree/bindings/timer/nuvoton,npcm7xx-timer.yaml
+++ b/Documentation/devicetree/bindings/timer/nuvoton,npcm7xx-timer.yaml
@@ -8,12 +8,14 @@ title: Nuvoton NPCM7xx timer
maintainers:
- Jonathan Neuschäfer <[email protected]>
+ - Tomer Maimon <[email protected]>
properties:
compatible:
enum:
- nuvoton,wpcm450-timer # for Hermon WPCM450
- nuvoton,npcm750-timer # for Poleg NPCM750
+ - nuvoton,npcm845-timer # for Arbel NPCM845
reg:
maxItems: 1
--
2.33.0
Describe syscon property that handles general control registers (GCR) in
Nuvoton BMC NPCM reset driver.
Signed-off-by: Tomer Maimon <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
---
.../devicetree/bindings/reset/nuvoton,npcm750-reset.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/reset/nuvoton,npcm750-reset.yaml b/Documentation/devicetree/bindings/reset/nuvoton,npcm750-reset.yaml
index fa5e4ea6400e..43a6e77cbf4e 100644
--- a/Documentation/devicetree/bindings/reset/nuvoton,npcm750-reset.yaml
+++ b/Documentation/devicetree/bindings/reset/nuvoton,npcm750-reset.yaml
@@ -19,6 +19,10 @@ properties:
'#reset-cells':
const: 2
+ nuvoton,sysgcr:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: a phandle to access GCR registers.
+
nuvoton,sw-reset-number:
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 1
@@ -31,6 +35,7 @@ required:
- compatible
- reg
- '#reset-cells'
+ - nuvoton,sysgcr
additionalProperties: false
@@ -41,6 +46,7 @@ examples:
compatible = "nuvoton,npcm750-reset";
reg = <0xf0801000 0x70>;
#reset-cells = <2>;
+ nuvoton,sysgcr = <&gcr>;
nuvoton,sw-reset-number = <2>;
};
--
2.33.0
Using syscon device tree property instead of device data to handle the
NPCM general control registers.
In case the syscon not found the code still search for nuvoton,npcm750-gcr
to support DTS backward compatibility.
Signed-off-by: Tomer Maimon <[email protected]>
---
drivers/reset/reset-npcm.c | 17 ++++++++---------
1 file changed, 8 insertions(+), 9 deletions(-)
diff --git a/drivers/reset/reset-npcm.c b/drivers/reset/reset-npcm.c
index 2ea4d3136e15..431ff2b602c5 100644
--- a/drivers/reset/reset-npcm.c
+++ b/drivers/reset/reset-npcm.c
@@ -138,8 +138,7 @@ static int npcm_reset_xlate(struct reset_controller_dev *rcdev,
}
static const struct of_device_id npcm_rc_match[] = {
- { .compatible = "nuvoton,npcm750-reset",
- .data = (void *)"nuvoton,npcm750-gcr" },
+ { .compatible = "nuvoton,npcm750-reset"},
{ }
};
@@ -155,15 +154,15 @@ static int npcm_usb_reset(struct platform_device *pdev, struct npcm_rc_data *rc)
u32 ipsrst1_bits = 0;
u32 ipsrst2_bits = NPCM_IPSRST2_USB_HOST;
u32 ipsrst3_bits = 0;
- const char *gcr_dt;
- gcr_dt = (const char *)
- of_match_device(dev->driver->of_match_table, dev)->data;
-
- gcr_regmap = syscon_regmap_lookup_by_compatible(gcr_dt);
+ gcr_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "nuvoton,sysgcr");
if (IS_ERR(gcr_regmap)) {
- dev_err(&pdev->dev, "Failed to find %s\n", gcr_dt);
- return PTR_ERR(gcr_regmap);
+ dev_warn(&pdev->dev, "Failed to find nuvoton,sysgcr search for nuvoton,npcm750-gcr for Poleg backward compatibility");
+ gcr_regmap = syscon_regmap_lookup_by_compatible("nuvoton,npcm750-gcr");
+ if (IS_ERR(gcr_regmap)) {
+ dev_err(&pdev->dev, "Failed to find nuvoton,npcm750-gcr");
+ return PTR_ERR(gcr_regmap);
+ }
}
/* checking which USB device is enabled */
--
2.33.0
Add nuvoton,sysgcr syscon property to the reset node to handle the general
control registers.
Signed-off-by: Tomer Maimon <[email protected]>
---
arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
index 3696980a3da1..8a2f29016291 100644
--- a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
+++ b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
@@ -110,6 +110,7 @@ rstc: rstc@f0801000 {
compatible = "nuvoton,npcm750-reset";
reg = <0xf0801000 0x70>;
#reset-cells = <2>;
+ nuvoton,sysgcr = <&gcr>;
};
clk: clock-controller@f0801000 {
--
2.33.0
Add a compatible string for Nuvoton BMC NPCM845 UART.
Signed-off-by: Tomer Maimon <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
---
Documentation/devicetree/bindings/serial/8250.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/serial/8250.yaml b/Documentation/devicetree/bindings/serial/8250.yaml
index 5f6b113d378f..6258f5f59b19 100644
--- a/Documentation/devicetree/bindings/serial/8250.yaml
+++ b/Documentation/devicetree/bindings/serial/8250.yaml
@@ -62,6 +62,7 @@ properties:
- const: mrvl,pxa-uart
- const: nuvoton,wpcm450-uart
- const: nuvoton,npcm750-uart
+ - const: nuvoton,npcm845-uart
- const: nvidia,tegra20-uart
- const: nxp,lpc3220-uart
- items:
--
2.33.0
Enable basic drivers for NPCM8XX booting up support: Architecture, Clock,
and WD.
Signed-off-by: Tomer Maimon <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
---
arch/arm64/configs/defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 7d1105343bc2..c4a237a84efa 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -49,6 +49,7 @@ CONFIG_ARCH_MEDIATEK=y
CONFIG_ARCH_MESON=y
CONFIG_ARCH_MVEBU=y
CONFIG_ARCH_MXC=y
+CONFIG_ARCH_NPCM=y
CONFIG_ARCH_QCOM=y
CONFIG_ARCH_RENESAS=y
CONFIG_ARCH_ROCKCHIP=y
@@ -627,6 +628,7 @@ CONFIG_RENESAS_RZG2LWDT=y
CONFIG_UNIPHIER_WATCHDOG=y
CONFIG_PM8916_WATCHDOG=m
CONFIG_BCM2835_WDT=y
+CONFIG_NPCM7XX_WATCHDOG=y
CONFIG_MFD_ALTERA_SYSMGR=y
CONFIG_MFD_BD9571MWV=y
CONFIG_MFD_AXP20X_I2C=y
@@ -1021,6 +1023,7 @@ CONFIG_COMMON_CLK_FSL_SAI=y
CONFIG_COMMON_CLK_S2MPS11=y
CONFIG_COMMON_CLK_PWM=y
CONFIG_COMMON_CLK_VC5=y
+CONFIG_COMMON_CLK_NPCM8XX=y
CONFIG_COMMON_CLK_BD718XX=m
CONFIG_CLK_RASPBERRYPI=m
CONFIG_CLK_IMX8MM=y
--
2.33.0
On 22/06/2022 15:22, Tomer Maimon wrote:
> Add binding for the Arbel BMC NPCM8XX Clock controller.
>
> Signed-off-by: Tomer Maimon <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof