2022-06-22 17:47:45

by Suthikulpanit, Suravee

Subject: [PATCH v3 7/7] iommu/amd: Do not support IOMMUv2 APIs when SNP is enabled

The IOMMUv2 APIs (for supporting shared virtual memory with PASID)
configures the domain with IOMMU v2 page table, and sets DTE[Mode]=0.
This configuration cannot be supported on SNP-enabled system.

Signed-off-by: Suravee Suthikulpanit <[email protected]>
---
drivers/iommu/amd/init.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c
index f5695ccb7c81..4c9b96160a8b 100644
--- a/drivers/iommu/amd/init.c
+++ b/drivers/iommu/amd/init.c
@@ -3448,7 +3448,12 @@ __setup("ivrs_acpihid", parse_ivrs_acpihid);

bool amd_iommu_v2_supported(void)
{
- return amd_iommu_v2_present;
+ /*
+ * Since DTE[Mode]=0 is prohibited on SNP-enabled system
+ * (i.e. EFR[SNPSup]=1), IOMMUv2 page table cannot be used without
+ * setting up IOMMUv1 page table.
+ */
+ return amd_iommu_v2_present && !amd_iommu_snp_en;
}
EXPORT_SYMBOL(amd_iommu_v2_supported);

--
2.32.0

2022-06-23 09:03:07

by Joerg Roedel

Subject: Re: [PATCH v3 7/7] iommu/amd: Do not support IOMMUv2 APIs when SNP is enabled

On Wed, Jun 22, 2022 at 12:11:31PM -0500, Suravee Suthikulpanit wrote:
> bool amd_iommu_v2_supported(void)
> {
> - return amd_iommu_v2_present;
> + /*
> + * Since DTE[Mode]=0 is prohibited on SNP-enabled system
> + * (i.e. EFR[SNPSup]=1), IOMMUv2 page table cannot be used without
> + * setting up IOMMUv1 page table.
> + */
> + return amd_iommu_v2_present && !amd_iommu_snp_en;

IOMMU_v2 APIs could actually be supported with GIOV and IOMMUv2
page-tables in-use, no?

Regards,

Joerg

2022-06-29 12:31:17

by Suthikulpanit, Suravee

Subject: Re: [PATCH v3 7/7] iommu/amd: Do not support IOMMUv2 APIs when SNP is enabled

On 6/23/2022 3:23 PM, Joerg Roedel wrote:
> On Wed, Jun 22, 2022 at 12:11:31PM -0500, Suravee Suthikulpanit wrote:
>> bool amd_iommu_v2_supported(void)
>> {
>> - return amd_iommu_v2_present;
>> + /*
>> + * Since DTE[Mode]=0 is prohibited on SNP-enabled system
>> + * (i.e. EFR[SNPSup]=1), IOMMUv2 page table cannot be used without
>> + * setting up IOMMUv1 page table.
>> + */
>> + return amd_iommu_v2_present && !amd_iommu_snp_en;
>
> IOMMU_v2 APIs could actually be supported with GIOV and IOMMUv2
> page-tables in-use, no?
>
We can support IOMMUv2 iff the v1 table is also setup (i.e. DTE[Mode] != 0).
Currently w/ IOMMU_v2 APIs, the IOMMU sets the mode to zero. Therefore, we
cannot support this use case.

Best Regards,
Suravee