Hi All,
This patch series adds PLIC support for Renesas RZ/Five SoC.
Sending this as an RFC based on the discussion [0].
This patches have been tested with I2C and DMAC interface as these
blocks have EDGE interrupts.
[0] https://lore.kernel.org/linux-arm-kernel/[email protected]/T/
RFC-->v1:
* Fixed review comments pointed by Rob and Geert.
* Changed implementation for EDGE interrupt handling on Renesas RZ/Five SoC.
RFC: https://lore.kernel.org/linux-renesas-soc/
[email protected]/T/
Cheers,
Prabhakar
Lad Prabhakar (2):
dt-bindings: interrupt-controller: sifive,plic: Document Renesas
RZ/Five SoC
irqchip/sifive-plic: Add support for Renesas RZ/Five SoC
.../sifive,plic-1.0.0.yaml | 40 +++++++-
drivers/irqchip/irq-sifive-plic.c | 95 ++++++++++++++++++-
2 files changed, 127 insertions(+), 8 deletions(-)
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2.25.1