Hi All,
This patch series adds PLIC support for Renesas RZ/Five SoC.
Sending this as an RFC based on the discussion [0].
This patches have been tested with I2C and DMAC interface as these
blocks have EDGE interrupts.
[0] https://lore.kernel.org/linux-arm-kernel/[email protected]/T/
v1-v2:
* Fixed review comments pointed by Marc and Krzysztof.
RFC-->v1:
* Fixed review comments pointed by Rob and Geert.
* Changed implementation for EDGE interrupt handling on Renesas RZ/Five SoC.
RFC: https://lore.kernel.org/linux-renesas-soc/
[email protected]/T/
Cheers,
Prabhakar
Lad Prabhakar (2):
dt-bindings: interrupt-controller: sifive,plic: Document Renesas
RZ/Five SoC
irqchip/sifive-plic: Add support for Renesas RZ/Five SoC
.../sifive,plic-1.0.0.yaml | 44 ++++++++++-
drivers/irqchip/Kconfig | 1 +
drivers/irqchip/irq-sifive-plic.c | 73 ++++++++++++++++++-
3 files changed, 113 insertions(+), 5 deletions(-)
--
2.25.1
Document Renesas RZ/Five (R9A07G043) SoC.
Signed-off-by: Lad Prabhakar <[email protected]>
---
v1->v2:
* Fixed binding doc
* Fixed review comments pointed by Krzysztof.
RFC->v1:
* Fixed Review comments pointed by Geert and Rob
---
.../sifive,plic-1.0.0.yaml | 44 +++++++++++++++++--
1 file changed, 41 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
index 27092c6a86c4..59df367d1e44 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -28,7 +28,10 @@ description:
While the PLIC supports both edge-triggered and level-triggered interrupts,
interrupt handlers are oblivious to this distinction and therefore it is not
- specified in the PLIC device-tree binding.
+ specified in the PLIC device-tree binding for SiFive PLIC (and similar PLIC's),
+ but for the Renesas RZ/Five Soc (AX45MP AndesCore) which has NCEPLIC100 we need
+ to specify the interrupt type as the flow for EDGE interrupts is different
+ compared to LEVEL interrupts.
While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
"sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
@@ -57,6 +60,7 @@ properties:
- enum:
- allwinner,sun20i-d1-plic
- const: thead,c900-plic
+ - const: renesas,r9a07g043-plic
reg:
maxItems: 1
@@ -64,8 +68,7 @@ properties:
'#address-cells':
const: 0
- '#interrupt-cells':
- const: 1
+ '#interrupt-cells': true
interrupt-controller: true
@@ -82,6 +85,12 @@ properties:
description:
Specifies how many external interrupts are supported by this controller.
+ clocks: true
+
+ power-domains: true
+
+ resets: true
+
required:
- compatible
- '#address-cells'
@@ -91,6 +100,35 @@ required:
- interrupts-extended
- riscv,ndev
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,r9a07g043-plic
+ then:
+ properties:
+ clocks:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ '#interrupt-cells':
+ const: 2
+
+ required:
+ - clocks
+ - resets
+ - power-domains
+ else:
+ properties:
+ '#interrupt-cells':
+ const: 1
+
additionalProperties: false
examples:
--
2.25.1
On Sun, 26 Jun 2022 01:43:25 +0100,
Lad Prabhakar <[email protected]> wrote:
>
> Document Renesas RZ/Five (R9A07G043) SoC.
>
> Signed-off-by: Lad Prabhakar <[email protected]>
> ---
> v1->v2:
> * Fixed binding doc
> * Fixed review comments pointed by Krzysztof.
>
> RFC->v1:
> * Fixed Review comments pointed by Geert and Rob
> ---
> .../sifive,plic-1.0.0.yaml | 44 +++++++++++++++++--
> 1 file changed, 41 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> index 27092c6a86c4..59df367d1e44 100644
> --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> @@ -28,7 +28,10 @@ description:
>
> While the PLIC supports both edge-triggered and level-triggered interrupts,
> interrupt handlers are oblivious to this distinction and therefore it is not
> - specified in the PLIC device-tree binding.
> + specified in the PLIC device-tree binding for SiFive PLIC (and similar PLIC's),
> + but for the Renesas RZ/Five Soc (AX45MP AndesCore) which has NCEPLIC100 we need
> + to specify the interrupt type as the flow for EDGE interrupts is different
> + compared to LEVEL interrupts.
>
> While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
> "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
> @@ -57,6 +60,7 @@ properties:
> - enum:
> - allwinner,sun20i-d1-plic
> - const: thead,c900-plic
> + - const: renesas,r9a07g043-plic
Since it is the NCEPLIC100 that is broken, shouldn't the compatible
string actually reflect that? I'd rather see 'andes,nceplic100' once
and for all instead of starting with Renesas, quickly followed by all
the other licensees that will inevitably integrate the same IP (which
isn't even specific to the AX45MP).
This IP also comes with all sort of added (mis-)features, which may or
may not be used in the future, and it would make sense to identify it
specifically.
M.
--
Without deviation from the norm, progress is not possible.
Hi Marc,
Thank you for the review.
On Sun, Jun 26, 2022 at 1:35 PM Marc Zyngier <[email protected]> wrote:
>
> On Sun, 26 Jun 2022 01:43:25 +0100,
> Lad Prabhakar <[email protected]> wrote:
> >
> > Document Renesas RZ/Five (R9A07G043) SoC.
> >
> > Signed-off-by: Lad Prabhakar <[email protected]>
> > ---
> > v1->v2:
> > * Fixed binding doc
> > * Fixed review comments pointed by Krzysztof.
> >
> > RFC->v1:
> > * Fixed Review comments pointed by Geert and Rob
> > ---
> > .../sifive,plic-1.0.0.yaml | 44 +++++++++++++++++--
> > 1 file changed, 41 insertions(+), 3 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> > index 27092c6a86c4..59df367d1e44 100644
> > --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> > +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> > @@ -28,7 +28,10 @@ description:
> >
> > While the PLIC supports both edge-triggered and level-triggered interrupts,
> > interrupt handlers are oblivious to this distinction and therefore it is not
> > - specified in the PLIC device-tree binding.
> > + specified in the PLIC device-tree binding for SiFive PLIC (and similar PLIC's),
> > + but for the Renesas RZ/Five Soc (AX45MP AndesCore) which has NCEPLIC100 we need
> > + to specify the interrupt type as the flow for EDGE interrupts is different
> > + compared to LEVEL interrupts.
> >
> > While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
> > "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
> > @@ -57,6 +60,7 @@ properties:
> > - enum:
> > - allwinner,sun20i-d1-plic
> > - const: thead,c900-plic
> > + - const: renesas,r9a07g043-plic
>
> Since it is the NCEPLIC100 that is broken, shouldn't the compatible
> string actually reflect that? I'd rather see 'andes,nceplic100' once
> and for all instead of starting with Renesas, quickly followed by all
> the other licensees that will inevitably integrate the same IP (which
> isn't even specific to the AX45MP).
>
> This IP also comes with all sort of added (mis-)features, which may or
> may not be used in the future, and it would make sense to identify it
> specifically.
>
Agreed, I'll update it as above.
Cheers,
Prabhakar
On 2022-06-27 13:27, Lad, Prabhakar wrote:
> Hi Marc,
>
> Thank you for the review.
>
> On Sun, Jun 26, 2022 at 1:35 PM Marc Zyngier <[email protected]> wrote:
>>
>> On Sun, 26 Jun 2022 01:43:25 +0100,
>> Lad Prabhakar <[email protected]> wrote:
>> >
>> > Document Renesas RZ/Five (R9A07G043) SoC.
>> >
>> > Signed-off-by: Lad Prabhakar <[email protected]>
>> > ---
>> > v1->v2:
>> > * Fixed binding doc
>> > * Fixed review comments pointed by Krzysztof.
>> >
>> > RFC->v1:
>> > * Fixed Review comments pointed by Geert and Rob
>> > ---
>> > .../sifive,plic-1.0.0.yaml | 44 +++++++++++++++++--
>> > 1 file changed, 41 insertions(+), 3 deletions(-)
>> >
>> > diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
>> > index 27092c6a86c4..59df367d1e44 100644
>> > --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
>> > +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
>> > @@ -28,7 +28,10 @@ description:
>> >
>> > While the PLIC supports both edge-triggered and level-triggered interrupts,
>> > interrupt handlers are oblivious to this distinction and therefore it is not
>> > - specified in the PLIC device-tree binding.
>> > + specified in the PLIC device-tree binding for SiFive PLIC (and similar PLIC's),
>> > + but for the Renesas RZ/Five Soc (AX45MP AndesCore) which has NCEPLIC100 we need
>> > + to specify the interrupt type as the flow for EDGE interrupts is different
>> > + compared to LEVEL interrupts.
>> >
>> > While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
>> > "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
>> > @@ -57,6 +60,7 @@ properties:
>> > - enum:
>> > - allwinner,sun20i-d1-plic
>> > - const: thead,c900-plic
>> > + - const: renesas,r9a07g043-plic
>>
>> Since it is the NCEPLIC100 that is broken, shouldn't the compatible
>> string actually reflect that? I'd rather see 'andes,nceplic100' once
>> and for all instead of starting with Renesas, quickly followed by all
>> the other licensees that will inevitably integrate the same IP (which
>> isn't even specific to the AX45MP).
>>
>> This IP also comes with all sort of added (mis-)features, which may or
>> may not be used in the future, and it would make sense to identify it
>> specifically.
>>
> Agreed, I'll update it as above.
Please synchronise with Samuel to have a common series that fixes
both the Renesas and Thead platforms.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
Hi Marc,
On Mon, Jun 27, 2022 at 3:22 PM Marc Zyngier <[email protected]> wrote:
>
> On 2022-06-27 13:27, Lad, Prabhakar wrote:
> > Hi Marc,
> >
> > Thank you for the review.
> >
> > On Sun, Jun 26, 2022 at 1:35 PM Marc Zyngier <[email protected]> wrote:
> >>
> >> On Sun, 26 Jun 2022 01:43:25 +0100,
> >> Lad Prabhakar <[email protected]> wrote:
> >> >
> >> > Document Renesas RZ/Five (R9A07G043) SoC.
> >> >
> >> > Signed-off-by: Lad Prabhakar <[email protected]>
> >> > ---
> >> > v1->v2:
> >> > * Fixed binding doc
> >> > * Fixed review comments pointed by Krzysztof.
> >> >
> >> > RFC->v1:
> >> > * Fixed Review comments pointed by Geert and Rob
> >> > ---
> >> > .../sifive,plic-1.0.0.yaml | 44 +++++++++++++++++--
> >> > 1 file changed, 41 insertions(+), 3 deletions(-)
> >> >
> >> > diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> >> > index 27092c6a86c4..59df367d1e44 100644
> >> > --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> >> > +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> >> > @@ -28,7 +28,10 @@ description:
> >> >
> >> > While the PLIC supports both edge-triggered and level-triggered interrupts,
> >> > interrupt handlers are oblivious to this distinction and therefore it is not
> >> > - specified in the PLIC device-tree binding.
> >> > + specified in the PLIC device-tree binding for SiFive PLIC (and similar PLIC's),
> >> > + but for the Renesas RZ/Five Soc (AX45MP AndesCore) which has NCEPLIC100 we need
> >> > + to specify the interrupt type as the flow for EDGE interrupts is different
> >> > + compared to LEVEL interrupts.
> >> >
> >> > While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
> >> > "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
> >> > @@ -57,6 +60,7 @@ properties:
> >> > - enum:
> >> > - allwinner,sun20i-d1-plic
> >> > - const: thead,c900-plic
> >> > + - const: renesas,r9a07g043-plic
> >>
> >> Since it is the NCEPLIC100 that is broken, shouldn't the compatible
> >> string actually reflect that? I'd rather see 'andes,nceplic100' once
> >> and for all instead of starting with Renesas, quickly followed by all
> >> the other licensees that will inevitably integrate the same IP (which
> >> isn't even specific to the AX45MP).
> >>
> >> This IP also comes with all sort of added (mis-)features, which may or
> >> may not be used in the future, and it would make sense to identify it
> >> specifically.
> >>
> > Agreed, I'll update it as above.
>
> Please synchronise with Samuel to have a common series that fixes
> both the Renesas and Thead platforms.
>
Yes Ive dropped an email to Samuel.
Cheers,
Prabhakar