The MediaTek PCIe driver supports resets from a reset controller and
they're essential for correct initialization of the PCIe controllers.
As a preparation for adding the PCIe nodes to mt8195, add the resets
to dt-bindings and infra_ao clock driver.
AngeloGioacchino Del Regno (2):
dt-bindings: reset: mt8195: Add resets for PCIE controllers
clk: mediatek: mt8195: Add reset idx for PCIe0 and PCIe1
drivers/clk/mediatek/clk-mt8195-infra_ao.c | 2 ++
include/dt-bindings/reset/mt8195-resets.h | 2 ++
2 files changed, 4 insertions(+)
--
2.35.1
Add the reset idx for PCIe P0, P1, located in infra_ao RST2 registers.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
---
drivers/clk/mediatek/clk-mt8195-infra_ao.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/mediatek/clk-mt8195-infra_ao.c b/drivers/clk/mediatek/clk-mt8195-infra_ao.c
index 97657f255618..ce7ac16a2f42 100644
--- a/drivers/clk/mediatek/clk-mt8195-infra_ao.c
+++ b/drivers/clk/mediatek/clk-mt8195-infra_ao.c
@@ -193,6 +193,8 @@ static u16 infra_ao_rst_ofs[] = {
static u16 infra_ao_idx_map[] = {
[MT8195_INFRA_RST0_THERM_CTRL_SWRST] = 0 * RST_NR_PER_BANK + 0,
+ [MT8195_INFRA_RST2_PCIE_P0_SWRST] = 2 * RST_NR_PER_BANK + 26,
+ [MT8195_INFRA_RST2_PCIE_P1_SWRST] = 2 * RST_NR_PER_BANK + 27,
[MT8195_INFRA_RST3_THERM_CTRL_PTP_SWRST] = 3 * RST_NR_PER_BANK + 5,
[MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST] = 4 * RST_NR_PER_BANK + 10,
};
--
2.35.1
Quoting AngeloGioacchino Del Regno (2022-06-29 03:52:05)
> Add the reset idx for PCIe P0, P1, located in infra_ao RST2 registers.
>
> Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
> ---
Applied to clk-next