The patch set in general is to add support for the VSC7512, and
eventually the VSC7511, VSC7513 and VSC7514 devices controlled over
SPI. Specifically this patch set enables pinctrl, serial gpio expander
access, and control of an internal and an external MDIO bus.
I have mentioned previously:
The hardware setup I'm using for development is a beaglebone black, with
jumpers from SPI0 to the microchip VSC7512 dev board. The microchip dev
board has been modified to not boot from flash, but wait for SPI. An
ethernet cable is connected from the beaglebone ethernet to port 0 of
the dev board. Network functionality will be included in a future patch set.
The device tree I'm using is included in the documentation, so I'll not
include that in this cover letter. I have exported the serial GPIOs to the
LEDs, and verified functionality via
"echo heartbeat > sys/class/leds/port0led/trigger"
/ {
vscleds {
compatible = "gpio-leds";
vscled@0 {
label = "port0led";
gpios = <&sgpio_out1 0 0 GPIO_ACTIVE_LOW>;
default-state = "off";
};
vscled@1 {
label = "port0led1";
gpios = <&sgpio_out1 0 1 GPIO_ACTIVE_LOW>;
default-state = "off";
};
[ ... ]
};
};
[ 0.000000] Booting Linux on physical CPU 0x0
[ 0.000000] Linux version 5.19.0-rc3-00745-g30c05ffbecdc (arm-linux-gnueabi-gcc (Ubuntu 9.4.0-1ubuntu1~20.04.1) 9.4.0, GNU ld (GNU Binutils for Ubuntu) 2.34) #826 SMP PREEMPT Fri Jul 1 11:26:44 PDT 2022
...
[ 1.952616] pinctrl-ocelot ocelot-pinctrl.0.auto: DMA mask not set
[ 1.956522] pinctrl-ocelot ocelot-pinctrl.0.auto: driver registered
[ 1.967188] pinctrl-microchip-sgpio ocelot-sgpio.1.auto: DMA mask not set
[ 1.983763] mscc-miim ocelot-miim0.2.auto: DMA mask not set
[ 3.020687] mscc-miim ocelot-miim1.3.auto: DMA mask not set
I only have hardware to test the last patch, so any testers are welcome.
I've been extra cautious about the ocelot_regmap_from_resource helper
function, both before and after the last patch. I accidentally broke it
in the past and would like to avoid doing so again.
RFC history:
v1 (accidentally named vN)
* Initial architecture. Not functional
* General concepts laid out
v2
* Near functional. No CPU port communication, but control over all
external ports
* Cleaned up regmap implementation from v1
v3
* Functional
* Shared MDIO transactions routed through mdio-mscc-miim
* CPU / NPI port enabled by way of vsc7512_enable_npi_port /
felix->info->enable_npi_port
* NPI port tagging functional - Requires a CPU port driver that supports
frames of 1520 bytes. Verified with a patch to the cpsw driver
v4
* Functional
* Device tree fixes
* Add hooks for pinctrl-ocelot - some functionality by way of sysfs
* Add hooks for pinctrl-microsemi-sgpio - not yet fully functional
* Remove lynx_pcs interface for a generic phylink_pcs. The goal here
is to have an ocelot_pcs that will work for each configuration of
every port.
v5
* Restructured to MFD
* Several commits were split out, submitted, and accepted
* pinctrl-ocelot believed to be fully functional (requires commits
from the linux-pinctrl tree)
* External MDIO bus believed to be fully functional
v6
* Applied several suggestions from the last RFC from Lee Jones. I
hope I didn't miss anything.
* Clean up MFD core - SPI interaction. They no longer use callbacks.
* regmaps get registered to the child device, and don't attempt to
get shared. It seems if a regmap is to be shared, that should be
solved with syscon, not dev or mfd.
v7
* Applied as much as I could from Lee and Vladimir's suggestions. As
always, the feedback is greatly appreciated!
* Remove "ocelot_spi" container complication
* Move internal MDIO bus from ocelot_ext to MFD, with a devicetree
change to match
* Add initial HSIO support
* Switch to IORESOURCE_REG for resource definitions
v8
* Applied another round of suggestions from Lee and Vladimir
* Utilize regmap bus reads, which speeds bulk transfers up by an
order of magnitude
* Add two additional patches to utilize phylink_generic_validate
* Changed GPL V2 to GPL in licenses where applicable (checkpatch)
* Remove initial hsio/serdes changes from the RFC
v9
* Submitting as a PATCH instead of an RFC
* Remove switch functionality - will be a separate patch set
* Remove Kconfig tristate module options
* Another round of suggestions from Lee, Vladimir, and Andy. Many
thanks!
* Add documentation
* Update maintainers
v10
* Fix warming by removing unused function
v11
* Suggestions from Rob and Andy. Thanks!
* Add pinctrl module functionality back and fixing those features
* Fix aarch64 compiler error
v12
* Suggestions from Vladimir, Andy, Randy, and Rob. Thanks as always!
* Utilize dev_get_regmap to clean up interfaces
* MFD_OCELOT can be a module
Colin Foster (9):
mfd: ocelot: add helper to get regmap from a resource
net: mdio: mscc-miim: add ability to be used in a non-mmio
configuration
pinctrl: ocelot: allow pinctrl-ocelot to be loaded as a module
pinctrl: ocelot: add ability to be used in a non-mmio configuration
pinctrl: microchip-sgpio: allow sgpio driver to be used as a module
pinctrl: microchip-sgpio: add ability to be used in a non-mmio
configuration
resource: add define macro for register address resources
dt-bindings: mfd: ocelot: add bindings for VSC7512
mfd: ocelot: add support for the vsc7512 chip via spi
.../devicetree/bindings/mfd/mscc,ocelot.yaml | 160 +++++++++
MAINTAINERS | 7 +
drivers/mfd/Kconfig | 18 +
drivers/mfd/Makefile | 2 +
drivers/mfd/ocelot-core.c | 164 +++++++++
drivers/mfd/ocelot-spi.c | 312 ++++++++++++++++++
drivers/mfd/ocelot.h | 28 ++
drivers/net/mdio/mdio-mscc-miim.c | 34 +-
drivers/pinctrl/Kconfig | 4 +-
drivers/pinctrl/pinctrl-microchip-sgpio.c | 14 +-
drivers/pinctrl/pinctrl-ocelot.c | 15 +-
include/linux/ioport.h | 5 +
include/linux/mfd/ocelot.h | 51 +++
13 files changed, 772 insertions(+), 42 deletions(-)
create mode 100644 Documentation/devicetree/bindings/mfd/mscc,ocelot.yaml
create mode 100644 drivers/mfd/ocelot-core.c
create mode 100644 drivers/mfd/ocelot-spi.c
create mode 100644 drivers/mfd/ocelot.h
create mode 100644 include/linux/mfd/ocelot.h
--
2.25.1
As the commit message suggests, this simply adds the ability to select
SGPIO pinctrl as a module. This becomes more practical when the SGPIO
hardware exists on an external chip, controlled indirectly by I2C or SPI.
This commit enables that level of control.
Signed-off-by: Colin Foster <[email protected]>
Reviewed-by: Linus Walleij <[email protected]>
Reviewed-by: Florian Fainelli <[email protected]>
Reviewed-by: Vladimir Oltean <[email protected]>
---
drivers/pinctrl/Kconfig | 2 +-
drivers/pinctrl/pinctrl-microchip-sgpio.c | 6 +++++-
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 257b06752747..40d243bc91f8 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -292,7 +292,7 @@ config PINCTRL_MCP23S08
corresponding interrupt-controller.
config PINCTRL_MICROCHIP_SGPIO
- bool "Pinctrl driver for Microsemi/Microchip Serial GPIO"
+ tristate "Pinctrl driver for Microsemi/Microchip Serial GPIO"
depends on OF
depends on HAS_IOMEM
select GPIOLIB
diff --git a/drivers/pinctrl/pinctrl-microchip-sgpio.c b/drivers/pinctrl/pinctrl-microchip-sgpio.c
index 6f55bf7d5e05..e56074b7e659 100644
--- a/drivers/pinctrl/pinctrl-microchip-sgpio.c
+++ b/drivers/pinctrl/pinctrl-microchip-sgpio.c
@@ -999,6 +999,7 @@ static const struct of_device_id microchip_sgpio_gpio_of_match[] = {
/* sentinel */
}
};
+MODULE_DEVICE_TABLE(of, microchip_sgpio_gpio_of_match);
static struct platform_driver microchip_sgpio_pinctrl_driver = {
.driver = {
@@ -1008,4 +1009,7 @@ static struct platform_driver microchip_sgpio_pinctrl_driver = {
},
.probe = microchip_sgpio_probe,
};
-builtin_platform_driver(microchip_sgpio_pinctrl_driver);
+module_platform_driver(microchip_sgpio_pinctrl_driver);
+
+MODULE_DESCRIPTION("Microchip SGPIO Pinctrl Driver");
+MODULE_LICENSE("GPL");
--
2.25.1
Add devicetree bindings for SPI-controlled Ocelot chips, specifically the
VSC7512.
Signed-off-by: Colin Foster <[email protected]>
---
.../devicetree/bindings/mfd/mscc,ocelot.yaml | 160 ++++++++++++++++++
MAINTAINERS | 1 +
2 files changed, 161 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mfd/mscc,ocelot.yaml
diff --git a/Documentation/devicetree/bindings/mfd/mscc,ocelot.yaml b/Documentation/devicetree/bindings/mfd/mscc,ocelot.yaml
new file mode 100644
index 000000000000..8bf45a5673a4
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/mscc,ocelot.yaml
@@ -0,0 +1,160 @@
+# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/mscc,ocelot.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Ocelot Externally-Controlled Ethernet Switch
+
+maintainers:
+ - Colin Foster <[email protected]>
+
+description: |
+ The Ocelot ethernet switch family contains chips that have an internal CPU
+ (VSC7513, VSC7514) and chips that don't (VSC7511, VSC7512). All switches have
+ the option to be controlled externally, which is the purpose of this driver.
+
+ The switch family is a multi-port networking switch that supports many
+ interfaces. Additionally, the device can perform pin control, MDIO buses, and
+ external GPIO expanders.
+
+properties:
+ compatible:
+ enum:
+ - mscc,vsc7512
+
+ reg:
+ maxItems: 1
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 1
+
+ spi-max-frequency:
+ maxItems: 1
+
+patternProperties:
+ "^pinctrl@[0-9a-f]+$":
+ type: object
+ $ref: /schemas/pinctrl/mscc,ocelot-pinctrl.yaml
+
+ "^gpio@[0-9a-f]+$":
+ type: object
+ $ref: /schemas/pinctrl/microchip,sparx5-sgpio.yaml
+ properties:
+ compatible:
+ enum:
+ - mscc,ocelot-sgpio
+
+ "^mdio@[0-9a-f]+$":
+ type: object
+ $ref: /schemas/net/mscc,miim.yaml
+ properties:
+ compatible:
+ enum:
+ - mscc,ocelot-miim
+
+required:
+ - compatible
+ - reg
+ - '#address-cells'
+ - '#size-cells'
+ - spi-max-frequency
+
+additionalProperties: false
+
+examples:
+ - |
+ ocelot_clock: ocelot-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ soc@0 {
+ compatible = "mscc,vsc7512";
+ spi-max-frequency = <2500000>;
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ mdio@7107009c {
+ compatible = "mscc,ocelot-miim";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x7107009c 0x24>;
+
+ sw_phy0: ethernet-phy@0 {
+ reg = <0x0>;
+ };
+ };
+
+ mdio@710700c0 {
+ compatible = "mscc,ocelot-miim";
+ pinctrl-names = "default";
+ pinctrl-0 = <&miim1_pins>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x710700c0 0x24>;
+
+ sw_phy4: ethernet-phy@4 {
+ reg = <0x4>;
+ };
+ };
+
+ gpio: pinctrl@71070034 {
+ compatible = "mscc,ocelot-pinctrl";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&gpio 0 0 22>;
+ reg = <0x71070034 0x6c>;
+
+ sgpio_pins: sgpio-pins {
+ pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3";
+ function = "sg0";
+ };
+
+ miim1_pins: miim1-pins {
+ pins = "GPIO_14", "GPIO_15";
+ function = "miim";
+ };
+ };
+
+ gpio@710700f8 {
+ compatible = "mscc,ocelot-sgpio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ bus-frequency = <12500000>;
+ clocks = <&ocelot_clock>;
+ microchip,sgpio-port-ranges = <0 15>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sgpio_pins>;
+ reg = <0x710700f8 0x100>;
+
+ sgpio_in0: gpio@0 {
+ compatible = "microchip,sparx5-sgpio-bank";
+ reg = <0>;
+ gpio-controller;
+ #gpio-cells = <3>;
+ ngpios = <64>;
+ };
+
+ sgpio_out1: gpio@1 {
+ compatible = "microchip,sparx5-sgpio-bank";
+ reg = <1>;
+ gpio-controller;
+ #gpio-cells = <3>;
+ ngpios = <64>;
+ };
+ };
+ };
+ };
+
+...
+
diff --git a/MAINTAINERS b/MAINTAINERS
index c2f61ed1b730..a67828cbda20 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -14416,6 +14416,7 @@ F: tools/testing/selftests/drivers/net/ocelot/*
OCELOT EXTERNAL SWITCH CONTROL
M: Colin Foster <[email protected]>
S: Supported
+F: Documentation/devicetree/bindings/mfd/mscc,ocelot.yaml
F: include/linux/mfd/ocelot.h
OCXL (Open Coherent Accelerator Processor Interface OpenCAPI) DRIVER
--
2.25.1
On Tue, Jul 05, 2022 at 02:24:22PM -0600, Rob Herring wrote:
> On Fri, Jul 01, 2022 at 12:26:00PM -0700, Colin Foster wrote:
> > The patch set in general is to add support for the VSC7512, and
> > eventually the VSC7511, VSC7513 and VSC7514 devices controlled over
> > SPI. Specifically this patch set enables pinctrl, serial gpio expander
> > access, and control of an internal and an external MDIO bus.
> >
> > I have mentioned previously:
> > The hardware setup I'm using for development is a beaglebone black, with
> > jumpers from SPI0 to the microchip VSC7512 dev board. The microchip dev
> > board has been modified to not boot from flash, but wait for SPI. An
> > ethernet cable is connected from the beaglebone ethernet to port 0 of
> > the dev board. Network functionality will be included in a future patch set.
> >
> > The device tree I'm using is included in the documentation, so I'll not
> > include that in this cover letter. I have exported the serial GPIOs to the
> > LEDs, and verified functionality via
> > "echo heartbeat > sys/class/leds/port0led/trigger"
> >
> > / {
> > vscleds {
> > compatible = "gpio-leds";
> > vscled@0 {
> > label = "port0led";
> > gpios = <&sgpio_out1 0 0 GPIO_ACTIVE_LOW>;
> > default-state = "off";
> > };
> > vscled@1 {
> > label = "port0led1";
> > gpios = <&sgpio_out1 0 1 GPIO_ACTIVE_LOW>;
> > default-state = "off";
> > };
> > [ ... ]
> > };
> > };
> >
> > [ 0.000000] Booting Linux on physical CPU 0x0
> > [ 0.000000] Linux version 5.19.0-rc3-00745-g30c05ffbecdc (arm-linux-gnueabi-gcc (Ubuntu 9.4.0-1ubuntu1~20.04.1) 9.4.0, GNU ld (GNU Binutils for Ubuntu) 2.34) #826 SMP PREEMPT Fri Jul 1 11:26:44 PDT 2022
> > ...
> > [ 1.952616] pinctrl-ocelot ocelot-pinctrl.0.auto: DMA mask not set
> > [ 1.956522] pinctrl-ocelot ocelot-pinctrl.0.auto: driver registered
> > [ 1.967188] pinctrl-microchip-sgpio ocelot-sgpio.1.auto: DMA mask not set
> > [ 1.983763] mscc-miim ocelot-miim0.2.auto: DMA mask not set
> > [ 3.020687] mscc-miim ocelot-miim1.3.auto: DMA mask not set
> >
> >
> > I only have hardware to test the last patch, so any testers are welcome.
> > I've been extra cautious about the ocelot_regmap_from_resource helper
> > function, both before and after the last patch. I accidentally broke it
> > in the past and would like to avoid doing so again.
> >
> >
> > RFC history:
> > v1 (accidentally named vN)
> > * Initial architecture. Not functional
> > * General concepts laid out
> >
> > v2
> > * Near functional. No CPU port communication, but control over all
> > external ports
> > * Cleaned up regmap implementation from v1
> >
> > v3
> > * Functional
> > * Shared MDIO transactions routed through mdio-mscc-miim
> > * CPU / NPI port enabled by way of vsc7512_enable_npi_port /
> > felix->info->enable_npi_port
> > * NPI port tagging functional - Requires a CPU port driver that supports
> > frames of 1520 bytes. Verified with a patch to the cpsw driver
> >
> > v4
> > * Functional
> > * Device tree fixes
> > * Add hooks for pinctrl-ocelot - some functionality by way of sysfs
> > * Add hooks for pinctrl-microsemi-sgpio - not yet fully functional
> > * Remove lynx_pcs interface for a generic phylink_pcs. The goal here
> > is to have an ocelot_pcs that will work for each configuration of
> > every port.
> >
> > v5
> > * Restructured to MFD
> > * Several commits were split out, submitted, and accepted
> > * pinctrl-ocelot believed to be fully functional (requires commits
> > from the linux-pinctrl tree)
> > * External MDIO bus believed to be fully functional
> >
> > v6
> > * Applied several suggestions from the last RFC from Lee Jones. I
> > hope I didn't miss anything.
> > * Clean up MFD core - SPI interaction. They no longer use callbacks.
> > * regmaps get registered to the child device, and don't attempt to
> > get shared. It seems if a regmap is to be shared, that should be
> > solved with syscon, not dev or mfd.
> >
> > v7
> > * Applied as much as I could from Lee and Vladimir's suggestions. As
> > always, the feedback is greatly appreciated!
> > * Remove "ocelot_spi" container complication
> > * Move internal MDIO bus from ocelot_ext to MFD, with a devicetree
> > change to match
> > * Add initial HSIO support
> > * Switch to IORESOURCE_REG for resource definitions
> >
> > v8
> > * Applied another round of suggestions from Lee and Vladimir
> > * Utilize regmap bus reads, which speeds bulk transfers up by an
> > order of magnitude
> > * Add two additional patches to utilize phylink_generic_validate
> > * Changed GPL V2 to GPL in licenses where applicable (checkpatch)
> > * Remove initial hsio/serdes changes from the RFC
> >
> > v9
> > * Submitting as a PATCH instead of an RFC
> > * Remove switch functionality - will be a separate patch set
> > * Remove Kconfig tristate module options
> > * Another round of suggestions from Lee, Vladimir, and Andy. Many
> > thanks!
> > * Add documentation
> > * Update maintainers
> >
> > v10
> > * Fix warming by removing unused function
> >
> > v11
> > * Suggestions from Rob and Andy. Thanks!
> > * Add pinctrl module functionality back and fixing those features
> > * Fix aarch64 compiler error
> >
> > v12
> > * Suggestions from Vladimir, Andy, Randy, and Rob. Thanks as always!
>
> Not all that useful as a changelog. I have no idea what I told you as
> that was probably 100s of reviews ago. When writing changelogs for patch
> revisions, you need to describe what changed. And it's best to put that
> into the relevant patch. IOW, I want to know what I said to change so I
> know what I need to look at again in particular.
>
> And now that I've found v11, 'suggestions from Rob' isn't really
> accurate as you fixed errors reported by running the tools.
>
> Rob
Good point - I'll be more clear going forward.
On Fri, Jul 01, 2022 at 12:26:00PM -0700, Colin Foster wrote:
> The patch set in general is to add support for the VSC7512, and
> eventually the VSC7511, VSC7513 and VSC7514 devices controlled over
> SPI. Specifically this patch set enables pinctrl, serial gpio expander
> access, and control of an internal and an external MDIO bus.
>
> I have mentioned previously:
> The hardware setup I'm using for development is a beaglebone black, with
> jumpers from SPI0 to the microchip VSC7512 dev board. The microchip dev
> board has been modified to not boot from flash, but wait for SPI. An
> ethernet cable is connected from the beaglebone ethernet to port 0 of
> the dev board. Network functionality will be included in a future patch set.
>
> The device tree I'm using is included in the documentation, so I'll not
> include that in this cover letter. I have exported the serial GPIOs to the
> LEDs, and verified functionality via
> "echo heartbeat > sys/class/leds/port0led/trigger"
>
> / {
> vscleds {
> compatible = "gpio-leds";
> vscled@0 {
> label = "port0led";
> gpios = <&sgpio_out1 0 0 GPIO_ACTIVE_LOW>;
> default-state = "off";
> };
> vscled@1 {
> label = "port0led1";
> gpios = <&sgpio_out1 0 1 GPIO_ACTIVE_LOW>;
> default-state = "off";
> };
> [ ... ]
> };
> };
>
> [ 0.000000] Booting Linux on physical CPU 0x0
> [ 0.000000] Linux version 5.19.0-rc3-00745-g30c05ffbecdc (arm-linux-gnueabi-gcc (Ubuntu 9.4.0-1ubuntu1~20.04.1) 9.4.0, GNU ld (GNU Binutils for Ubuntu) 2.34) #826 SMP PREEMPT Fri Jul 1 11:26:44 PDT 2022
> ...
> [ 1.952616] pinctrl-ocelot ocelot-pinctrl.0.auto: DMA mask not set
> [ 1.956522] pinctrl-ocelot ocelot-pinctrl.0.auto: driver registered
> [ 1.967188] pinctrl-microchip-sgpio ocelot-sgpio.1.auto: DMA mask not set
> [ 1.983763] mscc-miim ocelot-miim0.2.auto: DMA mask not set
> [ 3.020687] mscc-miim ocelot-miim1.3.auto: DMA mask not set
>
>
> I only have hardware to test the last patch, so any testers are welcome.
> I've been extra cautious about the ocelot_regmap_from_resource helper
> function, both before and after the last patch. I accidentally broke it
> in the past and would like to avoid doing so again.
>
>
> RFC history:
> v1 (accidentally named vN)
> * Initial architecture. Not functional
> * General concepts laid out
>
> v2
> * Near functional. No CPU port communication, but control over all
> external ports
> * Cleaned up regmap implementation from v1
>
> v3
> * Functional
> * Shared MDIO transactions routed through mdio-mscc-miim
> * CPU / NPI port enabled by way of vsc7512_enable_npi_port /
> felix->info->enable_npi_port
> * NPI port tagging functional - Requires a CPU port driver that supports
> frames of 1520 bytes. Verified with a patch to the cpsw driver
>
> v4
> * Functional
> * Device tree fixes
> * Add hooks for pinctrl-ocelot - some functionality by way of sysfs
> * Add hooks for pinctrl-microsemi-sgpio - not yet fully functional
> * Remove lynx_pcs interface for a generic phylink_pcs. The goal here
> is to have an ocelot_pcs that will work for each configuration of
> every port.
>
> v5
> * Restructured to MFD
> * Several commits were split out, submitted, and accepted
> * pinctrl-ocelot believed to be fully functional (requires commits
> from the linux-pinctrl tree)
> * External MDIO bus believed to be fully functional
>
> v6
> * Applied several suggestions from the last RFC from Lee Jones. I
> hope I didn't miss anything.
> * Clean up MFD core - SPI interaction. They no longer use callbacks.
> * regmaps get registered to the child device, and don't attempt to
> get shared. It seems if a regmap is to be shared, that should be
> solved with syscon, not dev or mfd.
>
> v7
> * Applied as much as I could from Lee and Vladimir's suggestions. As
> always, the feedback is greatly appreciated!
> * Remove "ocelot_spi" container complication
> * Move internal MDIO bus from ocelot_ext to MFD, with a devicetree
> change to match
> * Add initial HSIO support
> * Switch to IORESOURCE_REG for resource definitions
>
> v8
> * Applied another round of suggestions from Lee and Vladimir
> * Utilize regmap bus reads, which speeds bulk transfers up by an
> order of magnitude
> * Add two additional patches to utilize phylink_generic_validate
> * Changed GPL V2 to GPL in licenses where applicable (checkpatch)
> * Remove initial hsio/serdes changes from the RFC
>
> v9
> * Submitting as a PATCH instead of an RFC
> * Remove switch functionality - will be a separate patch set
> * Remove Kconfig tristate module options
> * Another round of suggestions from Lee, Vladimir, and Andy. Many
> thanks!
> * Add documentation
> * Update maintainers
>
> v10
> * Fix warming by removing unused function
>
> v11
> * Suggestions from Rob and Andy. Thanks!
> * Add pinctrl module functionality back and fixing those features
> * Fix aarch64 compiler error
>
> v12
> * Suggestions from Vladimir, Andy, Randy, and Rob. Thanks as always!
Not all that useful as a changelog. I have no idea what I told you as
that was probably 100s of reviews ago. When writing changelogs for patch
revisions, you need to describe what changed. And it's best to put that
into the relevant patch. IOW, I want to know what I said to change so I
know what I need to look at again in particular.
And now that I've found v11, 'suggestions from Rob' isn't really
accurate as you fixed errors reported by running the tools.
Rob
On Fri, 01 Jul 2022 12:26:08 -0700, Colin Foster wrote:
> Add devicetree bindings for SPI-controlled Ocelot chips, specifically the
> VSC7512.
>
> Signed-off-by: Colin Foster <[email protected]>
> ---
> .../devicetree/bindings/mfd/mscc,ocelot.yaml | 160 ++++++++++++++++++
> MAINTAINERS | 1 +
> 2 files changed, 161 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mfd/mscc,ocelot.yaml
>
Reviewed-by: Rob Herring <[email protected]>
On Tue, Jul 05, 2022 at 01:30:15PM -0700, Colin Foster wrote:
> > Not all that useful as a changelog. I have no idea what I told you as
> > that was probably 100s of reviews ago. When writing changelogs for patch
> > revisions, you need to describe what changed. And it's best to put that
> > into the relevant patch. IOW, I want to know what I said to change so I
> > know what I need to look at again in particular.
> >
> > And now that I've found v11, 'suggestions from Rob' isn't really
> > accurate as you fixed errors reported by running the tools.
> >
> > Rob
>
> Good point - I'll be more clear going forward.
I have to say I agree with Rob, and no, you weren't more clear in the
v13 you've just posted.
First, you need to understand that a patch set with 13 revisions is on
the long side. You can't honestly expect reviewers' attention span to
last months.
Now, ok, you're at v13 already, entropy goes forward, what can you do.
First, you can link to previous versions in the cover letter, and also
parallel series containing sub-groups of patches. This information needs
to be carried throughout. I spent too long tracking your patch set
numbering system, with change sets that sometimes cover DSA and
sometimes don't, then they sometimes fork into separate series.
I lost track, let's put it this way. I'm not an expert, but I spent my
fair share of time with VSC751X datasheets and I am theoretically aware
what this patch set is trying to do, but I'm still lost.
Then, each patch needs to contain a version history of its own, in
between the "---" marker and the git short stat. Look at other patch
sets for examples. This must contain a description of the delta compared
to the previous version, including commit message rewording.
In extreme cases of large patch sets with essentially minimal changes
from version to version, maybe even the output of "git range-diff" could
be considered to be posted in the cover letter (that's rare though, but
it might help).
Generally, what you want to avoid is changing your mind in the middle of
a long patch set, especially without traceability (without being asked
to do so). Traceability here also means including links to review
feedback asking to make a design change. It may also help if you reply
to your own patch sets stating that you've found a problem in your own
code, and that you're thinking about solving it in this or that way,
even if you don't intend to get any reply.
You may even try to ask someone whom you're not working very closely
with to proof-read your patch sets and get an honest feedback "hey, are
you even following what I'm saying here? could you summarize why I'm
making the changes I'm making, and is this series generally progressing
towards a resolve?"
You got some feedback at v11 (I believe) from Jakub about reposting too
soon. The phrasing was relatively rude and I'm not sure that you got the
central idea right. Large patch sets are generally less welcome when
submitted back to back compared to small ones, but they still need to be
posted frequent enough to not lose reviewers' attention. And small
fixups to fix a build as module are not going to make a huge difference
when reviewing, so it's best not to dig your own grave by gratuitously
bumping the version number just for a compilation fix. Again, replying
to your own patch saying "X was supposed to be Y, otherwise please go on
reviewing", may help.
Also, ordering. I don't necessarily care what changed between v1 and v2
when you post v13. So you could start with the changelog for v13 and go
back in time from there, so that reviewers don't have to scroll more and
more for each revision.
On Wed, Jul 06, 2022 at 01:04:32AM +0300, Vladimir Oltean wrote:
> You got some feedback at v11 (I believe) from Jakub about reposting too
> soon. The phrasing was relatively rude and I'm not sure that you got the
> central idea right. Large patch sets are generally less welcome when
> submitted back to back compared to small ones, but they still need to be
> posted frequent enough to not lose reviewers' attention. And small
> fixups to fix a build as module are not going to make a huge difference
> when reviewing, so it's best not to dig your own grave by gratuitously
> bumping the version number just for a compilation fix. Again, replying
> to your own patch saying "X was supposed to be Y, otherwise please go on
> reviewing", may help.
I hope I'm not coming off as a know-it-all by saying this, and I didn't
intend to make you feel bad. Ask me how do I know, and the answer will
be by making the same mistakes, of course.
Not sure if he's already on your radar, but you can watch and analyze
the patches submitted by Russell King. For example the recent patch set
for making phylink accept DSA CPU port OF nodes with no fixed-link or
phy-handle. Perfect timing in resubmitting a new series when one was
due, even when the previous one got no feedback whatsoever (which seems
to be the hardest situation to deal with). You need to be able to take
decisions even when you're doing so on your own, and much of that comes
with experience.
On Tue, Jul 05, 2022 at 10:56:26PM +0000, Vladimir Oltean wrote:
> On Wed, Jul 06, 2022 at 01:04:32AM +0300, Vladimir Oltean wrote:
> > You got some feedback at v11 (I believe) from Jakub about reposting too
> > soon. The phrasing was relatively rude and I'm not sure that you got the
> > central idea right. Large patch sets are generally less welcome when
> > submitted back to back compared to small ones, but they still need to be
> > posted frequent enough to not lose reviewers' attention. And small
> > fixups to fix a build as module are not going to make a huge difference
> > when reviewing, so it's best not to dig your own grave by gratuitously
> > bumping the version number just for a compilation fix. Again, replying
> > to your own patch saying "X was supposed to be Y, otherwise please go on
> > reviewing", may help.
>
> I hope I'm not coming off as a know-it-all by saying this, and I didn't
> intend to make you feel bad. Ask me how do I know, and the answer will
> be by making the same mistakes, of course.
No worries, but thanks for the concern. I understand the v10 fiasco
was my fault - I'm alright with being put in my place. This is very much
a learning experience for me, so all this feedback helps.
And I also am recognizing a difference being past the RFC stage. The
changes are becoming more subtle, while the initial RFCs had pretty
significant rewrites / restructures. I'll be mindful of this going
forward, and call out any changes I come across in self-review.
>
> Not sure if he's already on your radar, but you can watch and analyze
> the patches submitted by Russell King. For example the recent patch set
> for making phylink accept DSA CPU port OF nodes with no fixed-link or
> phy-handle. Perfect timing in resubmitting a new series when one was
> due, even when the previous one got no feedback whatsoever (which seems
> to be the hardest situation to deal with). You need to be able to take
> decisions even when you're doing so on your own, and much of that comes
> with experience.
I see the cadence of every 5-7 days or so seems to be the sweet spot. I
had thought this v13 would have been long enough since v12 (4 days) but
that seems to have been incorrect (understanding it was over a weekend).
I'll be more mindful of this in the future.