2022-07-05 19:25:52

by Robert Marko

Subject: [PATCH v5 1/3] clk: qcom: clk-alpha-pll: add support for APSS PLL

APSS PLL type will be used by the IPQ8074 APSS driver for providing the
CPU core clocks and enabling CPU Frequency scaling.

This is ported from the downstream 5.4 kernel.

Signed-off-by: Robert Marko <[email protected]>
---
drivers/clk/qcom/clk-alpha-pll.c | 12 ++++++++++++
drivers/clk/qcom/clk-alpha-pll.h | 1 +
2 files changed, 13 insertions(+)

diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index 4406cf609aae..8270363ff98e 100644
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -154,6 +154,18 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
[PLL_OFF_TEST_CTL_U] = 0x30,
[PLL_OFF_TEST_CTL_U1] = 0x34,
},
+ [CLK_ALPHA_PLL_TYPE_APSS] = {
+ [PLL_OFF_L_VAL] = 0x08,
+ [PLL_OFF_ALPHA_VAL] = 0x10,
+ [PLL_OFF_ALPHA_VAL_U] = 0xff,
+ [PLL_OFF_USER_CTL] = 0x18,
+ [PLL_OFF_USER_CTL_U] = 0xff,
+ [PLL_OFF_CONFIG_CTL] = 0x20,
+ [PLL_OFF_CONFIG_CTL_U] = 0x24,
+ [PLL_OFF_TEST_CTL] = 0x30,
+ [PLL_OFF_TEST_CTL_U] = 0x34,
+ [PLL_OFF_STATUS] = 0x28,
+ },
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);

diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h
index 6e9907deaf30..626fdf80336d 100644
--- a/drivers/clk/qcom/clk-alpha-pll.h
+++ b/drivers/clk/qcom/clk-alpha-pll.h
@@ -18,6 +18,7 @@ enum {
CLK_ALPHA_PLL_TYPE_AGERA,
CLK_ALPHA_PLL_TYPE_ZONDA,
CLK_ALPHA_PLL_TYPE_LUCID_EVO,
+ CLK_ALPHA_PLL_TYPE_APSS,
CLK_ALPHA_PLL_TYPE_MAX,
};

--
2.36.1

2022-07-05 19:53:05

by Robert Marko

Subject: [PATCH v5 2/3] dt-bindings: clock: Add support for IPQ8074 APSS clock controller

Add dt-binding for the IPQ8074 APSS clock controller which provides
clocks to the CPU cores.

Signed-off-by: Robert Marko <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
---
Changes in v4:
* Dual license the bindings
* Update the copyright year

Changes in v2:
* Correct subject
---
include/dt-bindings/clock/qcom,apss-ipq8074.h | 14 ++++++++++++++
1 file changed, 14 insertions(+)
create mode 100644 include/dt-bindings/clock/qcom,apss-ipq8074.h

diff --git a/include/dt-bindings/clock/qcom,apss-ipq8074.h b/include/dt-bindings/clock/qcom,apss-ipq8074.h
new file mode 100644
index 000000000000..32538c9311ff
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,apss-ipq8074.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2022, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_QCA_APSS_IPQ8074_H
+#define _DT_BINDINGS_CLOCK_QCA_APSS_IPQ8074_H
+
+#define APSS_PLL_EARLY 0
+#define APSS_PLL 1
+#define APCS_ALIAS0_CLK_SRC 2
+#define APCS_ALIAS0_CORE_CLK 3
+
+#endif
--
2.36.1

2022-07-06 13:29:26

by Konrad Dybcio

Subject: Re: [PATCH v5 1/3] clk: qcom: clk-alpha-pll: add support for APSS PLL

On 5.07.2022 21:10, Robert Marko wrote:
> APSS PLL type will be used by the IPQ8074 APSS driver for providing the
> CPU core clocks and enabling CPU Frequency scaling.
>
> This is ported from the downstream 5.4 kernel.
>
> Signed-off-by: Robert Marko <[email protected]>
> ---
> drivers/clk/qcom/clk-alpha-pll.c | 12 ++++++++++++
> drivers/clk/qcom/clk-alpha-pll.h | 1 +
> 2 files changed, 13 insertions(+)
>
> diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
> index 4406cf609aae..8270363ff98e 100644
> --- a/drivers/clk/qcom/clk-alpha-pll.c
> +++ b/drivers/clk/qcom/clk-alpha-pll.c
> @@ -154,6 +154,18 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
> [PLL_OFF_TEST_CTL_U] = 0x30,
> [PLL_OFF_TEST_CTL_U1] = 0x34,
> },
> + [CLK_ALPHA_PLL_TYPE_APSS] = {
The name is surely not correct, can somebody from qcom chime in
and suggest what it should be?

Konrad
> + [PLL_OFF_L_VAL] = 0x08,
> + [PLL_OFF_ALPHA_VAL] = 0x10,
> + [PLL_OFF_ALPHA_VAL_U] = 0xff,
> + [PLL_OFF_USER_CTL] = 0x18,
> + [PLL_OFF_USER_CTL_U] = 0xff,
> + [PLL_OFF_CONFIG_CTL] = 0x20,
> + [PLL_OFF_CONFIG_CTL_U] = 0x24,
> + [PLL_OFF_TEST_CTL] = 0x30,
> + [PLL_OFF_TEST_CTL_U] = 0x34,
> + [PLL_OFF_STATUS] = 0x28,
> + },
> };
> EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
>
> diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h
> index 6e9907deaf30..626fdf80336d 100644
> --- a/drivers/clk/qcom/clk-alpha-pll.h
> +++ b/drivers/clk/qcom/clk-alpha-pll.h
> @@ -18,6 +18,7 @@ enum {
> CLK_ALPHA_PLL_TYPE_AGERA,
> CLK_ALPHA_PLL_TYPE_ZONDA,
> CLK_ALPHA_PLL_TYPE_LUCID_EVO,
> + CLK_ALPHA_PLL_TYPE_APSS,
> CLK_ALPHA_PLL_TYPE_MAX,
> };
>

2022-07-08 13:46:47

by Robert Marko

Subject: Re: [PATCH v5 1/3] clk: qcom: clk-alpha-pll: add support for APSS PLL

On Wed, 6 Jul 2022 at 15:14, Konrad Dybcio <[email protected]> wrote:
>
>
>
> On 5.07.2022 21:10, Robert Marko wrote:
> > APSS PLL type will be used by the IPQ8074 APSS driver for providing the
> > CPU core clocks and enabling CPU Frequency scaling.
> >
> > This is ported from the downstream 5.4 kernel.
> >
> > Signed-off-by: Robert Marko <[email protected]>
> > ---
> > drivers/clk/qcom/clk-alpha-pll.c | 12 ++++++++++++
> > drivers/clk/qcom/clk-alpha-pll.h | 1 +
> > 2 files changed, 13 insertions(+)
> >
> > diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
> > index 4406cf609aae..8270363ff98e 100644
> > --- a/drivers/clk/qcom/clk-alpha-pll.c
> > +++ b/drivers/clk/qcom/clk-alpha-pll.c
> > @@ -154,6 +154,18 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
> > [PLL_OFF_TEST_CTL_U] = 0x30,
> > [PLL_OFF_TEST_CTL_U1] = 0x34,
> > },
> > + [CLK_ALPHA_PLL_TYPE_APSS] = {
> The name is surely not correct, can somebody from qcom chime in
> and suggest what it should be?

Hi Konrad,
That is how Qualcomm refers to the type in the downstream 4.4 and 5.4 kernels.
I dont have any other reference to the name unless somebody from
Qualcomm can chime in.

Regards,
Robert
>
> Konrad
> > + [PLL_OFF_L_VAL] = 0x08,
> > + [PLL_OFF_ALPHA_VAL] = 0x10,
> > + [PLL_OFF_ALPHA_VAL_U] = 0xff,
> > + [PLL_OFF_USER_CTL] = 0x18,
> > + [PLL_OFF_USER_CTL_U] = 0xff,
> > + [PLL_OFF_CONFIG_CTL] = 0x20,
> > + [PLL_OFF_CONFIG_CTL_U] = 0x24,
> > + [PLL_OFF_TEST_CTL] = 0x30,
> > + [PLL_OFF_TEST_CTL_U] = 0x34,
> > + [PLL_OFF_STATUS] = 0x28,
> > + },
> > };
> > EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
> >
> > diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h
> > index 6e9907deaf30..626fdf80336d 100644
> > --- a/drivers/clk/qcom/clk-alpha-pll.h
> > +++ b/drivers/clk/qcom/clk-alpha-pll.h
> > @@ -18,6 +18,7 @@ enum {
> > CLK_ALPHA_PLL_TYPE_AGERA,
> > CLK_ALPHA_PLL_TYPE_ZONDA,
> > CLK_ALPHA_PLL_TYPE_LUCID_EVO,
> > + CLK_ALPHA_PLL_TYPE_APSS,
> > CLK_ALPHA_PLL_TYPE_MAX,
> > };
> >