2022-07-05 19:27:32

by Robert Marko

Subject: [PATCH v5 1/3] mailbox: qcom-apcs-ipc: add IPQ8074 APSS clock controller support

IPQ8074 has the APSS clock controller utilizing the same register space as
the APCS, so provide access to the APSS utilizing a child device like
IPQ6018 does as well, but just by utilizing the IPQ8074 specific APSS
clock driver.

Also, APCS register space in IPQ8074 is 0x6000 so max_register needs to be
updated to 0x5ffc.

Signed-off-by: Robert Marko <[email protected]>
---
Changes in v5:
* Use lower case hex for max_register
* Update the APSS clock name to match the new one without commas
---
drivers/mailbox/qcom-apcs-ipc-mailbox.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
index 80a54d81412e..4ef7e917a911 100644
--- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c
+++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
@@ -33,6 +33,10 @@ static const struct qcom_apcs_ipc_data ipq6018_apcs_data = {
.offset = 8, .clk_name = "qcom,apss-ipq6018-clk"
};

+static const struct qcom_apcs_ipc_data ipq8074_apcs_data = {
+ .offset = 8, .clk_name = "qcom-apss-ipq8074-clk"
+};
+
static const struct qcom_apcs_ipc_data msm8916_apcs_data = {
.offset = 8, .clk_name = "qcom-apcs-msm8916-clk"
};
@@ -57,7 +61,7 @@ static const struct regmap_config apcs_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
- .max_register = 0x1008,
+ .max_register = 0x5ffc,
.fast_io = true,
};

@@ -142,7 +146,7 @@ static int qcom_apcs_ipc_remove(struct platform_device *pdev)
/* .data is the offset of the ipc register within the global block */
static const struct of_device_id qcom_apcs_ipc_of_match[] = {
{ .compatible = "qcom,ipq6018-apcs-apps-global", .data = &ipq6018_apcs_data },
- { .compatible = "qcom,ipq8074-apcs-apps-global", .data = &msm8994_apcs_data },
+ { .compatible = "qcom,ipq8074-apcs-apps-global", .data = &ipq8074_apcs_data },
{ .compatible = "qcom,msm8916-apcs-kpss-global", .data = &msm8916_apcs_data },
{ .compatible = "qcom,msm8939-apcs-kpss-global", .data = &msm8916_apcs_data },
{ .compatible = "qcom,msm8953-apcs-kpss-global", .data = &msm8994_apcs_data },
--
2.36.1

2022-07-06 09:00:41

by Dmitry Baryshkov

Subject: Re: [PATCH v5 1/3] mailbox: qcom-apcs-ipc: add IPQ8074 APSS clock controller support

On Tue, 5 Jul 2022 at 22:13, Robert Marko <[email protected]> wrote:
>
> IPQ8074 has the APSS clock controller utilizing the same register space as
> the APCS, so provide access to the APSS utilizing a child device like
> IPQ6018 does as well, but just by utilizing the IPQ8074 specific APSS
> clock driver.
>
> Also, APCS register space in IPQ8074 is 0x6000 so max_register needs to be
> updated to 0x5ffc.

As you can see, this was changed to support SDX55. Please either make
this configurable, or leave it as it is.

>
> Signed-off-by: Robert Marko <[email protected]>
> ---
> Changes in v5:
> * Use lower case hex for max_register
> * Update the APSS clock name to match the new one without commas
> ---
> drivers/mailbox/qcom-apcs-ipc-mailbox.c | 8 ++++++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>

--
With best wishes
Dmitry