This patch series add definitions for PCIe legacy INTx interrupts into
every DTS file used by the pci-mvebu.c controller driver.
It was tested on 88F6820 (A385) and 88F6281 (Kirkwood) SoCs.
Pali Rohár (11):
ARM: dts: kirkwood: Add definitions for PCIe legacy INTx interrupts
ARM: dts: dove: Add definitions for PCIe legacy INTx interrupts
ARM: dts: armada-370.dtsi: Add definitions for PCIe legacy INTx
interrupts
ARM: dts: armada-xp-98dx3236.dtsi: Add definitions for PCIe legacy
INTx interrupts
ARM: dts: armada-xp-mv78230.dtsi: Add definitions for PCIe legacy INTx
interrupts
ARM: dts: armada-xp-mv78260.dtsi: Add definitions for PCIe legacy INTx
interrupts
ARM: dts: armada-xp-mv78460.dtsi: Add definitions for PCIe legacy INTx
interrupts
ARM: dts: armada-375.dtsi: Add definitions for PCIe legacy INTx
interrupts
ARM: dts: armada-380.dtsi: Add definitions for PCIe legacy INTx
interrupts
ARM: dts: armada-385.dtsi: Add definitions for PCIe legacy INTx
interrupts
ARM: dts: armada-39x.dtsi: Add definitions for PCIe legacy INTx
interrupts
arch/arm/boot/dts/armada-370.dtsi | 28 ++++-
arch/arm/boot/dts/armada-375.dtsi | 28 ++++-
arch/arm/boot/dts/armada-380.dtsi | 42 ++++++-
arch/arm/boot/dts/armada-385.dtsi | 52 ++++++--
arch/arm/boot/dts/armada-39x.dtsi | 56 +++++++--
arch/arm/boot/dts/armada-xp-98dx3236.dtsi | 14 ++-
arch/arm/boot/dts/armada-xp-mv78230.dtsi | 70 +++++++++--
arch/arm/boot/dts/armada-xp-mv78260.dtsi | 126 ++++++++++++++++---
arch/arm/boot/dts/armada-xp-mv78460.dtsi | 140 ++++++++++++++++++----
arch/arm/boot/dts/dove.dtsi | 28 ++++-
arch/arm/boot/dts/kirkwood-6192.dtsi | 14 ++-
arch/arm/boot/dts/kirkwood-6281.dtsi | 14 ++-
arch/arm/boot/dts/kirkwood-6282.dtsi | 28 ++++-
arch/arm/boot/dts/kirkwood-98dx4122.dtsi | 14 ++-
14 files changed, 560 insertions(+), 94 deletions(-)
--
2.20.1
Signed-off-by: Pali Rohár <[email protected]>
---
arch/arm/boot/dts/dove.dtsi | 28 ++++++++++++++++++++++++----
1 file changed, 24 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
index 89e0bdaf3a85..96ba47c061a7 100644
--- a/arch/arm/boot/dts/dove.dtsi
+++ b/arch/arm/boot/dts/dove.dtsi
@@ -122,8 +122,18 @@
bus-range = <0x00 0xff>;
#interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &intc 16>;
+ interrupt-names = "intx";
+ interrupts = <16>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie0_intc 0>,
+ <0 0 0 2 &pcie0_intc 1>,
+ <0 0 0 3 &pcie0_intc 2>,
+ <0 0 0 4 &pcie0_intc 3>;
+
+ pcie0_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
};
pcie1: pcie@2 {
@@ -141,8 +151,18 @@
bus-range = <0x00 0xff>;
#interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &intc 18>;
+ interrupt-names = "intx";
+ interrupts = <18>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie1_intc 0>,
+ <0 0 0 2 &pcie1_intc 1>,
+ <0 0 0 3 &pcie1_intc 2>,
+ <0 0 0 4 &pcie1_intc 3>;
+
+ pcie1_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
};
};
--
2.20.1
Signed-off-by: Pali Rohár <[email protected]>
---
arch/arm/boot/dts/armada-xp-mv78460.dtsi | 140 +++++++++++++++++++----
1 file changed, 120 insertions(+), 20 deletions(-)
diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
index 230a3fd36b30..16185edf9aa5 100644
--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
@@ -119,16 +119,26 @@
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
+ interrupt-names = "intx";
+ interrupts-extended = <&mpic 58>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
bus-range = <0x00 0xff>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 58>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie1_intc 0>,
+ <0 0 0 2 &pcie1_intc 1>,
+ <0 0 0 3 &pcie1_intc 2>,
+ <0 0 0 4 &pcie1_intc 3>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 5>;
status = "disabled";
+
+ pcie1_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
};
pcie2: pcie@2,0 {
@@ -137,16 +147,26 @@
reg = <0x1000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
+ interrupt-names = "intx";
+ interrupts-extended = <&mpic 59>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0x81000000 0 0 0x81000000 0x2 0 1 0>;
bus-range = <0x00 0xff>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 59>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie2_intc 0>,
+ <0 0 0 2 &pcie2_intc 1>,
+ <0 0 0 3 &pcie2_intc 2>,
+ <0 0 0 4 &pcie2_intc 3>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <1>;
clocks = <&gateclk 6>;
status = "disabled";
+
+ pcie2_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
};
pcie3: pcie@3,0 {
@@ -155,16 +175,26 @@
reg = <0x1800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
+ interrupt-names = "intx";
+ interrupts-extended = <&mpic 60>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
0x81000000 0 0 0x81000000 0x3 0 1 0>;
bus-range = <0x00 0xff>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 60>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie3_intc 0>,
+ <0 0 0 2 &pcie3_intc 1>,
+ <0 0 0 3 &pcie3_intc 2>,
+ <0 0 0 4 &pcie3_intc 3>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <2>;
clocks = <&gateclk 7>;
status = "disabled";
+
+ pcie3_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
};
pcie4: pcie@4,0 {
@@ -173,16 +203,26 @@
reg = <0x2000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
+ interrupt-names = "intx";
+ interrupts-extended = <&mpic 61>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
0x81000000 0 0 0x81000000 0x4 0 1 0>;
bus-range = <0x00 0xff>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 61>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie4_intc 0>,
+ <0 0 0 2 &pcie4_intc 1>,
+ <0 0 0 3 &pcie4_intc 2>,
+ <0 0 0 4 &pcie4_intc 3>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <3>;
clocks = <&gateclk 8>;
status = "disabled";
+
+ pcie4_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
};
pcie5: pcie@5,0 {
@@ -191,16 +231,26 @@
reg = <0x2800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
+ interrupt-names = "intx";
+ interrupts-extended = <&mpic 62>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
0x81000000 0 0 0x81000000 0x5 0 1 0>;
bus-range = <0x00 0xff>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 62>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie5_intc 0>,
+ <0 0 0 2 &pcie5_intc 1>,
+ <0 0 0 3 &pcie5_intc 2>,
+ <0 0 0 4 &pcie5_intc 3>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 9>;
status = "disabled";
+
+ pcie5_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
};
pcie6: pcie@6,0 {
@@ -209,16 +259,26 @@
reg = <0x3000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
+ interrupt-names = "intx";
+ interrupts-extended = <&mpic 63>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
0x81000000 0 0 0x81000000 0x6 0 1 0>;
bus-range = <0x00 0xff>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 63>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie6_intc 0>,
+ <0 0 0 2 &pcie6_intc 1>,
+ <0 0 0 3 &pcie6_intc 2>,
+ <0 0 0 4 &pcie6_intc 3>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <1>;
clocks = <&gateclk 10>;
status = "disabled";
+
+ pcie6_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
};
pcie7: pcie@7,0 {
@@ -227,16 +287,26 @@
reg = <0x3800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
+ interrupt-names = "intx";
+ interrupts-extended = <&mpic 64>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
0x81000000 0 0 0x81000000 0x7 0 1 0>;
bus-range = <0x00 0xff>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 64>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie7_intc 0>,
+ <0 0 0 2 &pcie7_intc 1>,
+ <0 0 0 3 &pcie7_intc 2>,
+ <0 0 0 4 &pcie7_intc 3>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <2>;
clocks = <&gateclk 11>;
status = "disabled";
+
+ pcie7_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
};
pcie8: pcie@8,0 {
@@ -245,16 +315,26 @@
reg = <0x4000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
+ interrupt-names = "intx";
+ interrupts-extended = <&mpic 65>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
0x81000000 0 0 0x81000000 0x8 0 1 0>;
bus-range = <0x00 0xff>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 65>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie8_intc 0>,
+ <0 0 0 2 &pcie8_intc 1>,
+ <0 0 0 3 &pcie8_intc 2>,
+ <0 0 0 4 &pcie8_intc 3>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <3>;
clocks = <&gateclk 12>;
status = "disabled";
+
+ pcie8_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
};
pcie9: pcie@9,0 {
@@ -263,16 +343,26 @@
reg = <0x4800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
+ interrupt-names = "intx";
+ interrupts-extended = <&mpic 99>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
0x81000000 0 0 0x81000000 0x9 0 1 0>;
bus-range = <0x00 0xff>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 99>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie9_intc 0>,
+ <0 0 0 2 &pcie9_intc 1>,
+ <0 0 0 3 &pcie9_intc 2>,
+ <0 0 0 4 &pcie9_intc 3>;
marvell,pcie-port = <2>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 26>;
status = "disabled";
+
+ pcie9_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
};
pcie10: pcie@a,0 {
@@ -281,16 +371,26 @@
reg = <0x5000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
+ interrupt-names = "intx";
+ interrupts-extended = <&mpic 103>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
0x81000000 0 0 0x81000000 0xa 0 1 0>;
bus-range = <0x00 0xff>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 103>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie10_intc 0>,
+ <0 0 0 2 &pcie10_intc 1>,
+ <0 0 0 3 &pcie10_intc 2>,
+ <0 0 0 4 &pcie10_intc 3>;
marvell,pcie-port = <3>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 27>;
status = "disabled";
+
+ pcie10_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
};
};
--
2.20.1
Signed-off-by: Pali Rohár <[email protected]>
---
arch/arm/boot/dts/armada-xp-mv78260.dtsi | 126 +++++++++++++++++++----
1 file changed, 108 insertions(+), 18 deletions(-)
diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
index 2d85fe8ac327..0714af52e607 100644
--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
@@ -98,16 +98,26 @@
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
+ interrupt-names = "intx";
+ interrupts-extended = <&mpic 58>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
bus-range = <0x00 0xff>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 58>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie1_intc 0>,
+ <0 0 0 2 &pcie1_intc 1>,
+ <0 0 0 3 &pcie1_intc 2>,
+ <0 0 0 4 &pcie1_intc 3>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 5>;
status = "disabled";
+
+ pcie1_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
};
pcie2: pcie@2,0 {
@@ -116,16 +126,26 @@
reg = <0x1000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
+ interrupt-names = "intx";
+ interrupts-extended = <&mpic 59>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0x81000000 0 0 0x81000000 0x2 0 1 0>;
bus-range = <0x00 0xff>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 59>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie2_intc 0>,
+ <0 0 0 2 &pcie2_intc 1>,
+ <0 0 0 3 &pcie2_intc 2>,
+ <0 0 0 4 &pcie2_intc 3>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <1>;
clocks = <&gateclk 6>;
status = "disabled";
+
+ pcie2_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
};
pcie3: pcie@3,0 {
@@ -134,16 +154,26 @@
reg = <0x1800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
+ interrupt-names = "intx";
+ interrupts-extended = <&mpic 60>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
0x81000000 0 0 0x81000000 0x3 0 1 0>;
bus-range = <0x00 0xff>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 60>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie3_intc 0>,
+ <0 0 0 2 &pcie3_intc 1>,
+ <0 0 0 3 &pcie3_intc 2>,
+ <0 0 0 4 &pcie3_intc 3>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <2>;
clocks = <&gateclk 7>;
status = "disabled";
+
+ pcie3_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
};
pcie4: pcie@4,0 {
@@ -152,16 +182,26 @@
reg = <0x2000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
+ interrupt-names = "intx";
+ interrupts-extended = <&mpic 61>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
0x81000000 0 0 0x81000000 0x4 0 1 0>;
bus-range = <0x00 0xff>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 61>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie4_intc 0>,
+ <0 0 0 2 &pcie4_intc 1>,
+ <0 0 0 3 &pcie4_intc 2>,
+ <0 0 0 4 &pcie4_intc 3>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <3>;
clocks = <&gateclk 8>;
status = "disabled";
+
+ pcie4_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
};
pcie5: pcie@5,0 {
@@ -170,16 +210,26 @@
reg = <0x2800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
+ interrupt-names = "intx";
+ interrupts-extended = <&mpic 62>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
0x81000000 0 0 0x81000000 0x5 0 1 0>;
bus-range = <0x00 0xff>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 62>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie5_intc 0>,
+ <0 0 0 2 &pcie5_intc 1>,
+ <0 0 0 3 &pcie5_intc 2>,
+ <0 0 0 4 &pcie5_intc 3>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 9>;
status = "disabled";
+
+ pcie5_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
};
pcie6: pcie@6,0 {
@@ -188,16 +238,26 @@
reg = <0x3000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
+ interrupt-names = "intx";
+ interrupts-extended = <&mpic 63>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
0x81000000 0 0 0x81000000 0x6 0 1 0>;
bus-range = <0x00 0xff>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 63>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie6_intc 0>,
+ <0 0 0 2 &pcie6_intc 1>,
+ <0 0 0 3 &pcie6_intc 2>,
+ <0 0 0 4 &pcie6_intc 3>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <1>;
clocks = <&gateclk 10>;
status = "disabled";
+
+ pcie6_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
};
pcie7: pcie@7,0 {
@@ -206,16 +266,26 @@
reg = <0x3800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
+ interrupt-names = "intx";
+ interrupts-extended = <&mpic 64>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
0x81000000 0 0 0x81000000 0x7 0 1 0>;
bus-range = <0x00 0xff>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 64>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie7_intc 0>,
+ <0 0 0 2 &pcie7_intc 1>,
+ <0 0 0 3 &pcie7_intc 2>,
+ <0 0 0 4 &pcie7_intc 3>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <2>;
clocks = <&gateclk 11>;
status = "disabled";
+
+ pcie7_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
};
pcie8: pcie@8,0 {
@@ -224,16 +294,26 @@
reg = <0x4000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
+ interrupt-names = "intx";
+ interrupts-extended = <&mpic 65>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
0x81000000 0 0 0x81000000 0x8 0 1 0>;
bus-range = <0x00 0xff>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 65>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie8_intc 0>,
+ <0 0 0 2 &pcie8_intc 1>,
+ <0 0 0 3 &pcie8_intc 2>,
+ <0 0 0 4 &pcie8_intc 3>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <3>;
clocks = <&gateclk 12>;
status = "disabled";
+
+ pcie8_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
};
pcie9: pcie@9,0 {
@@ -242,16 +322,26 @@
reg = <0x4800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
+ interrupt-names = "intx";
+ interrupts-extended = <&mpic 99>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
0x81000000 0 0 0x81000000 0x9 0 1 0>;
bus-range = <0x00 0xff>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 99>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie9_intc 0>,
+ <0 0 0 2 &pcie9_intc 1>,
+ <0 0 0 3 &pcie9_intc 2>,
+ <0 0 0 4 &pcie9_intc 3>;
marvell,pcie-port = <2>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 26>;
status = "disabled";
+
+ pcie9_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
};
};
--
2.20.1
On Wed, Jul 06, 2022 at 08:31:03PM +0200, Pali Roh?r wrote:
> This patch series add definitions for PCIe legacy INTx interrupts into
> every DTS file used by the pci-mvebu.c controller driver.
What you fail to explain in the commit message is Why?
Andrew
On Wed, 6 Jul 2022 22:53:46 +0200
Andrew Lunn <[email protected]> wrote:
> On Wed, Jul 06, 2022 at 08:31:03PM +0200, Pali Rohár wrote:
> > This patch series add definitions for PCIe legacy INTx interrupts into
> > every DTS file used by the pci-mvebu.c controller driver.
>
> What you fail to explain in the commit message is Why?
>
> Andrew
Hi Andrew,
this is required for example in a scenario where a driver requests only
one of the legacy interrupts (INTA). Without this change, the driver
would be notified on events on all 4 (INTA, INTB, INTC, INTD), even if
it requested only one of them.
Marek
On Thu, Jul 07, 2022 at 04:38:18PM +0200, Marek Beh?n wrote:
> On Wed, 6 Jul 2022 22:53:46 +0200
> Andrew Lunn <[email protected]> wrote:
>
> > On Wed, Jul 06, 2022 at 08:31:03PM +0200, Pali Roh?r wrote:
> > > This patch series add definitions for PCIe legacy INTx interrupts into
> > > every DTS file used by the pci-mvebu.c controller driver.
> >
> > What you fail to explain in the commit message is Why?
> >
> > Andrew
>
> Hi Andrew,
>
> this is required for example in a scenario where a driver requests only
> one of the legacy interrupts (INTA). Without this change, the driver
> would be notified on events on all 4 (INTA, INTB, INTC, INTD), even if
> it requested only one of them.
O.K, so please add that to the commit message.
Is this purely theoretical, or are there known broken platforms out
there? Should a subset of these patches be added to stable?
Andrew