The following series of patches add support for the following
on J721S2 common processor board,
- USB
- SerDes
- OSPI
Aswath Govindraju (6):
arm64: dts: ti: k3-j721s2-main: Add support for USB
arm64: dts: ti: k3-j721s2-main: Add SERDES and WIZ device tree node
arm64: dts: ti: k3-j721s2-mcu-wakeup: Add support of OSPI
arm64: dts: ti: k3-j721s2-common-proc-board: Enable SERDES0
arm64: dts: ti: k3-j721s2-common-proc-board: Add USB support
arm64: dts: k3-j721s2: Add support for OSPI Flashes
.../dts/ti/k3-j721s2-common-proc-board.dts | 78 ++++++++++++
arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 112 ++++++++++++++++++
.../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 40 +++++++
arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 42 +++++++
4 files changed, 272 insertions(+)
--
2.36.1
From: Aswath Govindraju <[email protected]>
Add dt node for the single instance of WIZ (SERDES wrapper) and
SERDES module shared by PCIe, eDP and USB.
Acked-by: Matt Ranostay <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
---
arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 70 ++++++++++++++++++++++
1 file changed, 70 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
index f7e359da8690..f1e02d896168 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
@@ -5,6 +5,13 @@
* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
*/
+/ {
+ serdes_refclk: serdes-refclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ };
+};
+
&cbass_main {
msmc_ram: sram@70000000 {
compatible = "mmio-sram";
@@ -33,6 +40,13 @@ scm_conf: scm-conf@104000 {
#size-cells = <1>;
ranges = <0x00 0x00 0x00104000 0x18000>;
+ serdes_ln_ctrl: mux-controller@80 {
+ compatible = "mmio-mux";
+ #mux-control-cells = <1>;
+ mux-reg-masks = <0x80 0x3>, <0x84 0x3>, /* SERDES0 lane0/1 select */
+ <0x88 0x3>, <0x8c 0x3>; /* SERDES0 lane2/3 select */
+ };
+
usb_serdes_mux: mux-controller@0 {
compatible = "mmio-mux";
#mux-control-cells = <1>;
@@ -728,6 +742,62 @@ usb0: usb@6000000 {
};
};
+ serdes_wiz0: wiz@5060000 {
+ compatible = "ti,j721e-wiz-10g";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ power-domains = <&k3_pds 365 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 365 0>, <&k3_clks 365 3>, <&serdes_refclk>;
+ clock-names = "fck", "core_ref_clk", "ext_ref_clk";
+ num-lanes = <4>;
+ #reset-cells = <1>;
+ ranges = <0x5060000 0x0 0x5060000 0x10000>;
+
+ assigned-clocks = <&k3_clks 365 3>;
+ assigned-clock-parents = <&k3_clks 365 7>;
+
+ wiz0_pll0_refclk: pll0-refclk {
+ clocks = <&k3_clks 365 3>, <&serdes_refclk>;
+ clock-output-names = "wiz0_pll0_refclk";
+ #clock-cells = <0>;
+ assigned-clocks = <&wiz0_pll0_refclk>;
+ assigned-clock-parents = <&k3_clks 365 3>;
+ };
+
+ wiz0_pll1_refclk: pll1-refclk {
+ clocks = <&k3_clks 365 3>, <&serdes_refclk>;
+ clock-output-names = "wiz0_pll1_refclk";
+ #clock-cells = <0>;
+ assigned-clocks = <&wiz0_pll1_refclk>;
+ assigned-clock-parents = <&k3_clks 365 3>;
+ };
+
+ wiz0_refclk_dig: refclk-dig {
+ clocks = <&k3_clks 365 3>, <&serdes_refclk>;
+ clock-output-names = "wiz0_refclk_dig";
+ #clock-cells = <0>;
+ assigned-clocks = <&wiz0_refclk_dig>;
+ assigned-clock-parents = <&k3_clks 365 3>;
+ };
+
+ wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div {
+ clocks = <&wiz0_refclk_dig>;
+ #clock-cells = <0>;
+ };
+
+ serdes0: serdes@5060000 {
+ compatible = "ti,j721e-serdes-10g";
+ reg = <0x05060000 0x00010000>;
+ reg-names = "torrent_phy";
+ resets = <&serdes_wiz0 0>;
+ reset-names = "torrent_reset";
+ clocks = <&wiz0_pll0_refclk>;
+ clock-names = "refclk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
main_mcan0: can@2701000 {
compatible = "bosch,m_can";
reg = <0x00 0x02701000 0x00 0x200>,
--
2.36.1
From: Aswath Govindraju <[email protected]>
The board uses lane 1 of SERDES for USB. Set the mux
accordingly.
The USB controller and EVM supports super-speed for USB0
on the Type-C port. However, the SERDES has a limitation
that upto 2 protocols can be used at a time. The SERDES is
wired for PCIe, eDP and USB super-speed. It has been
chosen to use PCIe and eDP as default. So restrict
USB0 to high-speed mode.
Acked-by: Matt Ranostay <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
---
.../dts/ti/k3-j721s2-common-proc-board.dts | 22 +++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
index 791f235bd95f..aa75dc541842 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
@@ -147,6 +147,12 @@ vdd_sd_dv_pins_default: vdd-sd-dv-pins-default {
J721S2_IOPAD(0x020, PIN_INPUT, 7) /* (AA23) MCAN15_RX.GPIO0_8 */
>;
};
+
+ main_usbss0_pins_default: main-usbss0-pins-default {
+ pinctrl-single,pins = <
+ J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */
+ >;
+ };
};
&wkup_pmx0 {
@@ -372,6 +378,22 @@ serdes0_pcie_link: phy@0 {
};
};
+&usb_serdes_mux {
+ idle-states = <1>; /* USB0 to SERDES lane 1 */
+};
+
+&usbss0 {
+ pinctrl-0 = <&main_usbss0_pins_default>;
+ pinctrl-names = "default";
+ ti,vbus-divider;
+ ti,usb2-only;
+};
+
+&usb0 {
+ dr_mode = "otg";
+ maximum-speed = "high-speed";
+};
+
&mcu_mcan0 {
pinctrl-names = "default";
pinctrl-0 = <&mcu_mcan0_pins_default>;
--
2.36.1
From: Aswath Govindraju <[email protected]>
Add support for single instance of USB 3.0 controller in J721S2 SoC.
Acked-by: Matt Ranostay <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
---
arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 42 ++++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
index 34e7d577ae13..f7e359da8690 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
@@ -26,6 +26,20 @@ l3cache-sram@200000 {
};
};
+ scm_conf: scm-conf@104000 {
+ compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
+ reg = <0x00 0x00104000 0x00 0x18000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00 0x00 0x00104000 0x18000>;
+
+ usb_serdes_mux: mux-controller@0 {
+ compatible = "mmio-mux";
+ #mux-control-cells = <1>;
+ mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
+ };
+ };
+
gic500: interrupt-controller@1800000 {
compatible = "arm,gic-v3";
#address-cells = <2>;
@@ -686,6 +700,34 @@ cpts@310d0000 {
};
};
+ usbss0: cdns-usb@4104000 {
+ compatible = "ti,j721e-usb";
+ reg = <0x00 0x04104000 0x00 0x100>;
+ clocks = <&k3_clks 360 16>, <&k3_clks 360 15>;
+ clock-names = "ref", "lpm";
+ assigned-clocks = <&k3_clks 360 16>; /* USB2_REFCLK */
+ assigned-clock-parents = <&k3_clks 360 17>;
+ power-domains = <&k3_pds 360 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ dma-coherent;
+
+ usb0: usb@6000000 {
+ compatible = "cdns,usb3";
+ reg = <0x00 0x06000000 0x00 0x10000>,
+ <0x00 0x06010000 0x00 0x10000>,
+ <0x00 0x06020000 0x00 0x10000>;
+ reg-names = "otg", "xhci", "dev";
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "host", "peripheral", "otg";
+ maximum-speed = "super-speed";
+ dr_mode = "otg";
+ };
+ };
+
main_mcan0: can@2701000 {
compatible = "bosch,m_can";
reg = <0x00 0x02701000 0x00 0x200>,
--
2.36.1
From: Aswath Govindraju <[email protected]>
J721S2 has an OSPI NOR flash on its SOM connected the OSPI0 instance and a
QSPI NOR flash on the common processor board connected to the OSPI1
instance. Add support for the same
Acked-by: Matt Ranostay <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
---
.../dts/ti/k3-j721s2-common-proc-board.dts | 34 +++++++++++++++
arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 42 +++++++++++++++++++
2 files changed, 76 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
index aa75dc541842..cb99a97af426 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
@@ -206,6 +206,20 @@ mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-pins-default {
J721S2_WKUP_IOPAD(0x0c8, PIN_INPUT, 7) /* (C28) WKUP_GPIO0_2 */
>;
};
+
+ mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default {
+ pinctrl-single,pins = <
+ J721S2_WKUP_IOPAD(0x040, PIN_OUTPUT, 0) /* (A19) MCU_OSPI1_CLK */
+ J721S2_WKUP_IOPAD(0x05c, PIN_OUTPUT, 0) /* (D20) MCU_OSPI1_CSn0 */
+ J721S2_WKUP_IOPAD(0x060, PIN_OUTPUT, 0) /* (C21) MCU_OSPI1_CSn1 */
+ J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (D21) MCU_OSPI1_D0 */
+ J721S2_WKUP_IOPAD(0x050, PIN_INPUT, 0) /* (G20) MCU_OSPI1_D1 */
+ J721S2_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (C20) MCU_OSPI1_D2 */
+ J721S2_WKUP_IOPAD(0x058, PIN_INPUT, 0) /* (A20) MCU_OSPI1_D3 */
+ J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (B19) MCU_OSPI1_DQS */
+ J721S2_WKUP_IOPAD(0x044, PIN_INPUT, 0) /* (B20) MCU_OSPI1_LBCLKO */
+ >;
+ };
};
&main_gpio2 {
@@ -394,6 +408,26 @@ &usb0 {
maximum-speed = "high-speed";
};
+&ospi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_fss0_ospi1_pins_default>;
+
+ flash@0{
+ compatible = "jedec,spi-nor";
+ reg = <0x0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <40000000>;
+ cdns,tshsl-ns = <60>;
+ cdns,tsd2d-ns = <60>;
+ cdns,tchsh-ns = <60>;
+ cdns,tslch-ns = <60>;
+ cdns,read-delay = <2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+};
+
&mcu_mcan0 {
pinctrl-names = "default";
pinctrl-0 = <&mcu_mcan0_pins_default>;
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi
index 76f0ceacb6d4..a05c17dd69b6 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi
@@ -39,6 +39,28 @@ transceiver0: can-phy0 {
};
};
+&wkup_pmx0 {
+ mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
+ pinctrl-single,pins = <
+ J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (D19) MCU_OSPI0_CLK */
+ J721S2_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F15) MCU_OSPI0_CSn0 */
+ J721S2_WKUP_IOPAD(0x030, PIN_OUTPUT, 0) /* (G17) MCU_OSPI0_CSn1 */
+ J721S2_WKUP_IOPAD(0x038, PIN_OUTPUT, 0) /* (F14) MCU_OSPI0_CSn2 */
+ J721S2_WKUP_IOPAD(0x03c, PIN_OUTPUT, 0) /* (F17) MCU_OSPI0_CSn3 */
+ J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (C19) MCU_OSPI0_D0 */
+ J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F16) MCU_OSPI0_D1 */
+ J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (G15) MCU_OSPI0_D2 */
+ J721S2_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (F18) MCU_OSPI0_D3 */
+ J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (E19) MCU_OSPI0_D4 */
+ J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D5 */
+ J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (F19) MCU_OSPI0_D6 */
+ J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D7 */
+ J721S2_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (E18) MCU_OSPI0_DQS */
+ J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E20) MCU_OSPI0_LBCLKO */
+ >;
+ };
+};
+
&main_pmx0 {
main_i2c0_pins_default: main-i2c0-pins-default {
pinctrl-single,pins = <
@@ -78,6 +100,26 @@ &main_mcan16 {
phys = <&transceiver0>;
};
+&ospi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0x0>;
+ spi-tx-bus-width = <8>;
+ spi-rx-bus-width = <8>;
+ spi-max-frequency = <25000000>;
+ cdns,tshsl-ns = <60>;
+ cdns,tsd2d-ns = <60>;
+ cdns,tchsh-ns = <60>;
+ cdns,tslch-ns = <60>;
+ cdns,read-delay = <4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+};
+
&mailbox0_cluster0 {
status = "disabled";
};
--
2.36.1
From: Aswath Govindraju <[email protected]>
Add support for two instance of OSPI in J721S2 SoC.
Acked-by: Matt Ranostay <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
---
.../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 40 +++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
index 4d1bfabd1313..7bc268f27030 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
@@ -299,4 +299,44 @@ cpts@3d000 {
ti,cpts-periodic-outputs = <2>;
};
};
+
+ fss: syscon@47000000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0x0 0x47000000 0x0 0x100>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ ospi0: spi@47040000 {
+ compatible = "ti,am654-ospi", "cdns,qspi-nor";
+ reg = <0x00 0x47040000 0x00 0x100>,
+ <0x5 0x0000000 0x1 0x0000000>;
+ interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
+ cdns,fifo-depth = <256>;
+ cdns,fifo-width = <4>;
+ cdns,trigger-address = <0x0>;
+ clocks = <&k3_clks 109 5>;
+ assigned-clocks = <&k3_clks 109 5>;
+ assigned-clock-parents = <&k3_clks 109 7>;
+ assigned-clock-rates = <166666666>;
+ power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ ospi1: spi@47050000 {
+ compatible = "ti,am654-ospi", "cdns,qspi-nor";
+ reg = <0x00 0x47050000 0x00 0x100>,
+ <0x7 0x0000000 0x1 0x0000000>;
+ interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>;
+ cdns,fifo-depth = <256>;
+ cdns,fifo-width = <4>;
+ cdns,trigger-address = <0x0>;
+ clocks = <&k3_clks 110 5>;
+ power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ };
};
--
2.36.1
From: Aswath Govindraju <[email protected]>
Configure first lane to PCIe, the second lane to USB and the last two lanes
to eDP. Also, add sub-nodes to SERDES0 DT node to represent SERDES0 is
connected to PCIe.
Acked-by: Matt Ranostay <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
---
.../dts/ti/k3-j721s2-common-proc-board.dts | 22 +++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
index b210cc07c539..791f235bd95f 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
@@ -9,6 +9,9 @@
#include "k3-j721s2-som-p0.dtsi"
#include <dt-bindings/net/ti-dp83867.h>
+#include <dt-bindings/phy/phy-cadence.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/mux/ti-serdes.h>
/ {
compatible = "ti,j721s2-evm", "ti,j721s2";
@@ -350,6 +353,25 @@ &cpsw_port1 {
phy-handle = <&phy0>;
};
+&serdes_ln_ctrl {
+ idle-states = <J721S2_SERDES0_LANE0_PCIE1_LANE0>, <J721S2_SERDES0_LANE1_USB>,
+ <J721S2_SERDES0_LANE2_EDP_LANE2>, <J721S2_SERDES0_LANE3_EDP_LANE3>;
+};
+
+&serdes_refclk {
+ clock-frequency = <100000000>;
+};
+
+&serdes0 {
+ serdes0_pcie_link: phy@0 {
+ reg = <0>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_PCIE>;
+ resets = <&serdes_wiz0 1>;
+ };
+};
+
&mcu_mcan0 {
pinctrl-names = "default";
pinctrl-0 = <&mcu_mcan0_pins_default>;
--
2.36.1