Tegra234 has a total of 11 PCIe controllers based on Synopsys DesignWare core.
There are three Universal PHY (UPHY) blocks (viz. HSIO, NVHS and GBE) with
each block supporting 8 lanes respectively. Controllers:0~4 use UPHY lanes
from HSIO block, Controllers:5,6 use UPHY lanes from NVHS block and
Controllers:7~10 use UPHY lanes from GBE block. Lane mapping in each block
is controlled in XBAR module by BPMP-FW. Since PCIe core has PIPE interface,
a glue module called PIPE-to-UPHY (P2U) is used to connect each UPHY lane
(applicable to all three UPHY bricks i.e. HSIO/NVHS/GBE) to PCIe controller.
All the controllers can operate in the RootPort mode where as only controllers
C5, C6, C7 and C10 can operate in the EndPoint mode.
This patch series
- Adds support for Tegra234 in the existing P2U PHY driver
- Adds support for Tegra234 in the existing PCIe platform controller driver
- Adds device tree nodes for all PCIe controllers
- Enables nodes applicable to P3737-0000 platform
Testing done on P3737-0000 platform
- PCIe link is up with on-board Broadcom WiFi controller
- PCIe link is up with an NVMe drive connected to M.2 Key-M slot and its
functionality is verified
- PCIe link is up with a variety of cards (NICs and USB3.0 add-on cards)
connected to CEM slot and their functionality is verified
- PCIe link is up with C5 controller configured for the endpoint mode with
a host
V4:
* Addressed review comments from Krzysztof and Rob
* Changes are only in schema files and regulator patch
* Dropped PHY related patches as they are already accepted
V3:
* Add DT nodes for the controllers that can work in the EndPoint mode
* Converted the existing device-tree binding documentation from .txt to .yaml
* Add T234 specific information to the RP and EP .yaml documentation files
* Added regulators required to power up required power rails
V2:
* Dropped 3 patches that add clocks & resets IDs, power-domain IDs and
memory IDs for PCIe controllers as the patches are already available
in linux-next
* Based on Bjorn's review comment, reverted the commit b57256918399 ("PCI:
tegra194: Rename tegra_pcie_dw to tegra194_pcie") and pushed it as a
separate patch before adding support for T234 in the existing driver
* Addressed review comments from Rob for the other changes
Vidya Sagar (9):
dt-bindings: pci: tegra: Convert to json-schema
dt-bindings: PCI: tegra234: Add schema for tegra234 rootport mode
dt-bindings: PCI: tegra234: Add schema for tegra234 endpoint mode
arm64: tegra: Add regulators required for PCIe
arm64: tegra: Add P2U and PCIe controller nodes to Tegra234 DT
arm64: tegra: Enable PCIe slots in P3737-0000 board
PCI: Disable MSI for Tegra234 root ports
Revert "PCI: tegra194: Rename tegra_pcie_dw to tegra194_pcie"
PCI: tegra: Add Tegra234 PCIe support
.../bindings/pci/nvidia,tegra194-pcie-ep.yaml | 339 +++++++
.../bindings/pci/nvidia,tegra194-pcie.txt | 245 -----
.../bindings/pci/nvidia,tegra194-pcie.yaml | 381 +++++++
.../devicetree/bindings/pci/snps,dw-pcie.yaml | 2 +-
.../boot/dts/nvidia/tegra234-p3701-0000.dtsi | 36 +
.../nvidia/tegra234-p3737-0000+p3701-0000.dts | 51 +
arch/arm64/boot/dts/nvidia/tegra234.dtsi | 927 ++++++++++++++++++
drivers/pci/controller/dwc/pcie-tegra194.c | 622 ++++++++----
drivers/pci/quirks.c | 13 +-
9 files changed, 2170 insertions(+), 446 deletions(-)
create mode 100644 Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml
delete mode 100644 Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt
create mode 100644 Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml
--
2.17.1
Tegra234 PCIe rootports don't generate MSI interrupts for PME and AER
events. Since PCIe spec (Ref: r4.0 sec 6.1.4.3) doesn't support using
a mix of INTx and MSI/MSI-X, MSI needs to be disabled to avoid root
ports service drivers registering their respective ISRs with MSI interrupt
and to let only INTx be used for all events.
Signed-off-by: Vidya Sagar <[email protected]>
---
V4:
* None
V3:
* None
V2:
* Addressed review comments from Bjorn i.e. changed the PCIe spec reference
to a more relevant section and modified commit message accordingly
drivers/pci/quirks.c | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 2e68f50bc7ae..5b532449ac4f 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -2709,8 +2709,8 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
nvenet_msi_disable);
/*
- * PCIe spec r4.0 sec 7.7.1.2 and sec 7.7.2.2 say that if MSI/MSI-X is enabled,
- * then the device can't use INTx interrupts. Tegra's PCIe root ports don't
+ * PCIe spec r4.0 sec 6.1.4.3 says that if MSI/MSI-X is enabled,then the
+ * device can't use INTx interrupts. Tegra's PCIe root ports don't
* generate MSI interrupts for PME and AER events instead only INTx interrupts
* are generated. Though Tegra's PCIe root ports can generate MSI interrupts
* for other events, since PCIe specification doesn't support using a mix of
@@ -2760,6 +2760,15 @@ DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e5,
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e6,
PCI_CLASS_BRIDGE_PCI, 8,
pci_quirk_nvidia_tegra_disable_rp_msi);
+DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229a,
+ PCI_CLASS_BRIDGE_PCI, 8,
+ pci_quirk_nvidia_tegra_disable_rp_msi);
+DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229c,
+ PCI_CLASS_BRIDGE_PCI, 8,
+ pci_quirk_nvidia_tegra_disable_rp_msi);
+DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229e,
+ PCI_CLASS_BRIDGE_PCI, 8,
+ pci_quirk_nvidia_tegra_disable_rp_msi);
/*
* Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing
--
2.17.1
Convert the Tegra194 PCIe bindings from the free-form text format to
json-schema.
Signed-off-by: Vidya Sagar <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
---
V4:
* Addressed review comments from Krzysztof and Rob
V3:
* New patch in this series. Added as part of addressing Rob's review
comment to convert the existing .txt file to .yaml schema
.../bindings/pci/nvidia,tegra194-pcie-ep.yaml | 228 ++++++++++++++++
.../bindings/pci/nvidia,tegra194-pcie.txt | 245 -----------------
.../bindings/pci/nvidia,tegra194-pcie.yaml | 257 ++++++++++++++++++
.../devicetree/bindings/pci/snps,dw-pcie.yaml | 2 +-
4 files changed, 486 insertions(+), 246 deletions(-)
create mode 100644 Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml
delete mode 100644 Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt
create mode 100644 Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml
diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml
new file mode 100644
index 000000000000..98e2d40e876b
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml
@@ -0,0 +1,228 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie-ep.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra194 (and later) PCIe endpoint controller (Synopsys DesignWare Core based)
+
+maintainers:
+ - Thierry Reding <[email protected]>
+ - Jon Hunter <[email protected]>
+ - Vidya Sagar <[email protected]>
+
+description: |
+ This PCIe controller is based on the Synopsis Designware PCIe IP and thus
+ inherits all the common properties defined in snps,dw-pcie-ep.yaml.
+ Some of the controller instances are dual mode where in they can work either
+ in root port mode or endpoint mode but one at a time.
+
+ On Tegra194, controllers C0, C4 and C5 support endpoint mode.
+
+ Note: On Tegra194's P2972-0000 platform, only C5 controller can be enabled to
+ operate in the endpoint mode because of the way the platform is designed.
+
+properties:
+ compatible:
+ enum:
+ - nvidia,tegra194-pcie-ep
+
+ reg:
+ items:
+ - description: controller's application logic registers
+ - description: iATU and DMA registers. This is where the iATU (internal
+ Address Translation Unit) registers of the PCIe core are made
+ available for software access.
+ - description: The aperture where the root port's own configuration
+ registers are available.
+ - description: Aperture used to map the remote root-complex' address space.
+
+ reg-names:
+ items:
+ - const: appl
+ - const: atu_dma
+ - const: dbi
+ - const: addr_space
+
+ interrupts:
+ items:
+ - description: controller interrupt
+
+ interrupt-names:
+ items:
+ - const: intr
+
+ clocks:
+ items:
+ - description: module clock
+
+ clock-names:
+ items:
+ - const: core
+
+ resets:
+ items:
+ - description: APB bus interface reset
+ - description: module reset
+
+ reset-names:
+ items:
+ - const: apb
+ - const: core
+
+ reset-gpios:
+ description: Must contain a phandle to a GPIO controller followed by GPIO
+ that is being used as PERST input signal. Please refer to pci.txt document.
+
+ phys:
+ minItems: 1
+ maxItems: 8
+
+ phy-names:
+ minItems: 1
+ items:
+ - const: p2u-0
+ - const: p2u-1
+ - const: p2u-2
+ - const: p2u-3
+ - const: p2u-4
+ - const: p2u-5
+ - const: p2u-6
+ - const: p2u-7
+
+ power-domains:
+ maxItems: 1
+ description: |
+ A phandle to the node that controls power to the respective PCIe
+ controller and a specifier name for the PCIe controller.
+
+ specifiers are defined in "include/dt-bindings/power/tegra194-powergate.h" file.
+
+ interconnects:
+ items:
+ - description: memory read client
+ - description: memory write client
+
+ interconnect-names:
+ items:
+ - const: dma-mem # read
+ - const: write
+
+ dma-coherent: true
+
+ nvidia,bpmp:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ Must contain a pair of phandle to BPMP controller node followed by
+ controller ID. Following are the controller IDs for each controller:
+
+ 0: C0
+ 1: C1
+ 2: C2
+ 3: C3
+ 4: C4
+ 5: C5
+ items:
+ - items:
+ - description: phandle to BPMP controller node
+ - description: PCIe controller ID
+ maximum: 5
+
+ nvidia,aspm-cmrt-us:
+ description: Common Mode Restore Time for proper operation of ASPM to be
+ specified in microseconds
+
+ nvidia,aspm-pwr-on-t-us:
+ description: Power On time for proper operation of ASPM to be specified in
+ microseconds
+
+ nvidia,aspm-l0s-entrance-latency-us:
+ description: ASPM L0s entrance latency to be specified in microseconds
+
+ vddio-pex-ctl-supply:
+ description: A phandle to the regulator supply for PCIe side band signals.
+
+ nvidia,refclk-select-gpios:
+ maxItems: 1
+ description: GPIO used to enable REFCLK to controller from the host
+
+allOf:
+ - $ref: /schemas/pci/pci-ep.yaml#
+
+unevaluatedProperties: false
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - interrupts
+ - interrupt-names
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+ - power-domains
+ - reset-gpios
+ - vddio-pex-ctl-supply
+ - num-lanes
+ - phys
+ - phy-names
+ - nvidia,bpmp
+
+examples:
+ - |
+ #include <dt-bindings/clock/tegra194-clock.h>
+ #include <dt-bindings/gpio/tegra194-gpio.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/tegra194-powergate.h>
+ #include <dt-bindings/reset/tegra194-reset.h>
+
+ bus@0 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0x8 0x0>;
+
+ pcie-ep@141a0000 {
+ compatible = "nvidia,tegra194-pcie-ep";
+ reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
+ <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
+ <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */
+ <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
+ reg-names = "appl", "atu_dma", "dbi", "addr_space";
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
+ interrupt-names = "intr";
+
+ clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>;
+ clock-names = "core";
+
+ resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
+ <&bpmp TEGRA194_RESET_PEX1_CORE_5>;
+ reset-names = "apb", "core";
+
+ power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&clkreq_c5_bi_dir_state>;
+
+ nvidia,bpmp = <&bpmp 5>;
+
+ nvidia,aspm-cmrt-us = <60>;
+ nvidia,aspm-pwr-on-t-us = <20>;
+ nvidia,aspm-l0s-entrance-latency-us = <3>;
+
+ vddio-pex-ctl-supply = <&vdd_1v8ao>;
+
+ reset-gpios = <&gpio TEGRA194_MAIN_GPIO(GG, 1) GPIO_ACTIVE_LOW>;
+
+ nvidia,refclk-select-gpios = <&gpio_aon TEGRA194_AON_GPIO(AA, 5)
+ GPIO_ACTIVE_HIGH>;
+
+ num-lanes = <8>;
+
+ phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
+ <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,
+ <&p2u_nvhs_6>, <&p2u_nvhs_7>;
+
+ phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
+ "p2u-5", "p2u-6", "p2u-7";
+ };
+ };
diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt
deleted file mode 100644
index 8e4f9bfb316d..000000000000
--- a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt
+++ /dev/null
@@ -1,245 +0,0 @@
-NVIDIA Tegra PCIe controller (Synopsys DesignWare Core based)
-
-This PCIe controller is based on the Synopsis Designware PCIe IP
-and thus inherits all the common properties defined in snps,dw-pcie.yaml and
-snps,dw-pcie-ep.yaml.
-Some of the controller instances are dual mode where in they can work either
-in root port mode or endpoint mode but one at a time.
-
-Required properties:
-- power-domains: A phandle to the node that controls power to the respective
- PCIe controller and a specifier name for the PCIe controller. Following are
- the specifiers for the different PCIe controllers
- TEGRA194_POWER_DOMAIN_PCIEX8B: C0
- TEGRA194_POWER_DOMAIN_PCIEX1A: C1
- TEGRA194_POWER_DOMAIN_PCIEX1A: C2
- TEGRA194_POWER_DOMAIN_PCIEX1A: C3
- TEGRA194_POWER_DOMAIN_PCIEX4A: C4
- TEGRA194_POWER_DOMAIN_PCIEX8A: C5
- these specifiers are defined in
- "include/dt-bindings/power/tegra194-powergate.h" file.
-- reg: A list of physical base address and length pairs for each set of
- controller registers. Must contain an entry for each entry in the reg-names
- property.
-- reg-names: Must include the following entries:
- "appl": Controller's application logic registers
- "config": As per the definition in snps,dw-pcie.yaml
- "atu_dma": iATU and DMA registers. This is where the iATU (internal Address
- Translation Unit) registers of the PCIe core are made available
- for SW access.
- "dbi": The aperture where root port's own configuration registers are
- available
-- interrupts: A list of interrupt outputs of the controller. Must contain an
- entry for each entry in the interrupt-names property.
-- interrupt-names: Must include the following entries:
- "intr": The Tegra interrupt that is asserted for controller interrupts
-- clocks: Must contain an entry for each entry in clock-names.
- See ../clocks/clock-bindings.txt for details.
-- clock-names: Must include the following entries:
- - core
-- resets: Must contain an entry for each entry in reset-names.
- See ../reset/reset.txt for details.
-- reset-names: Must include the following entries:
- - apb
- - core
-- phys: Must contain a phandle to P2U PHY for each entry in phy-names.
-- phy-names: Must include an entry for each active lane.
- "p2u-N": where N ranges from 0 to one less than the total number of lanes
-- nvidia,bpmp: Must contain a pair of phandle to BPMP controller node followed
- by controller-id. Following are the controller ids for each controller.
- 0: C0
- 1: C1
- 2: C2
- 3: C3
- 4: C4
- 5: C5
-- vddio-pex-ctl-supply: Regulator supply for PCIe side band signals
-
-RC mode:
-- compatible: Tegra19x must contain "nvidia,tegra194-pcie"
-- device_type: Must be "pci" for RC mode
-- interrupt-names: Must include the following entries:
- "msi": The Tegra interrupt that is asserted when an MSI is received
-- bus-range: Range of bus numbers associated with this controller
-- #address-cells: Address representation for root ports (must be 3)
- - cell 0 specifies the bus and device numbers of the root port:
- [23:16]: bus number
- [15:11]: device number
- - cell 1 denotes the upper 32 address bits and should be 0
- - cell 2 contains the lower 32 address bits and is used to translate to the
- CPU address space
-- #size-cells: Size representation for root ports (must be 2)
-- ranges: Describes the translation of addresses for root ports and standard
- PCI regions. The entries must be 7 cells each, where the first three cells
- correspond to the address as described for the #address-cells property
- above, the fourth and fifth cells are for the physical CPU address to
- translate to and the sixth and seventh cells are as described for the
- #size-cells property above.
- - Entries setup the mapping for the standard I/O, memory and
- prefetchable PCI regions. The first cell determines the type of region
- that is setup:
- - 0x81000000: I/O memory region
- - 0x82000000: non-prefetchable memory region
- - 0xc2000000: prefetchable memory region
- Please refer to the standard PCI bus binding document for a more detailed
- explanation.
-- #interrupt-cells: Size representation for interrupts (must be 1)
-- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
- Please refer to the standard PCI bus binding document for a more detailed
- explanation.
-
-EP mode:
-In Tegra194, Only controllers C0, C4 & C5 support EP mode.
-- compatible: Tegra19x must contain "nvidia,tegra194-pcie-ep"
-- reg-names: Must include the following entries:
- "addr_space": Used to map remote RC address space
-- reset-gpios: Must contain a phandle to a GPIO controller followed by
- GPIO that is being used as PERST input signal. Please refer to pci.txt
- document.
-
-Optional properties:
-- pinctrl-names: A list of pinctrl state names.
- It is mandatory for C5 controller and optional for other controllers.
- - "default": Configures PCIe I/O for proper operation.
-- pinctrl-0: phandle for the 'default' state of pin configuration.
- It is mandatory for C5 controller and optional for other controllers.
-- supports-clkreq: Refer to Documentation/devicetree/bindings/pci/pci.txt
-- nvidia,update-fc-fixup: This is a boolean property and needs to be present to
- improve performance when a platform is designed in such a way that it
- satisfies at least one of the following conditions thereby enabling root
- port to exchange optimum number of FC (Flow Control) credits with
- downstream devices
- 1. If C0/C4/C5 run at x1/x2 link widths (irrespective of speed and MPS)
- 2. If C0/C1/C2/C3/C4/C5 operate at their respective max link widths and
- a) speed is Gen-2 and MPS is 256B
- b) speed is >= Gen-3 with any MPS
-- nvidia,aspm-cmrt-us: Common Mode Restore Time for proper operation of ASPM
- to be specified in microseconds
-- nvidia,aspm-pwr-on-t-us: Power On time for proper operation of ASPM to be
- specified in microseconds
-- nvidia,aspm-l0s-entrance-latency-us: ASPM L0s entrance latency to be
- specified in microseconds
-
-RC mode:
-- vpcie3v3-supply: A phandle to the regulator node that supplies 3.3V to the slot
- if the platform has one such slot. (Ex:- x16 slot owned by C5 controller
- in p2972-0000 platform).
-- vpcie12v-supply: A phandle to the regulator node that supplies 12V to the slot
- if the platform has one such slot. (Ex:- x16 slot owned by C5 controller
- in p2972-0000 platform).
-
-EP mode:
-- nvidia,refclk-select-gpios: Must contain a phandle to a GPIO controller
- followed by GPIO that is being used to enable REFCLK to controller from host
-
-NOTE:- On Tegra194's P2972-0000 platform, only C5 controller can be enabled to
-operate in the endpoint mode because of the way the platform is designed.
-
-Examples:
-=========
-
-Tegra194 RC mode:
------------------
-
- pcie@14180000 {
- compatible = "nvidia,tegra194-pcie";
- power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
- reg = <0x00 0x14180000 0x0 0x00020000 /* appl registers (128K) */
- 0x00 0x38000000 0x0 0x00040000 /* configuration space (256K) */
- 0x00 0x38040000 0x0 0x00040000>; /* iATU_DMA reg space (256K) */
- reg-names = "appl", "config", "atu_dma";
-
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
- num-lanes = <8>;
- linux,pci-domain = <0>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>;
-
- clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
- clock-names = "core";
-
- resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
- <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
- reset-names = "apb", "core";
-
- interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
- <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
- interrupt-names = "intr", "msi";
-
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
-
- nvidia,bpmp = <&bpmp 0>;
-
- supports-clkreq;
- nvidia,aspm-cmrt-us = <60>;
- nvidia,aspm-pwr-on-t-us = <20>;
- nvidia,aspm-l0s-entrance-latency-us = <3>;
-
- bus-range = <0x0 0xff>;
- ranges = <0x81000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000 /* downstream I/O (1MB) */
- 0x82000000 0x0 0x38200000 0x0 0x38200000 0x0 0x01E00000 /* non-prefetchable memory (30MB) */
- 0xc2000000 0x18 0x00000000 0x18 0x00000000 0x4 0x00000000>; /* prefetchable memory (16GB) */
-
- vddio-pex-ctl-supply = <&vdd_1v8ao>;
- vpcie3v3-supply = <&vdd_3v3_pcie>;
- vpcie12v-supply = <&vdd_12v_pcie>;
-
- phys = <&p2u_hsio_2>, <&p2u_hsio_3>, <&p2u_hsio_4>,
- <&p2u_hsio_5>;
- phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
- };
-
-Tegra194 EP mode:
------------------
-
- pcie-ep@141a0000 {
- compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";
- power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
- reg = <0x00 0x141a0000 0x0 0x00020000 /* appl registers (128K) */
- 0x00 0x3a040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
- 0x00 0x3a080000 0x0 0x00040000 /* DBI reg space (256K) */
- 0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
- reg-names = "appl", "atu_dma", "dbi", "addr_space";
-
- num-lanes = <8>;
- num-ib-windows = <2>;
- num-ob-windows = <8>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&clkreq_c5_bi_dir_state>;
-
- clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>;
- clock-names = "core";
-
- resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
- <&bpmp TEGRA194_RESET_PEX1_CORE_5>;
- reset-names = "apb", "core";
-
- interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
- interrupt-names = "intr";
-
- nvidia,bpmp = <&bpmp 5>;
-
- nvidia,aspm-cmrt-us = <60>;
- nvidia,aspm-pwr-on-t-us = <20>;
- nvidia,aspm-l0s-entrance-latency-us = <3>;
-
- vddio-pex-ctl-supply = <&vdd_1v8ao>;
-
- reset-gpios = <&gpio TEGRA194_MAIN_GPIO(GG, 1) GPIO_ACTIVE_LOW>;
-
- nvidia,refclk-select-gpios = <&gpio_aon TEGRA194_AON_GPIO(AA, 5)
- GPIO_ACTIVE_HIGH>;
-
- phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
- <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,
- <&p2u_nvhs_6>, <&p2u_nvhs_7>;
-
- phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
- "p2u-5", "p2u-6", "p2u-7";
- };
diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml
new file mode 100644
index 000000000000..5d7cb56c86a2
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml
@@ -0,0 +1,257 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra194 (and later) PCIe controller (Synopsys DesignWare Core based)
+
+maintainers:
+ - Thierry Reding <[email protected]>
+ - Jon Hunter <[email protected]>
+ - Vidya Sagar <[email protected]>
+
+description: |
+ This PCIe controller is based on the Synopsis Designware PCIe IP and thus
+ inherits all the common properties defined in snps,dw-pcie.yaml. Some of the
+ controller instances are dual mode where in they can work either in root port
+ mode or endpoint mode but one at a time.
+
+ see nvidia,tegra194-pcie-ep.yaml for details on the endpoint mode device tree
+ bindings.
+
+properties:
+ compatible:
+ enum:
+ - nvidia,tegra194-pcie
+
+ reg:
+ items:
+ - description: controller's application logic registers
+ - description: configuration registers
+ - description: iATU and DMA registers. This is where the iATU (internal
+ Address Translation Unit) registers of the PCIe core are made
+ available for software access.
+ - description: The aperture where the root port's own configuration
+ registers are available.
+
+ reg-names:
+ items:
+ - const: appl
+ - const: config
+ - const: atu_dma
+ - const: dbi
+
+ interrupts:
+ items:
+ - description: controller interrupt
+ - description: MSI interrupt
+
+ interrupt-names:
+ items:
+ - const: intr
+ - const: msi
+
+ clocks:
+ items:
+ - description: module clock
+
+ clock-names:
+ items:
+ - const: core
+
+ resets:
+ items:
+ - description: APB bus interface reset
+ - description: module reset
+
+ reset-names:
+ items:
+ - const: apb
+ - const: core
+
+ phys:
+ minItems: 1
+ maxItems: 8
+
+ phy-names:
+ minItems: 1
+ items:
+ - const: p2u-0
+ - const: p2u-1
+ - const: p2u-2
+ - const: p2u-3
+ - const: p2u-4
+ - const: p2u-5
+ - const: p2u-6
+ - const: p2u-7
+
+ power-domains:
+ maxItems: 1
+ description: |
+ A phandle to the node that controls power to the respective PCIe
+ controller and a specifier name for the PCIe controller.
+
+ specifiers are defined in "include/dt-bindings/power/tegra194-powergate.h" file.
+
+ interconnects:
+ items:
+ - description: memory read client
+ - description: memory write client
+
+ interconnect-names:
+ items:
+ - const: dma-mem # read
+ - const: write
+
+ dma-coherent: true
+
+ nvidia,bpmp:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ Must contain a pair of phandle to BPMP controller node followed by
+ controller ID. Following are the controller IDs for each controller:
+
+ 0: C0
+ 1: C1
+ 2: C2
+ 3: C3
+ 4: C4
+ 5: C5
+ items:
+ - items:
+ - description: phandle to BPMP controller node
+ - description: PCIe controller ID
+ maximum: 5
+
+ nvidia,update-fc-fixup:
+ description: |
+ This is a boolean property and needs to be present to improve performance
+ when a platform is designed in such a way that it satisfies at least one
+ of the following conditions thereby enabling root port to exchange
+ optimum number of FC (Flow Control) credits with downstream devices:
+
+ 1. If C0/C4/C5 run at x1/x2 link widths (irrespective of speed and MPS)
+ 2. If C0/C1/C2/C3/C4/C5 operate at their respective max link widths and
+ a) speed is Gen-2 and MPS is 256B
+ b) speed is >= Gen-3 with any MPS
+
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ nvidia,aspm-cmrt-us:
+ description: Common Mode Restore Time for proper operation of ASPM to be
+ specified in microseconds
+
+ nvidia,aspm-pwr-on-t-us:
+ description: Power On time for proper operation of ASPM to be specified in
+ microseconds
+
+ nvidia,aspm-l0s-entrance-latency-us:
+ description: ASPM L0s entrance latency to be specified in microseconds
+
+ vddio-pex-ctl-supply:
+ description: A phandle to the regulator supply for PCIe side band signals.
+
+ vpcie3v3-supply:
+ description: A phandle to the regulator node that supplies 3.3V to the slot
+ if the platform has one such slot. (Ex:- x16 slot owned by C5 controller
+ in p2972-0000 platform).
+
+ vpcie12v-supply:
+ description: A phandle to the regulator node that supplies 12V to the slot
+ if the platform has one such slot. (Ex:- x16 slot owned by C5 controller
+ in p2972-0000 platform).
+
+allOf:
+ - $ref: /schemas/pci/pci-bus.yaml#
+ - $ref: /schemas/pci/snps,dw-pcie.yaml#
+
+unevaluatedProperties: false
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - interrupts
+ - interrupt-names
+ - interrupt-map
+ - interrupt-map-mask
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+ - power-domains
+ - bus-range
+ - ranges
+ - vddio-pex-ctl-supply
+ - num-lanes
+ - phys
+ - phy-names
+ - nvidia,bpmp
+
+examples:
+ - |
+ #include <dt-bindings/clock/tegra194-clock.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/tegra194-powergate.h>
+ #include <dt-bindings/reset/tegra194-reset.h>
+
+ bus@0 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0x8 0x0>;
+
+ pcie@14180000 {
+ compatible = "nvidia,tegra194-pcie";
+ power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
+ reg = <0x0 0x14180000 0x0 0x00020000>, /* appl registers (128K) */
+ <0x0 0x38000000 0x0 0x00040000>, /* configuration space (256K) */
+ <0x0 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
+ <0x0 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */
+ reg-names = "appl", "config", "atu_dma", "dbi";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ num-lanes = <8>;
+ linux,pci-domain = <0>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>;
+
+ clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
+ clock-names = "core";
+
+ resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
+ <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
+ reset-names = "apb", "core";
+
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
+ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
+ interrupt-names = "intr", "msi";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+
+ nvidia,bpmp = <&bpmp 0>;
+
+ supports-clkreq;
+ nvidia,aspm-cmrt-us = <60>;
+ nvidia,aspm-pwr-on-t-us = <20>;
+ nvidia,aspm-l0s-entrance-latency-us = <3>;
+
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000>, /* downstream I/O */
+ <0x82000000 0x0 0x38200000 0x0 0x38200000 0x0 0x01e00000>, /* non-prefetch memory */
+ <0xc2000000 0x18 0x00000000 0x18 0x00000000 0x4 0x00000000>; /* prefetchable memory */
+
+ vddio-pex-ctl-supply = <&vdd_1v8ao>;
+ vpcie3v3-supply = <&vdd_3v3_pcie>;
+ vpcie12v-supply = <&vdd_12v_pcie>;
+
+ phys = <&p2u_hsio_2>, <&p2u_hsio_3>, <&p2u_hsio_4>,
+ <&p2u_hsio_5>;
+ phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
+ };
+ };
diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
index c90e5e2d25f6..7e0bf941fbfe 100644
--- a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
@@ -35,7 +35,7 @@ properties:
maxItems: 5
items:
enum: [ dbi, dbi2, config, atu, app, elbi, mgmt, ctrl, parf, cfg, link,
- ulreg, smu, mpu, apb, phy ]
+ ulreg, smu, mpu, apb, phy, appl, atu_dma ]
num-lanes:
description: |
--
2.17.1
On Thu, Jul 07, 2022 at 01:42:53PM +0530, Vidya Sagar wrote:
> Convert the Tegra194 PCIe bindings from the free-form text format to
> json-schema.
>
> Signed-off-by: Vidya Sagar <[email protected]>
> Signed-off-by: Thierry Reding <[email protected]>
> ---
> V4:
> * Addressed review comments from Krzysztof and Rob
>
> V3:
> * New patch in this series. Added as part of addressing Rob's review
> comment to convert the existing .txt file to .yaml schema
>
> .../bindings/pci/nvidia,tegra194-pcie-ep.yaml | 228 ++++++++++++++++
> .../bindings/pci/nvidia,tegra194-pcie.txt | 245 -----------------
> .../bindings/pci/nvidia,tegra194-pcie.yaml | 257 ++++++++++++++++++
> .../devicetree/bindings/pci/snps,dw-pcie.yaml | 2 +-
> 4 files changed, 486 insertions(+), 246 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml
> delete mode 100644 Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt
> create mode 100644 Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml
[...]
> diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml
> new file mode 100644
> index 000000000000..5d7cb56c86a2
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml
> @@ -0,0 +1,257 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NVIDIA Tegra194 (and later) PCIe controller (Synopsys DesignWare Core based)
> +
> +maintainers:
> + - Thierry Reding <[email protected]>
> + - Jon Hunter <[email protected]>
> + - Vidya Sagar <[email protected]>
> +
> +description: |
> + This PCIe controller is based on the Synopsis Designware PCIe IP and thus
> + inherits all the common properties defined in snps,dw-pcie.yaml. Some of the
> + controller instances are dual mode where in they can work either in root port
> + mode or endpoint mode but one at a time.
> +
> + see nvidia,tegra194-pcie-ep.yaml for details on the endpoint mode device tree
> + bindings.
> +
> +properties:
> + compatible:
> + enum:
> + - nvidia,tegra194-pcie
> +
> + reg:
> + items:
> + - description: controller's application logic registers
> + - description: configuration registers
> + - description: iATU and DMA registers. This is where the iATU (internal
> + Address Translation Unit) registers of the PCIe core are made
> + available for software access.
> + - description: The aperture where the root port's own configuration
> + registers are available.
> +
> + reg-names:
> + items:
> + - const: appl
> + - const: config
> + - const: atu_dma
> + - const: dbi
> +
> + interrupts:
> + items:
> + - description: controller interrupt
> + - description: MSI interrupt
> +
> + interrupt-names:
> + items:
> + - const: intr
> + - const: msi
> +
> + clocks:
> + items:
> + - description: module clock
> +
> + clock-names:
> + items:
> + - const: core
> +
> + resets:
> + items:
> + - description: APB bus interface reset
> + - description: module reset
> +
> + reset-names:
> + items:
> + - const: apb
> + - const: core
> +
> + phys:
> + minItems: 1
> + maxItems: 8
> +
> + phy-names:
> + minItems: 1
> + items:
> + - const: p2u-0
> + - const: p2u-1
> + - const: p2u-2
> + - const: p2u-3
> + - const: p2u-4
> + - const: p2u-5
> + - const: p2u-6
> + - const: p2u-7
> +
> + power-domains:
> + maxItems: 1
> + description: |
> + A phandle to the node that controls power to the respective PCIe
> + controller and a specifier name for the PCIe controller.
> +
> + specifiers are defined in "include/dt-bindings/power/tegra194-powergate.h" file.
> +
> + interconnects:
> + items:
> + - description: memory read client
> + - description: memory write client
> +
> + interconnect-names:
> + items:
> + - const: dma-mem # read
> + - const: write
> +
> + dma-coherent: true
> +
> + nvidia,bpmp:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + description: |
> + Must contain a pair of phandle to BPMP controller node followed by
> + controller ID. Following are the controller IDs for each controller:
> +
> + 0: C0
> + 1: C1
> + 2: C2
> + 3: C3
> + 4: C4
> + 5: C5
> + items:
> + - items:
> + - description: phandle to BPMP controller node
> + - description: PCIe controller ID
> + maximum: 5
> +
> + nvidia,update-fc-fixup:
> + description: |
> + This is a boolean property and needs to be present to improve performance
> + when a platform is designed in such a way that it satisfies at least one
> + of the following conditions thereby enabling root port to exchange
> + optimum number of FC (Flow Control) credits with downstream devices:
> +
> + 1. If C0/C4/C5 run at x1/x2 link widths (irrespective of speed and MPS)
> + 2. If C0/C1/C2/C3/C4/C5 operate at their respective max link widths and
> + a) speed is Gen-2 and MPS is 256B
> + b) speed is >= Gen-3 with any MPS
> +
> + $ref: /schemas/types.yaml#/definitions/flag
> +
> + nvidia,aspm-cmrt-us:
> + description: Common Mode Restore Time for proper operation of ASPM to be
> + specified in microseconds
> +
> + nvidia,aspm-pwr-on-t-us:
> + description: Power On time for proper operation of ASPM to be specified in
> + microseconds
> +
> + nvidia,aspm-l0s-entrance-latency-us:
> + description: ASPM L0s entrance latency to be specified in microseconds
> +
> + vddio-pex-ctl-supply:
> + description: A phandle to the regulator supply for PCIe side band signals.
> +
> + vpcie3v3-supply:
> + description: A phandle to the regulator node that supplies 3.3V to the slot
> + if the platform has one such slot. (Ex:- x16 slot owned by C5 controller
> + in p2972-0000 platform).
> +
> + vpcie12v-supply:
> + description: A phandle to the regulator node that supplies 12V to the slot
> + if the platform has one such slot. (Ex:- x16 slot owned by C5 controller
> + in p2972-0000 platform).
> +
> +allOf:
> + - $ref: /schemas/pci/pci-bus.yaml#
Already referenced by this:
> + - $ref: /schemas/pci/snps,dw-pcie.yaml#
> +
> +unevaluatedProperties: false
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
Already required by snps,dw-pcie.yaml.
> + - interrupts
> + - interrupt-names
> + - interrupt-map
> + - interrupt-map-mask
> + - clocks
> + - clock-names
> + - resets
> + - reset-names
> + - power-domains
> + - bus-range
Should not be required. 0-0xff is the default.
> + - ranges
Already required by pci-bus.yaml
> + - vddio-pex-ctl-supply
> + - num-lanes
> + - phys
> + - phy-names
> + - nvidia,bpmp
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/tegra194-clock.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/power/tegra194-powergate.h>
> + #include <dt-bindings/reset/tegra194-reset.h>
> +
> + bus@0 {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges = <0x0 0x0 0x0 0x8 0x0>;
> +
> + pcie@14180000 {
> + compatible = "nvidia,tegra194-pcie";
> + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
> + reg = <0x0 0x14180000 0x0 0x00020000>, /* appl registers (128K) */
> + <0x0 0x38000000 0x0 0x00040000>, /* configuration space (256K) */
> + <0x0 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
> + <0x0 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */
> + reg-names = "appl", "config", "atu_dma", "dbi";
> +
> + #address-cells = <3>;
> + #size-cells = <2>;
> + device_type = "pci";
> + num-lanes = <8>;
> + linux,pci-domain = <0>;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>;
> +
> + clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
> + clock-names = "core";
> +
> + resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
> + <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
> + reset-names = "apb", "core";
> +
> + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
> + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
> + interrupt-names = "intr", "msi";
> +
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0>;
> + interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
> +
> + nvidia,bpmp = <&bpmp 0>;
> +
> + supports-clkreq;
> + nvidia,aspm-cmrt-us = <60>;
> + nvidia,aspm-pwr-on-t-us = <20>;
> + nvidia,aspm-l0s-entrance-latency-us = <3>;
> +
> + bus-range = <0x0 0xff>;
> + ranges = <0x81000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000>, /* downstream I/O */
> + <0x82000000 0x0 0x38200000 0x0 0x38200000 0x0 0x01e00000>, /* non-prefetch memory */
> + <0xc2000000 0x18 0x00000000 0x18 0x00000000 0x4 0x00000000>; /* prefetchable memory */
> +
> + vddio-pex-ctl-supply = <&vdd_1v8ao>;
> + vpcie3v3-supply = <&vdd_3v3_pcie>;
> + vpcie12v-supply = <&vdd_12v_pcie>;
> +
> + phys = <&p2u_hsio_2>, <&p2u_hsio_3>, <&p2u_hsio_4>,
> + <&p2u_hsio_5>;
> + phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
> + };
> + };
> diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
> index c90e5e2d25f6..7e0bf941fbfe 100644
> --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
> @@ -35,7 +35,7 @@ properties:
> maxItems: 5
> items:
> enum: [ dbi, dbi2, config, atu, app, elbi, mgmt, ctrl, parf, cfg, link,
> - ulreg, smu, mpu, apb, phy ]
> + ulreg, smu, mpu, apb, phy, appl, atu_dma ]
I'd put 'appl' next to 'app' and 'atu_dma' next to 'atu'.
With those fixes,
Reviewed-by: Rob Herring <[email protected]>
Rob