Hi,
this series contains patches related to the support of mt8365 power domains. I
took over the series from Fabien.
Best,
Markus
Changes in v2:
- Updated error handling path for scpsys_power_on()
- Minor updates described in each patch
Previous versions:
v1 - https://lore.kernel.org/linux-mediatek/[email protected]/
Alexandre Bailon (2):
soc: mediatek: Add support of WAY_EN operations
soc: mediatek: add support of MTK_SCPD_STRICT_BUSP cap
Fabien Parent (2):
dt-bindings: power: Add MT8365 power domains
soc: mediatek: pm-domains: Add support for MT8365
.../power/mediatek,power-controller.yaml | 2 +
drivers/soc/mediatek/mt8365-pm-domains.h | 147 ++++++++++++++++++
drivers/soc/mediatek/mtk-pm-domains.c | 98 +++++++++---
drivers/soc/mediatek/mtk-pm-domains.h | 29 ++--
include/dt-bindings/power/mt8365-power.h | 19 +++
5 files changed, 267 insertions(+), 28 deletions(-)
create mode 100644 drivers/soc/mediatek/mt8365-pm-domains.h
create mode 100644 include/dt-bindings/power/mt8365-power.h
--
2.36.1
From: Alexandre Bailon <[email protected]>
This adds support for MTK_SCPD_STRICT_BUSP capability. It is a strict
bus protection policy that requires the bus protection to be disabled
before accessing the bus.
This is required by the mt8365, for the MM power domain.
Signed-off-by: Alexandre Bailon <[email protected]>
Signed-off-by: Fabien Parent <[email protected]>
Signed-off-by: Markus Schneider-Pargmann <[email protected]>
---
Notes:
Changes in v2:
- Fixup error handling path.
drivers/soc/mediatek/mtk-pm-domains.c | 29 +++++++++++++++++++++++----
drivers/soc/mediatek/mtk-pm-domains.h | 1 +
2 files changed, 26 insertions(+), 4 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c
index d0eae2227813..94ca8981f45e 100644
--- a/drivers/soc/mediatek/mtk-pm-domains.c
+++ b/drivers/soc/mediatek/mtk-pm-domains.c
@@ -240,6 +240,7 @@ static int scpsys_power_on(struct generic_pm_domain *genpd)
struct scpsys *scpsys = pd->scpsys;
bool tmp;
int ret;
+ bool strict_busprotect;
ret = scpsys_regulator_enable(pd->supply);
if (ret)
@@ -263,9 +264,18 @@ static int scpsys_power_on(struct generic_pm_domain *genpd)
regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ISO_BIT);
regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT);
- ret = clk_bulk_prepare_enable(pd->num_subsys_clks, pd->subsys_clks);
- if (ret)
- goto err_pwr_ack;
+ /*
+ * In few Mediatek platforms(e.g. MT6779), the bus protect policy is
+ * stricter, which leads to bus protect release must be prior to bus
+ * access.
+ */
+ strict_busprotect = MTK_SCPD_CAPS(pd, MTK_SCPD_STRICT_BUSP);
+ if (!strict_busprotect) {
+ ret = clk_bulk_prepare_enable(pd->num_subsys_clks,
+ pd->subsys_clks);
+ if (ret)
+ goto err_pwr_ack;
+ }
ret = scpsys_sram_enable(pd);
if (ret < 0)
@@ -275,12 +285,23 @@ static int scpsys_power_on(struct generic_pm_domain *genpd)
if (ret < 0)
goto err_disable_sram;
+ if (strict_busprotect) {
+ ret = clk_bulk_prepare_enable(pd->num_subsys_clks,
+ pd->subsys_clks);
+ if (ret)
+ goto err_enable_bus_protect;
+ }
+
return 0;
+err_enable_bus_protect:
+ scpsys_bus_protect_enable(pd);
err_disable_sram:
scpsys_sram_disable(pd);
err_disable_subsys_clks:
- clk_bulk_disable_unprepare(pd->num_subsys_clks, pd->subsys_clks);
+ if (!strict_busprotect)
+ clk_bulk_disable_unprepare(pd->num_subsys_clks,
+ pd->subsys_clks);
err_pwr_ack:
clk_bulk_disable_unprepare(pd->num_clks, pd->clks);
err_reg:
diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/mtk-pm-domains.h
index e788d6bdde9d..a50cfb926d22 100644
--- a/drivers/soc/mediatek/mtk-pm-domains.h
+++ b/drivers/soc/mediatek/mtk-pm-domains.h
@@ -8,6 +8,7 @@
#define MTK_SCPD_SRAM_ISO BIT(2)
#define MTK_SCPD_KEEP_DEFAULT_OFF BIT(3)
#define MTK_SCPD_DOMAIN_SUPPLY BIT(4)
+#define MTK_SCPD_STRICT_BUSP BIT(5)
#define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x))
#define SPM_VDE_PWR_CON 0x0210
--
2.36.1
From: Fabien Parent <[email protected]>
Add the needed board data to support MT8365 SoC.
Signed-off-by: Fabien Parent <[email protected]>
Signed-off-by: Markus Schneider-Pargmann <[email protected]>
---
drivers/soc/mediatek/mt8365-pm-domains.h | 147 +++++++++++++++++++++++
drivers/soc/mediatek/mtk-pm-domains.c | 5 +
2 files changed, 152 insertions(+)
create mode 100644 drivers/soc/mediatek/mt8365-pm-domains.h
diff --git a/drivers/soc/mediatek/mt8365-pm-domains.h b/drivers/soc/mediatek/mt8365-pm-domains.h
new file mode 100644
index 000000000000..011049d64bb2
--- /dev/null
+++ b/drivers/soc/mediatek/mt8365-pm-domains.h
@@ -0,0 +1,147 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_MEDIATEK_MT8365_PM_DOMAINS_H
+#define __SOC_MEDIATEK_MT8365_PM_DOMAINS_H
+
+#include "mtk-pm-domains.h"
+#include <dt-bindings/power/mt8365-power.h>
+
+/*
+ * MT8365 power domain support
+ */
+
+static const struct scpsys_domain_data scpsys_domain_data_mt8365[] = {
+ [MT8365_POWER_DOMAIN_MM] = {
+ .name = "mm",
+ .sta_mask = PWR_STATUS_DISP,
+ .ctl_offs = 0x30c,
+ .pwr_sta_offs = 0x0180,
+ .pwr_sta2nd_offs = 0x0184,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .caps = MTK_SCPD_STRICT_BUSP,
+ .bp_infracfg = {
+ BUS_PROT_WR(BIT(16) | BIT(17), 0x2a8, 0x2ac, 0x258),
+ BUS_PROT_WR(BIT(1) | BIT(2) | BIT(10) | BIT(11), 0x2a0, 0x2a4, 0x228),
+ BUS_PROT_WAY_EN(BIT(6), BIT(24), 0x200, 0x0),
+ BUS_PROT_WAY_EN(BIT(5), BIT(14), 0x234, 0x28),
+ BUS_PROT_WR(BIT(6), 0x2a0, 0x2a4, 0x228),
+ },
+ },
+ [MT8365_POWER_DOMAIN_VENC] = {
+ .name = "venc",
+ .sta_mask = PWR_STATUS_VENC,
+ .ctl_offs = 0x0304,
+ .pwr_sta_offs = 0x0180,
+ .pwr_sta2nd_offs = 0x0184,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .bp_smi = {
+ BUS_PROT_WR(BIT(1), 0x3c4, 0x3c8, 0x3c0),
+ },
+ },
+ [MT8365_POWER_DOMAIN_AUDIO] = {
+ .name = "audio",
+ .sta_mask = PWR_STATUS_AUDIO,
+ .ctl_offs = 0x0314,
+ .pwr_sta_offs = 0x0180,
+ .pwr_sta2nd_offs = 0x0184,
+ .sram_pdn_bits = GENMASK(12, 8),
+ .sram_pdn_ack_bits = GENMASK(17, 13),
+ .bp_infracfg = {
+ BUS_PROT_WR(BIT(27) | BIT(28), 0x2a8, 0x2ac, 0x258),
+ },
+ .caps = MTK_SCPD_ACTIVE_WAKEUP,
+ },
+ [MT8365_POWER_DOMAIN_CONN] = {
+ .name = "conn",
+ .sta_mask = PWR_STATUS_CONN,
+ .ctl_offs = 0x032c,
+ .pwr_sta_offs = 0x0180,
+ .pwr_sta2nd_offs = 0x0184,
+ .sram_pdn_bits = 0,
+ .sram_pdn_ack_bits = 0,
+ .bp_infracfg = {
+ BUS_PROT_WR(BIT(13), 0x2a0, 0x2a4, 0x228),
+ BUS_PROT_WR(BIT(18), 0x2a8, 0x2ac, 0x258),
+ BUS_PROT_WR(BIT(14), 0x2a0, 0x2a4, 0x228),
+ BUS_PROT_WR(BIT(21), 0x2a8, 0x2ac, 0x258),
+ },
+ .caps = MTK_SCPD_ACTIVE_WAKEUP | MTK_SCPD_KEEP_DEFAULT_OFF,
+ },
+ [MT8365_POWER_DOMAIN_MFG] = {
+ .name = "mfg",
+ .sta_mask = PWR_STATUS_MFG,
+ .ctl_offs = 0x0338,
+ .pwr_sta_offs = 0x0180,
+ .pwr_sta2nd_offs = 0x0184,
+ .sram_pdn_bits = GENMASK(9, 8),
+ .sram_pdn_ack_bits = GENMASK(13, 12),
+ .bp_infracfg = {
+ BUS_PROT_WR(BIT(25), 0x2a0, 0x2a4, 0x228),
+ BUS_PROT_WR(BIT(21) | BIT(22), 0x2a0, 0x2a4, 0x228),
+ },
+ },
+ [MT8365_POWER_DOMAIN_CAM] = {
+ .name = "cam",
+ .sta_mask = BIT(25),
+ .ctl_offs = 0x0344,
+ .pwr_sta_offs = 0x0180,
+ .pwr_sta2nd_offs = 0x0184,
+ .sram_pdn_bits = GENMASK(9, 8),
+ .sram_pdn_ack_bits = GENMASK(13, 12),
+ .bp_infracfg = {
+ BUS_PROT_WR(BIT(19), 0x2a8, 0x2ac, 0x258),
+ },
+ .bp_smi = {
+ BUS_PROT_WR(BIT(2), 0x3c4, 0x3c8, 0x3c0),
+ },
+ },
+ [MT8365_POWER_DOMAIN_VDEC] = {
+ .name = "vdec",
+ .sta_mask = BIT(31),
+ .ctl_offs = 0x0370,
+ .pwr_sta_offs = 0x0180,
+ .pwr_sta2nd_offs = 0x0184,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .bp_smi = {
+ BUS_PROT_WR(BIT(3), 0x3c4, 0x3c8, 0x3c0),
+ },
+ },
+ [MT8365_POWER_DOMAIN_APU] = {
+ .name = "apu",
+ .sta_mask = BIT(16),
+ .ctl_offs = 0x0378,
+ .pwr_sta_offs = 0x0180,
+ .pwr_sta2nd_offs = 0x0184,
+ .sram_pdn_bits = GENMASK(14, 8),
+ .sram_pdn_ack_bits = GENMASK(21, 15),
+ .bp_infracfg = {
+ BUS_PROT_WR(BIT(2) | BIT(20), 0x2a8, 0x2ac, 0x258),
+ },
+ .bp_smi = {
+ BUS_PROT_WR(BIT(4), 0x3c4, 0x3c8, 0x3c0),
+ },
+ },
+ [MT8365_POWER_DOMAIN_DSP] = {
+ .name = "dsp",
+ .sta_mask = BIT(17),
+ .ctl_offs = 0x037C,
+ .pwr_sta_offs = 0x0180,
+ .pwr_sta2nd_offs = 0x0184,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(15, 12),
+ .bp_infracfg = {
+ BUS_PROT_WR(BIT(24) | BIT(30) | BIT(31), 0x2a8, 0x2ac, 0x258),
+ },
+ .caps = MTK_SCPD_ACTIVE_WAKEUP,
+ },
+};
+
+static const struct scpsys_soc_data mt8365_scpsys_data = {
+ .domains_data = scpsys_domain_data_mt8365,
+ .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8365),
+};
+
+#endif /* __SOC_MEDIATEK_MT8365_PM_DOMAINS_H */
diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c
index 94ca8981f45e..7bfadc8dee7e 100644
--- a/drivers/soc/mediatek/mtk-pm-domains.c
+++ b/drivers/soc/mediatek/mtk-pm-domains.c
@@ -22,6 +22,7 @@
#include "mt8186-pm-domains.h"
#include "mt8192-pm-domains.h"
#include "mt8195-pm-domains.h"
+#include "mt8365-pm-domains.h"
#define MTK_POLL_DELAY_US 10
#define MTK_POLL_TIMEOUT USEC_PER_SEC
@@ -636,6 +637,10 @@ static const struct of_device_id scpsys_of_match[] = {
.compatible = "mediatek,mt8195-power-controller",
.data = &mt8195_scpsys_data,
},
+ {
+ .compatible = "mediatek,mt8365-power-controller",
+ .data = &mt8365_scpsys_data,
+ },
{ }
};
--
2.36.1
Il 25/07/22 10:18, Markus Schneider-Pargmann ha scritto:
> From: Alexandre Bailon <[email protected]>
>
> This adds support for MTK_SCPD_STRICT_BUSP capability. It is a strict
> bus protection policy that requires the bus protection to be disabled
> before accessing the bus.
> This is required by the mt8365, for the MM power domain.
>
> Signed-off-by: Alexandre Bailon <[email protected]>
> Signed-off-by: Fabien Parent <[email protected]>
> Signed-off-by: Markus Schneider-Pargmann <[email protected]>
> ---
>
> Notes:
> Changes in v2:
> - Fixup error handling path.
>
> drivers/soc/mediatek/mtk-pm-domains.c | 29 +++++++++++++++++++++++----
> drivers/soc/mediatek/mtk-pm-domains.h | 1 +
> 2 files changed, 26 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c
> index d0eae2227813..94ca8981f45e 100644
> --- a/drivers/soc/mediatek/mtk-pm-domains.c
> +++ b/drivers/soc/mediatek/mtk-pm-domains.c
> @@ -240,6 +240,7 @@ static int scpsys_power_on(struct generic_pm_domain *genpd)
> struct scpsys *scpsys = pd->scpsys;
> bool tmp;
> int ret;
> + bool strict_busprotect;
>
> ret = scpsys_regulator_enable(pd->supply);
> if (ret)
> @@ -263,9 +264,18 @@ static int scpsys_power_on(struct generic_pm_domain *genpd)
> regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ISO_BIT);
> regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT);
>
> - ret = clk_bulk_prepare_enable(pd->num_subsys_clks, pd->subsys_clks);
> - if (ret)
> - goto err_pwr_ack;
> + /*
> + * In few Mediatek platforms(e.g. MT6779), the bus protect policy is
> + * stricter, which leads to bus protect release must be prior to bus
> + * access.
> + */
> + strict_busprotect = MTK_SCPD_CAPS(pd, MTK_SCPD_STRICT_BUSP);
> + if (!strict_busprotect) {
Please directly check for MTK_SCPD_CAPS, you don't really need that bool variable,
not even for performance... and it fits just fine in one line, even.
if (!MTK_SCPD_CAPS(pd, MTK_SCPD_STRICT_BUS_PROTECTION)) {
> + ret = clk_bulk_prepare_enable(pd->num_subsys_clks,
> + pd->subsys_clks);
> + if (ret)
> + goto err_pwr_ack;
> + }
>
> ret = scpsys_sram_enable(pd);
> if (ret < 0)
> @@ -275,12 +285,23 @@ static int scpsys_power_on(struct generic_pm_domain *genpd)
> if (ret < 0)
> goto err_disable_sram;
>
> + if (strict_busprotect) {
if (MTK_SCPD_CAPS(pd, MTK_SCPD_STRICT_BUS_PROTECTION)) {
> + ret = clk_bulk_prepare_enable(pd->num_subsys_clks,
> + pd->subsys_clks);
> + if (ret)
> + goto err_enable_bus_protect;
> + }
> +
> return 0;
>
> +err_enable_bus_protect:
For human readability purposes (and paranoidly preventing future mistakes), I'd
add a check for the strict bus protection cap here too.
> + scpsys_bus_protect_enable(pd);
> err_disable_sram:
> scpsys_sram_disable(pd);
> err_disable_subsys_clks:
> - clk_bulk_disable_unprepare(pd->num_subsys_clks, pd->subsys_clks);
> + if (!strict_busprotect)
> + clk_bulk_disable_unprepare(pd->num_subsys_clks,
> + pd->subsys_clks);
> err_pwr_ack:
> clk_bulk_disable_unprepare(pd->num_clks, pd->clks);
> err_reg:
> diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/mtk-pm-domains.h
> index e788d6bdde9d..a50cfb926d22 100644
> --- a/drivers/soc/mediatek/mtk-pm-domains.h
> +++ b/drivers/soc/mediatek/mtk-pm-domains.h
> @@ -8,6 +8,7 @@
> #define MTK_SCPD_SRAM_ISO BIT(2)
> #define MTK_SCPD_KEEP_DEFAULT_OFF BIT(3)
> #define MTK_SCPD_DOMAIN_SUPPLY BIT(4)
> +#define MTK_SCPD_STRICT_BUSP BIT(5)
MTK_SCPD_STRICT_BUS_PROTECTION is a bit more human readable.
> #define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x))
>
> #define SPM_VDE_PWR_CON 0x0210
Regards,
Angelo