Allow a consumer driver to poll for cx gdsc collapse through Reset
framework.
Signed-off-by: Akhil P Oommen <[email protected]>
---
drivers/clk/qcom/gpucc-sc7280.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/clk/qcom/gpucc-sc7280.c b/drivers/clk/qcom/gpucc-sc7280.c
index 9a832f2..f5df51d 100644
--- a/drivers/clk/qcom/gpucc-sc7280.c
+++ b/drivers/clk/qcom/gpucc-sc7280.c
@@ -433,12 +433,18 @@ static const struct regmap_config gpu_cc_sc7280_regmap_config = {
.fast_io = true,
};
+static const struct qcom_reset_map gpucc_sc7280_resets[] = {
+ [GPU_CX_COLLAPSE] = { .op = gdsc_wait_for_collapse, .priv = &cx_gdsc },
+};
+
static const struct qcom_cc_desc gpu_cc_sc7280_desc = {
.config = &gpu_cc_sc7280_regmap_config,
.clks = gpu_cc_sc7280_clocks,
.num_clks = ARRAY_SIZE(gpu_cc_sc7280_clocks),
.gdscs = gpu_cc_sc7180_gdscs,
.num_gdscs = ARRAY_SIZE(gpu_cc_sc7180_gdscs),
+ .resets = gpucc_sc7280_resets,
+ .num_resets = ARRAY_SIZE(gpucc_sc7280_resets),
};
static const struct of_device_id gpu_cc_sc7280_match_table[] = {
--
2.7.4
On 30/07/2022 12:17, Akhil P Oommen wrote:
> Allow a consumer driver to poll for cx gdsc collapse through Reset
> framework.
>
> Signed-off-by: Akhil P Oommen <[email protected]>
> ---
>
> drivers/clk/qcom/gpucc-sc7280.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/clk/qcom/gpucc-sc7280.c b/drivers/clk/qcom/gpucc-sc7280.c
> index 9a832f2..f5df51d 100644
> --- a/drivers/clk/qcom/gpucc-sc7280.c
> +++ b/drivers/clk/qcom/gpucc-sc7280.c
> @@ -433,12 +433,18 @@ static const struct regmap_config gpu_cc_sc7280_regmap_config = {
> .fast_io = true,
> };
>
> +static const struct qcom_reset_map gpucc_sc7280_resets[] = {
> + [GPU_CX_COLLAPSE] = { .op = gdsc_wait_for_collapse, .priv = &cx_gdsc },
This will break bisectability. Please swap this one and the patch 4.
> +};
> +
> static const struct qcom_cc_desc gpu_cc_sc7280_desc = {
> .config = &gpu_cc_sc7280_regmap_config,
> .clks = gpu_cc_sc7280_clocks,
> .num_clks = ARRAY_SIZE(gpu_cc_sc7280_clocks),
> .gdscs = gpu_cc_sc7180_gdscs,
> .num_gdscs = ARRAY_SIZE(gpu_cc_sc7180_gdscs),
> + .resets = gpucc_sc7280_resets,
> + .num_resets = ARRAY_SIZE(gpucc_sc7280_resets),
> };
>
> static const struct of_device_id gpu_cc_sc7280_match_table[] = {
--
With best wishes
Dmitry
On 30/07/2022 12:17, Akhil P Oommen wrote:
> Allow a consumer driver to poll for cx gdsc collapse through Reset
> framework.
>
> Signed-off-by: Akhil P Oommen <[email protected]>
> ---
>
> drivers/clk/qcom/gpucc-sc7280.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/clk/qcom/gpucc-sc7280.c b/drivers/clk/qcom/gpucc-sc7280.c
> index 9a832f2..f5df51d 100644
> --- a/drivers/clk/qcom/gpucc-sc7280.c
> +++ b/drivers/clk/qcom/gpucc-sc7280.c
> @@ -433,12 +433,18 @@ static const struct regmap_config gpu_cc_sc7280_regmap_config = {
> .fast_io = true,
> };
>
> +static const struct qcom_reset_map gpucc_sc7280_resets[] = {
> + [GPU_CX_COLLAPSE] = { .op = gdsc_wait_for_collapse, .priv = &cx_gdsc },
> +};
> +
> static const struct qcom_cc_desc gpu_cc_sc7280_desc = {
> .config = &gpu_cc_sc7280_regmap_config,
> .clks = gpu_cc_sc7280_clocks,
> .num_clks = ARRAY_SIZE(gpu_cc_sc7280_clocks),
> .gdscs = gpu_cc_sc7180_gdscs,
> .num_gdscs = ARRAY_SIZE(gpu_cc_sc7180_gdscs),
> + .resets = gpucc_sc7280_resets,
> + .num_resets = ARRAY_SIZE(gpucc_sc7280_resets),
An implementation question. Do we have to poll for the GDSC on platforms
like sm8150/sm8250 which have the plain BCR resets?
> };
>
> static const struct of_device_id gpu_cc_sc7280_match_table[] = {
--
With best wishes
Dmitry
On 8/2/2022 12:45 PM, Dmitry Baryshkov wrote:
> On 30/07/2022 12:17, Akhil P Oommen wrote:
>> Allow a consumer driver to poll for cx gdsc collapse through Reset
>> framework.
>>
>> Signed-off-by: Akhil P Oommen <[email protected]>
>> ---
>>
>> drivers/clk/qcom/gpucc-sc7280.c | 6 ++++++
>> 1 file changed, 6 insertions(+)
>>
>> diff --git a/drivers/clk/qcom/gpucc-sc7280.c
>> b/drivers/clk/qcom/gpucc-sc7280.c
>> index 9a832f2..f5df51d 100644
>> --- a/drivers/clk/qcom/gpucc-sc7280.c
>> +++ b/drivers/clk/qcom/gpucc-sc7280.c
>> @@ -433,12 +433,18 @@ static const struct regmap_config
>> gpu_cc_sc7280_regmap_config = {
>> .fast_io = true,
>> };
>> +static const struct qcom_reset_map gpucc_sc7280_resets[] = {
>> + [GPU_CX_COLLAPSE] = { .op = gdsc_wait_for_collapse, .priv =
>> &cx_gdsc },
>> +};
>> +
>> static const struct qcom_cc_desc gpu_cc_sc7280_desc = {
>> .config = &gpu_cc_sc7280_regmap_config,
>> .clks = gpu_cc_sc7280_clocks,
>> .num_clks = ARRAY_SIZE(gpu_cc_sc7280_clocks),
>> .gdscs = gpu_cc_sc7180_gdscs,
>> .num_gdscs = ARRAY_SIZE(gpu_cc_sc7180_gdscs),
>> + .resets = gpucc_sc7280_resets,
>> + .num_resets = ARRAY_SIZE(gpucc_sc7280_resets),
>
> An implementation question. Do we have to poll for the GDSC on
> platforms like sm8150/sm8250 which have the plain BCR resets?
Yes.
Thanks for all the feedback, Dmitry. I will post another version of this
series.
-Akhil.
>
>> };
>> static const struct of_device_id gpu_cc_sc7280_match_table[] = {
>
>