2022-08-04 13:38:53

by Balsam CHIHI

Subject: [PATCH v8.1, 3/7] arm64: dts: mt8192: Add thermal zone

From: Balsam CHIHI <[email protected]>

This adds the thermal zone for the mt8192.

Signed-off-by: Balsam CHIHI <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 113 ++++++++++++++++++++++-
1 file changed, 112 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index cbae5a5ee4a0..3320b5c14ee3 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
- * Copyright (C) 2020 MediaTek Inc.
+ * Copyright (C) 2022 MediaTek Inc.
* Author: Seiya Wang <[email protected]>
*/

@@ -12,6 +12,7 @@
#include <dt-bindings/pinctrl/mt8192-pinfunc.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/power/mt8192-power.h>
+#include <dt-bindings/reset/mt8192-resets.h>

/ {
compatible = "mediatek,mt8192";
@@ -599,6 +600,28 @@ spi0: spi@1100a000 {
status = "disabled";
};

+ lvts_ap: thermal-sensor@1100b000 {
+ compatible = "mediatek,mt8192-lvts-ap";
+ #thermal-sensor-cells = <1>;
+ reg = <0 0x1100b000 0 0x1000>;
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&infracfg CLK_INFRA_THERM>;
+ resets = <&infracfg MT8192_INFRA_RST0_THERM_CTRL_SWRST>;
+ nvmem-cells = <&lvts_e_data1>;
+ nvmem-cell-names = "lvts_calib_data1";
+ };
+
+ lvts_mcu: thermal-sensor@11278000 {
+ compatible = "mediatek,mt8192-lvts-mcu";
+ #thermal-sensor-cells = <1>;
+ reg = <0 0x11278000 0 0x1000>;
+ interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&infracfg CLK_INFRA_THERM>;
+ resets = <&infracfg MT8192_INFRA_RST4_THERM_CTRL_MCU_SWRST>;
+ nvmem-cells = <&lvts_e_data1>;
+ nvmem-cell-names = "lvts_calib_data1";
+ };
+
spi1: spi@11010000 {
compatible = "mediatek,mt8192-spi",
"mediatek,mt6765-spi";
@@ -1457,4 +1480,92 @@ larb2: larb@1f002000 {
power-domains = <&spm MT8192_POWER_DOMAIN_MDP>;
};
};
+
+ thermal_zones: thermal-zones {
+ cpu-big1-thermal {
+ polling-delay = <0>;
+ polling-delay-passive = <0>;
+ thermal-sensors = <&lvts_mcu 0>;
+ };
+ cpu-big2-thermal {
+ polling-delay = <0>;
+ polling-delay-passive = <0>;
+ thermal-sensors = <&lvts_mcu 1>;
+ };
+ cpu-big3-thermal {
+ polling-delay = <0>;
+ polling-delay-passive = <0>;
+ thermal-sensors = <&lvts_mcu 2>;
+ };
+ cpu-big4-thermal {
+ polling-delay = <0>;
+ polling-delay-passive = <0>;
+ thermal-sensors = <&lvts_mcu 3>;
+ };
+ cpu-little1-thermal {
+ polling-delay = <0>;
+ polling-delay-passive = <0>;
+ thermal-sensors = <&lvts_mcu 4>;
+ };
+ cpu-little2-thermal {
+ polling-delay = <0>;
+ polling-delay-passive = <0>;
+ thermal-sensors = <&lvts_mcu 5>;
+ };
+ cpu-little3-thermal {
+ polling-delay = <0>;
+ polling-delay-passive = <0>;
+ thermal-sensors = <&lvts_mcu 6>;
+ };
+ cpu-little4-thermal {
+ polling-delay = <0>;
+ polling-delay-passive = <0>;
+ thermal-sensors = <&lvts_mcu 7>;
+ };
+ vpu1-thermal {
+ polling-delay = <0>;
+ polling-delay-passive = <0>;
+ thermal-sensors = <&lvts_ap 0>;
+ };
+ vpu2-thermal {
+ polling-delay = <0>;
+ polling-delay-passive = <0>;
+ thermal-sensors = <&lvts_ap 1>;
+ };
+ gpu1-thermal {
+ polling-delay = <0>;
+ polling-delay-passive = <0>;
+ thermal-sensors = <&lvts_ap 2>;
+ };
+ gpu2-thermal {
+ polling-delay = <0>;
+ polling-delay-passive = <0>;
+ thermal-sensors = <&lvts_ap 3>;
+ };
+ vdec-thermal {
+ polling-delay = <0>;
+ polling-delay-passive = <0>;
+ thermal-sensors = <&lvts_ap 4>;
+ };
+ img-thermal {
+ polling-delay = <0>;
+ polling-delay-passive = <0>;
+ thermal-sensors = <&lvts_ap 5>;
+ };
+ infra-thermal {
+ polling-delay = <0>;
+ polling-delay-passive = <0>;
+ thermal-sensors = <&lvts_ap 6>;
+ };
+ cam1-thermal {
+ polling-delay = <0>;
+ polling-delay-passive = <0>;
+ thermal-sensors = <&lvts_ap 7>;
+ };
+ cam2-thermal {
+ polling-delay = <0>;
+ polling-delay-passive = <0>;
+ thermal-sensors = <&lvts_ap 8>;
+ };
+ };
};
--
2.34.1

2022-08-04 15:40:56

by Krzysztof Kozlowski

Subject: Re: [PATCH v8.1, 3/7] arm64: dts: mt8192: Add thermal zone

On 04/08/2022 15:09, [email protected] wrote:
> From: Balsam CHIHI <[email protected]>
>
> This adds the thermal zone for the mt8192.
>
> Signed-off-by: Balsam CHIHI <[email protected]>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 113 ++++++++++++++++++++++-
> 1 file changed, 112 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index cbae5a5ee4a0..3320b5c14ee3 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1,6 +1,6 @@
> // SPDX-License-Identifier: (GPL-2.0 OR MIT)
> /*
> - * Copyright (C) 2020 MediaTek Inc.
> + * Copyright (C) 2022 MediaTek Inc.

This is unexpected, so it needs careful explanation.

> * Author: Seiya Wang <[email protected]>
> */
>
> @@ -12,6 +12,7 @@
> #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
> #include <dt-bindings/phy/phy.h>
> #include <dt-bindings/power/mt8192-power.h>
> +#include <dt-bindings/reset/mt8192-resets.h>
>
> / {
> compatible = "mediatek,mt8192";
> @@ -599,6 +600,28 @@ spi0: spi@1100a000 {
> status = "disabled";
> };
>
> + lvts_ap: thermal-sensor@1100b000 {
> + compatible = "mediatek,mt8192-lvts-ap";
> + #thermal-sensor-cells = <1>;
> + reg = <0 0x1100b000 0 0x1000>;
> + interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&infracfg CLK_INFRA_THERM>;
> + resets = <&infracfg MT8192_INFRA_RST0_THERM_CTRL_SWRST>;
> + nvmem-cells = <&lvts_e_data1>;
> + nvmem-cell-names = "lvts_calib_data1";
> + };
> +
> + lvts_mcu: thermal-sensor@11278000 {
> + compatible = "mediatek,mt8192-lvts-mcu";
> + #thermal-sensor-cells = <1>;
> + reg = <0 0x11278000 0 0x1000>;
> + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&infracfg CLK_INFRA_THERM>;
> + resets = <&infracfg MT8192_INFRA_RST4_THERM_CTRL_MCU_SWRST>;
> + nvmem-cells = <&lvts_e_data1>;
> + nvmem-cell-names = "lvts_calib_data1";
> + };
> +
> spi1: spi@11010000 {
> compatible = "mediatek,mt8192-spi",
> "mediatek,mt6765-spi";
> @@ -1457,4 +1480,92 @@ larb2: larb@1f002000 {
> power-domains = <&spm MT8192_POWER_DOMAIN_MDP>;
> };
> };
> +
> + thermal_zones: thermal-zones {
> + cpu-big1-thermal {

Names look not matching DT schema.


Best regards,
Krzysztof

2022-08-04 23:33:10

by Nícolas F. R. A. Prado

Subject: Re: [PATCH v8.1, 3/7] arm64: dts: mt8192: Add thermal zone

On Thu, Aug 04, 2022 at 03:09:08PM +0200, [email protected] wrote:
> From: Balsam CHIHI <[email protected]>
>
> This adds the thermal zone for the mt8192.
>
> Signed-off-by: Balsam CHIHI <[email protected]>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 113 ++++++++++++++++++++++-
> 1 file changed, 112 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index cbae5a5ee4a0..3320b5c14ee3 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
[..]
> + vdec-thermal {

infra-thermal

> + polling-delay = <0>;
> + polling-delay-passive = <0>;
> + thermal-sensors = <&lvts_ap 4>;
> + };
> + img-thermal {

cam-thermal

> + polling-delay = <0>;
> + polling-delay-passive = <0>;
> + thermal-sensors = <&lvts_ap 5>;
> + };
> + infra-thermal {

md1-thermal

> + polling-delay = <0>;
> + polling-delay-passive = <0>;
> + thermal-sensors = <&lvts_ap 6>;
> + };
> + cam1-thermal {

md2-thermal

> + polling-delay = <0>;
> + polling-delay-passive = <0>;
> + thermal-sensors = <&lvts_ap 7>;
> + };
> + cam2-thermal {

md3-thermal

Thanks,
N?colas

> + polling-delay = <0>;
> + polling-delay-passive = <0>;
> + thermal-sensors = <&lvts_ap 8>;
> + };
> + };
> };
> --
> 2.34.1
>
>