This adds binding and implementation of the SC8280XP display clock controller.
Bjorn Andersson (2):
dt-bindings: clock: Add Qualcomm SC8280XP display clock bindings
clk: qcom: Add SC8280XP display clock controller
.../bindings/clock/qcom,dispcc-sc8280xp.yaml | 98 +
drivers/clk/qcom/Kconfig | 9 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/dispcc-sc8280xp.c | 3218 +++++++++++++++++
.../dt-bindings/clock/qcom,dispcc-sc8280xp.h | 100 +
5 files changed, 3426 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,dispcc-sc8280xp.yaml
create mode 100644 drivers/clk/qcom/dispcc-sc8280xp.c
create mode 100644 include/dt-bindings/clock/qcom,dispcc-sc8280xp.h
--
2.35.1
The Qualcomm SC8280XP platform has two display clock controllers, add a
binding for these.
Signed-off-by: Bjorn Andersson <[email protected]>
---
.../bindings/clock/qcom,dispcc-sc8280xp.yaml | 98 +++++++++++++++++
.../dt-bindings/clock/qcom,dispcc-sc8280xp.h | 100 ++++++++++++++++++
2 files changed, 198 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,dispcc-sc8280xp.yaml
create mode 100644 include/dt-bindings/clock/qcom,dispcc-sc8280xp.h
diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sc8280xp.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sc8280xp.yaml
new file mode 100644
index 000000000000..98e5dfd53f76
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sc8280xp.yaml
@@ -0,0 +1,98 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,dispcc-sc8280xp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Display Clock & Reset Controller Binding for SC8280XP
+
+maintainers:
+ - Bjorn Andersson <[email protected]>
+
+description: |
+ Qualcomm display clock control module which supports the clocks, resets and
+ power domains for the two MDSS instances on SC8280XP.
+
+ See also:
+ include/dt-bindings/clock/qcom,dispcc-sc8280xp.h
+
+properties:
+ compatible:
+ enum:
+ - qcom,sc8280x-dispcc0
+ - qcom,sc8280x-dispcc1
+
+ clocks:
+ items:
+ - description: AHB interface clock,
+ - description: SoC CXO clock
+ - description: SoC sleep clock
+ - description: DisplayPort 0 link clock
+ - description: DisplayPort 0 VCO div clock
+ - description: DisplayPort 1 link clock
+ - description: DisplayPort 1 VCO div clock
+ - description: DisplayPort 2 link clock
+ - description: DisplayPort 2 VCO div clock
+ - description: DisplayPort 3 link clock
+ - description: DisplayPort 3 VCO div clock
+ - description: DSI 0 PLL byte clock
+ - description: DSI 0 PLL DSI clock
+ - description: DSI 1 PLL byte clock
+ - description: DSI 1 PLL DSI clock
+
+ '#clock-cells':
+ const: 1
+
+ '#reset-cells':
+ const: 1
+
+ '#power-domain-cells':
+ const: 1
+
+ reg:
+ maxItems: 1
+
+ power-domains:
+ description:
+ A phandle and PM domain specifier for the MMCX power domain.
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - '#clock-cells'
+ - '#reset-cells'
+ - '#power-domain-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ #include <dt-bindings/power/qcom-rpmpd.h>
+ clock-controller@af00000 {
+ compatible = "qcom,sc8280xp-dispcc0";
+ reg = <0x0af00000 0x20000>;
+ clocks = <&gcc GCC_DISP_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <&sleep_clk>,
+ <&mdss0_dp_phy0 0>,
+ <&mdss0_dp_phy0 1>,
+ <&mdss0_dp_phy1 0>,
+ <&mdss0_dp_phy1 1>,
+ <&mdss0_dp_phy2 0>,
+ <&mdss0_dp_phy2 1>,
+ <&mdss0_dp_phy3 0>,
+ <&mdss0_dp_phy3 1>,
+ <&mdss0_dsi0_phy 0>,
+ <&mdss0_dsi0_phy 1>,
+ <&mdss0_dsi1_phy 0>,
+ <&mdss0_dsi1_phy 1>;
+ power-domains = <&rpmhpd SC8280XP_MMCX>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+...
diff --git a/include/dt-bindings/clock/qcom,dispcc-sc8280xp.h b/include/dt-bindings/clock/qcom,dispcc-sc8280xp.h
new file mode 100644
index 000000000000..2831c61fa979
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,dispcc-sc8280xp.h
@@ -0,0 +1,100 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SC8280XP_H
+#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SC8280XP_H
+
+/* DISPCC clocks */
+#define DISP_CC_PLL0 0
+#define DISP_CC_PLL1 1
+#define DISP_CC_PLL1_OUT_EVEN 2
+#define DISP_CC_PLL2 3
+#define DISP_CC_MDSS_AHB1_CLK 4
+#define DISP_CC_MDSS_AHB_CLK 5
+#define DISP_CC_MDSS_AHB_CLK_SRC 6
+#define DISP_CC_MDSS_BYTE0_CLK 7
+#define DISP_CC_MDSS_BYTE0_CLK_SRC 8
+#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 9
+#define DISP_CC_MDSS_BYTE0_INTF_CLK 10
+#define DISP_CC_MDSS_BYTE1_CLK 11
+#define DISP_CC_MDSS_BYTE1_CLK_SRC 12
+#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 13
+#define DISP_CC_MDSS_BYTE1_INTF_CLK 14
+#define DISP_CC_MDSS_DPTX0_AUX_CLK 15
+#define DISP_CC_MDSS_DPTX0_AUX_CLK_SRC 16
+#define DISP_CC_MDSS_DPTX0_LINK_CLK 17
+#define DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 18
+#define DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC 19
+#define DISP_CC_MDSS_DPTX0_LINK_INTF_CLK 20
+#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK 21
+#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC 22
+#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK 23
+#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC 24
+#define DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK 25
+#define DISP_CC_MDSS_DPTX1_AUX_CLK 26
+#define DISP_CC_MDSS_DPTX1_AUX_CLK_SRC 27
+#define DISP_CC_MDSS_DPTX1_LINK_CLK 28
+#define DISP_CC_MDSS_DPTX1_LINK_CLK_SRC 29
+#define DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC 30
+#define DISP_CC_MDSS_DPTX1_LINK_INTF_CLK 31
+#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK 32
+#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC 33
+#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK 34
+#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC 35
+#define DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK 36
+#define DISP_CC_MDSS_DPTX2_AUX_CLK 37
+#define DISP_CC_MDSS_DPTX2_AUX_CLK_SRC 38
+#define DISP_CC_MDSS_DPTX2_LINK_CLK 39
+#define DISP_CC_MDSS_DPTX2_LINK_CLK_SRC 40
+#define DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC 41
+#define DISP_CC_MDSS_DPTX2_LINK_INTF_CLK 42
+#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK 43
+#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC 44
+#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK 45
+#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC 46
+#define DISP_CC_MDSS_DPTX3_AUX_CLK 47
+#define DISP_CC_MDSS_DPTX3_AUX_CLK_SRC 48
+#define DISP_CC_MDSS_DPTX3_LINK_CLK 49
+#define DISP_CC_MDSS_DPTX3_LINK_CLK_SRC 50
+#define DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC 51
+#define DISP_CC_MDSS_DPTX3_LINK_INTF_CLK 52
+#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK 53
+#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC 54
+#define DISP_CC_MDSS_ESC0_CLK 55
+#define DISP_CC_MDSS_ESC0_CLK_SRC 56
+#define DISP_CC_MDSS_ESC1_CLK 57
+#define DISP_CC_MDSS_ESC1_CLK_SRC 58
+#define DISP_CC_MDSS_MDP1_CLK 59
+#define DISP_CC_MDSS_MDP_CLK 60
+#define DISP_CC_MDSS_MDP_CLK_SRC 61
+#define DISP_CC_MDSS_MDP_LUT1_CLK 62
+#define DISP_CC_MDSS_MDP_LUT_CLK 63
+#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 64
+#define DISP_CC_MDSS_PCLK0_CLK 65
+#define DISP_CC_MDSS_PCLK0_CLK_SRC 66
+#define DISP_CC_MDSS_PCLK1_CLK 67
+#define DISP_CC_MDSS_PCLK1_CLK_SRC 68
+#define DISP_CC_MDSS_ROT1_CLK 69
+#define DISP_CC_MDSS_ROT_CLK 70
+#define DISP_CC_MDSS_ROT_CLK_SRC 71
+#define DISP_CC_MDSS_RSCC_AHB_CLK 72
+#define DISP_CC_MDSS_RSCC_VSYNC_CLK 73
+#define DISP_CC_MDSS_VSYNC1_CLK 74
+#define DISP_CC_MDSS_VSYNC_CLK 75
+#define DISP_CC_MDSS_VSYNC_CLK_SRC 76
+#define DISP_CC_SLEEP_CLK 77
+#define DISP_CC_SLEEP_CLK_SRC 78
+#define DISP_CC_XO_CLK 79
+#define DISP_CC_XO_CLK_SRC 80
+
+/* DISPCC resets */
+#define DISP_CC_MDSS_CORE_BCR 0
+#define DISP_CC_MDSS_RSCC_BCR 1
+
+/* DISPCC GDSCs */
+#define MDSS_GDSC 0
+#define MDSS_INT2_GDSC 1
+
+#endif
--
2.35.1
On 11/08/2022 07:12, Bjorn Andersson wrote:
> The Qualcomm SC8280XP platform has two display clock controllers, add a
> binding for these.
>
> Signed-off-by: Bjorn Andersson <[email protected]>
> ---
> .../bindings/clock/qcom,dispcc-sc8280xp.yaml | 98 +++++++++++++++++
> .../dt-bindings/clock/qcom,dispcc-sc8280xp.h | 100 ++++++++++++++++++
> 2 files changed, 198 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/qcom,dispcc-sc8280xp.yaml
> create mode 100644 include/dt-bindings/clock/qcom,dispcc-sc8280xp.h
>
> diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sc8280xp.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sc8280xp.yaml
> new file mode 100644
> index 000000000000..98e5dfd53f76
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sc8280xp.yaml
> @@ -0,0 +1,98 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/qcom,dispcc-sc8280xp.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Display Clock & Reset Controller Binding for SC8280XP
> +
> +maintainers:
> + - Bjorn Andersson <[email protected]>
> +
> +description: |
> + Qualcomm display clock control module which supports the clocks, resets and
> + power domains for the two MDSS instances on SC8280XP.
> +
> + See also:
> + include/dt-bindings/clock/qcom,dispcc-sc8280xp.h
> +
> +properties:
> + compatible:
> + enum:
> + - qcom,sc8280x-dispcc0
> + - qcom,sc8280x-dispcc1
These are two independent and different devices, right? Driver seems to
confirm this which would justify using indexes in compatible.
> +
> + clocks:
> + items:
> + - description: AHB interface clock,
> + - description: SoC CXO clock
> + - description: SoC sleep clock
> + - description: DisplayPort 0 link clock
> + - description: DisplayPort 0 VCO div clock
> + - description: DisplayPort 1 link clock
> + - description: DisplayPort 1 VCO div clock
> + - description: DisplayPort 2 link clock
> + - description: DisplayPort 2 VCO div clock
> + - description: DisplayPort 3 link clock
> + - description: DisplayPort 3 VCO div clock
> + - description: DSI 0 PLL byte clock
> + - description: DSI 0 PLL DSI clock
> + - description: DSI 1 PLL byte clock
> + - description: DSI 1 PLL DSI clock
> +
> + '#clock-cells':
> + const: 1
> +
> + '#reset-cells':
> + const: 1
> +
> + '#power-domain-cells':
> + const: 1
> +
> + reg:
> + maxItems: 1
> +
> + power-domains:
> + description:
> + A phandle and PM domain specifier for the MMCX power domain.
> + maxItems: 1
Three lines can be shorter:
items:
- description: MMCX power domain
With above:
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
On Wed, 10 Aug 2022 21:12:10 -0700, Bjorn Andersson wrote:
> The Qualcomm SC8280XP platform has two display clock controllers, add a
> binding for these.
>
> Signed-off-by: Bjorn Andersson <[email protected]>
> ---
> .../bindings/clock/qcom,dispcc-sc8280xp.yaml | 98 +++++++++++++++++
> .../dt-bindings/clock/qcom,dispcc-sc8280xp.h | 100 ++++++++++++++++++
> 2 files changed, 198 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/qcom,dispcc-sc8280xp.yaml
> create mode 100644 include/dt-bindings/clock/qcom,dispcc-sc8280xp.h
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/clock/qcom,dispcc-sc8280xp.example.dtb:0:0: /example-0/clock-controller@af00000: failed to match any schema with compatible: ['qcom,sc8280xp-dispcc0']
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
On Wed, 10 Aug 2022 21:12:09 -0700, Bjorn Andersson wrote:
> This adds binding and implementation of the SC8280XP display clock controller.
>
> Bjorn Andersson (2):
> dt-bindings: clock: Add Qualcomm SC8280XP display clock bindings
> clk: qcom: Add SC8280XP display clock controller
>
> .../bindings/clock/qcom,dispcc-sc8280xp.yaml | 98 +
> drivers/clk/qcom/Kconfig | 9 +
> drivers/clk/qcom/Makefile | 1 +
> drivers/clk/qcom/dispcc-sc8280xp.c | 3218 +++++++++++++++++
> .../dt-bindings/clock/qcom,dispcc-sc8280xp.h | 100 +
> 5 files changed, 3426 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/qcom,dispcc-sc8280xp.yaml
> create mode 100644 drivers/clk/qcom/dispcc-sc8280xp.c
> create mode 100644 include/dt-bindings/clock/qcom,dispcc-sc8280xp.h
>
> [...]
Applied, thanks!
[1/2] dt-bindings: clock: Add Qualcomm SC8280XP display clock bindings
commit: 73d9c10a96e52aaa2cd19806ac127a3a0e87c410
[2/2] clk: qcom: Add SC8280XP display clock controller
commit: 4a66e76fdb6d0c742ad13db45888c14a9c1ef1a9
Best regards,
--
Bjorn Andersson <[email protected]>