Add compatible for J7200 CPSW5G.
Add support for QSGMII mode in phy-gmii-sel driver for CPSW5G in J7200.
Change log:
v1->v2:
1. Rename ti,enet-ctrl-qsgmii as ti,qsgmii-main-ports.
2. Change ti,qsgmii-main-ports property from bitmask to integer.
3.Update commit message with property name as ti,qsgmii-main-ports.
v1: https://lore.kernel.org/r/[email protected]/
Siddharth Vadapalli (2):
dt-bindings: phy: ti: phy-gmii-sel: Add bindings for J7200
phy: ti: gmii-sel: Add support for CPSW5G GMII SEL in J7200
.../mfd/ti,j721e-system-controller.yaml | 5 +++
.../bindings/phy/ti,phy-gmii-sel.yaml | 27 ++++++++++++-
drivers/phy/ti/phy-gmii-sel.c | 40 +++++++++++++++++--
3 files changed, 68 insertions(+), 4 deletions(-)
--
2.25.1
TI's J7200 SoC supports additional PHY modes like QSGMII and SGMII
that are not supported on earlier SoCs. Add a compatible for it.
Signed-off-by: Siddharth Vadapalli <[email protected]>
---
.../mfd/ti,j721e-system-controller.yaml | 5 ++++
.../bindings/phy/ti,phy-gmii-sel.yaml | 27 ++++++++++++++++++-
2 files changed, 31 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
index 73cffc45e056..527fd47b648b 100644
--- a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
+++ b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
@@ -54,6 +54,11 @@ patternProperties:
description:
Clock provider for TI EHRPWM nodes.
+ "phy@[0-9a-f]+$":
+ type: object
+ description:
+ This is the register to set phy mode through phy-gmii-sel driver.
+
required:
- compatible
- reg
diff --git a/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml b/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml
index ff8a6d9eb153..54da408d0360 100644
--- a/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml
+++ b/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml
@@ -53,12 +53,21 @@ properties:
- ti,am43xx-phy-gmii-sel
- ti,dm814-phy-gmii-sel
- ti,am654-phy-gmii-sel
+ - ti,j7200-cpsw5g-phy-gmii-sel
reg:
maxItems: 1
'#phy-cells': true
+ ti,qsgmii-main-ports:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description: |
+ Required only for QSGMII mode. Array to select the port for
+ QSGMII main mode. Rest of the ports are selected as QSGMII_SUB
+ ports automatically. Any one of the 4 CPSW5G ports can act as the
+ main port with the rest of them being the QSGMII_SUB ports.
+
allOf:
- if:
properties:
@@ -73,6 +82,22 @@ allOf:
'#phy-cells':
const: 1
description: CPSW port number (starting from 1)
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - ti,j7200-cpsw5g-phy-gmii-sel
+ then:
+ properties:
+ '#phy-cells':
+ const: 1
+ description: CPSW port number (starting from 1)
+ ti,qsgmii-main-ports:
+ maxItems: 1
+ items:
+ minimum: 1
+ maximum: 4
- if:
properties:
compatible:
@@ -97,7 +122,7 @@ additionalProperties: false
examples:
- |
- phy_gmii_sel: phy-gmii-sel@650 {
+ phy_gmii_sel: phy@650 {
compatible = "ti,am3352-phy-gmii-sel";
reg = <0x650 0x4>;
#phy-cells = <2>;
--
2.25.1
Each of the CPSW5G ports in J7200 support additional modes like QSGMII.
Add a new compatible for J7200 to support the additional modes.
In TI's J7200, each of the CPSW5G ethernet interfaces can act as a
QSGMII or QSGMII-SUB port. The QSGMII interface is responsible for
performing auto-negotiation between the MAC and the PHY while the rest of
the interfaces are designated as QSGMII-SUB interfaces, indicating that
they will not be taking part in the auto-negotiation process.
To indicate the interface which will serve as the main QSGMII interface,
add a property "ti,qsgmii-main-ports", whose value indicates the
port number of the interface which shall serve as the main QSGMII
interface. The rest of the interfaces are then assigned QSGMII-SUB mode by
default.
Signed-off-by: Siddharth Vadapalli <[email protected]>
---
drivers/phy/ti/phy-gmii-sel.c | 40 ++++++++++++++++++++++++++++++++---
1 file changed, 37 insertions(+), 3 deletions(-)
diff --git a/drivers/phy/ti/phy-gmii-sel.c b/drivers/phy/ti/phy-gmii-sel.c
index d0ab69750c6b..270083606b14 100644
--- a/drivers/phy/ti/phy-gmii-sel.c
+++ b/drivers/phy/ti/phy-gmii-sel.c
@@ -22,6 +22,12 @@
#define AM33XX_GMII_SEL_MODE_RMII 1
#define AM33XX_GMII_SEL_MODE_RGMII 2
+/* J72xx SoC specific definitions for the CONTROL port */
+#define J72XX_GMII_SEL_MODE_QSGMII 4
+#define J72XX_GMII_SEL_MODE_QSGMII_SUB 6
+
+#define PHY_GMII_PORT(n) BIT((n) - 1)
+
enum {
PHY_GMII_SEL_PORT_MODE = 0,
PHY_GMII_SEL_RGMII_ID_MODE,
@@ -43,6 +49,7 @@ struct phy_gmii_sel_soc_data {
u32 features;
const struct reg_field (*regfields)[PHY_GMII_SEL_LAST];
bool use_of_data;
+ u64 extra_modes;
};
struct phy_gmii_sel_priv {
@@ -53,6 +60,7 @@ struct phy_gmii_sel_priv {
struct phy_gmii_sel_phy_priv *if_phys;
u32 num_ports;
u32 reg_offset;
+ u32 qsgmii_main_ports;
};
static int phy_gmii_sel_mode(struct phy *phy, enum phy_mode mode, int submode)
@@ -88,10 +96,17 @@ static int phy_gmii_sel_mode(struct phy *phy, enum phy_mode mode, int submode)
gmii_sel_mode = AM33XX_GMII_SEL_MODE_MII;
break;
+ case PHY_INTERFACE_MODE_QSGMII:
+ if (!(soc_data->extra_modes & BIT(PHY_INTERFACE_MODE_QSGMII)))
+ goto unsupported;
+ if (if_phy->priv->qsgmii_main_ports & BIT(if_phy->id - 1))
+ gmii_sel_mode = J72XX_GMII_SEL_MODE_QSGMII;
+ else
+ gmii_sel_mode = J72XX_GMII_SEL_MODE_QSGMII_SUB;
+ break;
+
default:
- dev_warn(dev, "port%u: unsupported mode: \"%s\"\n",
- if_phy->id, phy_modes(submode));
- return -EINVAL;
+ goto unsupported;
}
if_phy->phy_if_mode = submode;
@@ -123,6 +138,11 @@ static int phy_gmii_sel_mode(struct phy *phy, enum phy_mode mode, int submode)
}
return 0;
+
+unsupported:
+ dev_warn(dev, "port%u: unsupported mode: \"%s\"\n",
+ if_phy->id, phy_modes(submode));
+ return -EINVAL;
}
static const
@@ -188,6 +208,13 @@ struct phy_gmii_sel_soc_data phy_gmii_sel_soc_am654 = {
.regfields = phy_gmii_sel_fields_am654,
};
+static const
+struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw5g_soc_j7200 = {
+ .use_of_data = true,
+ .regfields = phy_gmii_sel_fields_am654,
+ .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII),
+};
+
static const struct of_device_id phy_gmii_sel_id_table[] = {
{
.compatible = "ti,am3352-phy-gmii-sel",
@@ -209,6 +236,10 @@ static const struct of_device_id phy_gmii_sel_id_table[] = {
.compatible = "ti,am654-phy-gmii-sel",
.data = &phy_gmii_sel_soc_am654,
},
+ {
+ .compatible = "ti,j7200-cpsw5g-phy-gmii-sel",
+ .data = &phy_gmii_sel_cpsw5g_soc_j7200,
+ },
{}
};
MODULE_DEVICE_TABLE(of, phy_gmii_sel_id_table);
@@ -350,6 +381,7 @@ static int phy_gmii_sel_probe(struct platform_device *pdev)
struct device_node *node = dev->of_node;
const struct of_device_id *of_id;
struct phy_gmii_sel_priv *priv;
+ u32 main_ports = 1;
int ret;
of_id = of_match_node(phy_gmii_sel_id_table, pdev->dev.of_node);
@@ -363,6 +395,8 @@ static int phy_gmii_sel_probe(struct platform_device *pdev)
priv->dev = &pdev->dev;
priv->soc_data = of_id->data;
priv->num_ports = priv->soc_data->num_ports;
+ of_property_read_u32_array(node, "ti,qsgmii-main-ports", &main_ports, 1);
+ priv->qsgmii_main_ports = PHY_GMII_PORT(main_ports);
priv->regmap = syscon_node_to_regmap(node->parent);
if (IS_ERR(priv->regmap)) {
--
2.25.1
On Tue, Aug 16, 2022 at 11:28:47AM +0530, Siddharth Vadapalli wrote:
> TI's J7200 SoC supports additional PHY modes like QSGMII and SGMII
> that are not supported on earlier SoCs. Add a compatible for it.
>
> Signed-off-by: Siddharth Vadapalli <[email protected]>
> ---
> .../mfd/ti,j721e-system-controller.yaml | 5 ++++
> .../bindings/phy/ti,phy-gmii-sel.yaml | 27 ++++++++++++++++++-
> 2 files changed, 31 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
> index 73cffc45e056..527fd47b648b 100644
> --- a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
> +++ b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
> @@ -54,6 +54,11 @@ patternProperties:
> description:
> Clock provider for TI EHRPWM nodes.
>
> + "phy@[0-9a-f]+$":
> + type: object
> + description:
> + This is the register to set phy mode through phy-gmii-sel driver.
No properties for this node? A whole node for 1 register?
Or this node is ti,phy-gmii-sel.yaml? If so, add a $ref to it.
> +
> required:
> - compatible
> - reg
> diff --git a/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml b/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml
> index ff8a6d9eb153..54da408d0360 100644
> --- a/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml
> +++ b/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml
> @@ -53,12 +53,21 @@ properties:
> - ti,am43xx-phy-gmii-sel
> - ti,dm814-phy-gmii-sel
> - ti,am654-phy-gmii-sel
> + - ti,j7200-cpsw5g-phy-gmii-sel
>
> reg:
> maxItems: 1
>
> '#phy-cells': true
>
> + ti,qsgmii-main-ports:
> + $ref: /schemas/types.yaml#/definitions/uint32-array
> + description: |
> + Required only for QSGMII mode. Array to select the port for
> + QSGMII main mode. Rest of the ports are selected as QSGMII_SUB
> + ports automatically. Any one of the 4 CPSW5G ports can act as the
> + main port with the rest of them being the QSGMII_SUB ports.
Constraints?
> +
> allOf:
> - if:
> properties:
> @@ -73,6 +82,22 @@ allOf:
> '#phy-cells':
> const: 1
> description: CPSW port number (starting from 1)
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - ti,j7200-cpsw5g-phy-gmii-sel
> + then:
> + properties:
> + '#phy-cells':
> + const: 1
> + description: CPSW port number (starting from 1)
> + ti,qsgmii-main-ports:
> + maxItems: 1
An array, but only 1 entry allowed?
> + items:
> + minimum: 1
> + maximum: 4
Can't this be up above?
> - if:
> properties:
> compatible:
> @@ -97,7 +122,7 @@ additionalProperties: false
>
> examples:
> - |
> - phy_gmii_sel: phy-gmii-sel@650 {
> + phy_gmii_sel: phy@650 {
> compatible = "ti,am3352-phy-gmii-sel";
> reg = <0x650 0x4>;
> #phy-cells = <2>;
> --
> 2.25.1
>
Hello Rob,
On 18/08/22 20:13, Rob Herring wrote:
> On Tue, Aug 16, 2022 at 11:28:47AM +0530, Siddharth Vadapalli wrote:
>> TI's J7200 SoC supports additional PHY modes like QSGMII and SGMII
>> that are not supported on earlier SoCs. Add a compatible for it.
>>
>> Signed-off-by: Siddharth Vadapalli <[email protected]>
>> ---
>> .../mfd/ti,j721e-system-controller.yaml | 5 ++++
>> .../bindings/phy/ti,phy-gmii-sel.yaml | 27 ++++++++++++++++++-
>> 2 files changed, 31 insertions(+), 1 deletion(-)
>>
>> diff --git a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
>> index 73cffc45e056..527fd47b648b 100644
>> --- a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
>> +++ b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
>> @@ -54,6 +54,11 @@ patternProperties:
>> description:
>> Clock provider for TI EHRPWM nodes.
>>
>> + "phy@[0-9a-f]+$":
>> + type: object
>> + description:
>> + This is the register to set phy mode through phy-gmii-sel driver.
>
> No properties for this node? A whole node for 1 register?
>
> Or this node is ti,phy-gmii-sel.yaml? If so, add a $ref to it.
Thank you for reviewing the patch. Yes, the node is for
ti,phy-gmii-sel.yaml. I will add the $ref for it.
>
>> +
>> required:
>> - compatible
>> - reg
>> diff --git a/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml b/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml
>> index ff8a6d9eb153..54da408d0360 100644
>> --- a/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml
>> +++ b/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml
>> @@ -53,12 +53,21 @@ properties:
>> - ti,am43xx-phy-gmii-sel
>> - ti,dm814-phy-gmii-sel
>> - ti,am654-phy-gmii-sel
>> + - ti,j7200-cpsw5g-phy-gmii-sel
>>
>> reg:
>> maxItems: 1
>>
>> '#phy-cells': true
>>
>> + ti,qsgmii-main-ports:
>> + $ref: /schemas/types.yaml#/definitions/uint32-array
>> + description: |
>> + Required only for QSGMII mode. Array to select the port for
>> + QSGMII main mode. Rest of the ports are selected as QSGMII_SUB
>> + ports automatically. Any one of the 4 CPSW5G ports can act as the
>> + main port with the rest of them being the QSGMII_SUB ports.
>
> Constraints?
This is an optional property that should only be used for the
ti,j7200-cpsw5g-phy-gmii-sel compatible if it is used. I did not realize
that by defining it here, I had automatically defined it as a valid
property for all the compatibles. I will restrict this property only to
the ti,j7200-cpsw5g-phy-gmii-sel compatible by extending the if-then
statement below, adding an else statement with "ti,qsgmii-main-ports:
false", which will disallow this property for other compatibles.
>
>> +
>> allOf:
>> - if:
>> properties:
>> @@ -73,6 +82,22 @@ allOf:
>> '#phy-cells':
>> const: 1
>> description: CPSW port number (starting from 1)
>> + - if:
>> + properties:
>> + compatible:
>> + contains:
>> + enum:
>> + - ti,j7200-cpsw5g-phy-gmii-sel
>> + then:
>> + properties:
>> + '#phy-cells':
>> + const: 1
>> + description: CPSW port number (starting from 1)
>> + ti,qsgmii-main-ports:
>> + maxItems: 1
>
> An array, but only 1 entry allowed?
For the ti,j7200-cpsw5g-phy-gmii-sel compatible, only one entry is
allowed, but in the future, I will be adding a new compatible which will
require two entries for the ti,qsgmii-main-ports property. On TI's J721e
device, there are a total of 8 external ports, therefore making it
possible to configure them as two sets of QSGMII interfaces. This
requires two qsgmii-main ports which can be specified in the
ti,qsgmii-main-ports property as an array. Therefore, I have declared
the property as an array.
>
>> + items:
>> + minimum: 1
>> + maximum: 4
>
> Can't this be up above?
Yes, I will move it to the top where the ti,qsgmii-main-ports property
is defined.
Regards,
Siddharth.