2022-07-26 06:56:21

by Wei Fang

Subject: [PATCH V4 3/3] arm64: dts: imx8ulp-evk: Add the fec support

From: Wei Fang <[email protected]>

Enable the fec on i.MX8ULP EVK board.

Signed-off-by: Wei Fang <[email protected]>
---
V2 change:
Add clock_ext_rmii and clock_ext_ts. They are both related to EVK board.
V3 change:
No change.
V4 change:
Add ethernet-phy address "@1".
---
arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 57 +++++++++++++++++++
1 file changed, 57 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
index 33e84c4e9ed8..f1c6d933a17c 100644
--- a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
@@ -19,6 +19,21 @@ memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0 0x80000000>;
};
+
+ clock_ext_rmii: clock-ext-rmii {
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+ clock-output-names = "ext_rmii_clk";
+ #clock-cells = <0>;
+ };
+
+ clock_ext_ts: clock-ext-ts {
+ compatible = "fixed-clock";
+ /* External ts clock is 50MHZ from PHY on EVK board. */
+ clock-frequency = <50000000>;
+ clock-output-names = "ext_ts_clk";
+ #clock-cells = <0>;
+ };
};

&lpuart5 {
@@ -38,7 +53,49 @@ &usdhc0 {
status = "okay";
};

+&fec {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pinctrl_enet>;
+ pinctrl-1 = <&pinctrl_enet>;
+ clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
+ <&pcc4 IMX8ULP_CLK_ENET>,
+ <&cgc1 IMX8ULP_CLK_ENET_TS_SEL>,
+ <&clock_ext_rmii>;
+ clock-names = "ipg", "ahb", "ptp", "enet_clk_ref";
+ assigned-clocks = <&cgc1 IMX8ULP_CLK_ENET_TS_SEL>;
+ assigned-clock-parents = <&clock_ext_ts>;
+ phy-mode = "rmii";
+ phy-handle = <&ethphy>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy: ethernet-phy@1 {
+ reg = <1>;
+ micrel,led-mode = <1>;
+ };
+ };
+};
+
&iomuxc1 {
+ pinctrl_enet: enetgrp {
+ fsl,pins = <
+ MX8ULP_PAD_PTE15__ENET0_MDC 0x43
+ MX8ULP_PAD_PTE14__ENET0_MDIO 0x43
+ MX8ULP_PAD_PTE17__ENET0_RXER 0x43
+ MX8ULP_PAD_PTE18__ENET0_CRS_DV 0x43
+ MX8ULP_PAD_PTF1__ENET0_RXD0 0x43
+ MX8ULP_PAD_PTE20__ENET0_RXD1 0x43
+ MX8ULP_PAD_PTE16__ENET0_TXEN 0x43
+ MX8ULP_PAD_PTE23__ENET0_TXD0 0x43
+ MX8ULP_PAD_PTE22__ENET0_TXD1 0x43
+ MX8ULP_PAD_PTE19__ENET0_REFCLK 0x43
+ MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x43
+ >;
+ };
+
pinctrl_lpuart5: lpuart5grp {
fsl,pins = <
MX8ULP_PAD_PTF14__LPUART5_TX 0x3
--
2.25.1

2022-08-01 04:23:28

by Wei Fang

Subject: RE: [PATCH V4 3/3] arm64: dts: imx8ulp-evk: Add the fec support

Hi
Kindly Ping.

> -----Original Message-----
> From: Wei Fang
> Sent: 2022??7??26?? 14:46
> To: [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]
> Cc: [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> dl-linux-imx <[email protected]>; Peng Fan <[email protected]>; Jacky Bai
> <[email protected]>; [email protected];
> [email protected]; Aisheng Dong <[email protected]>
> Subject: [PATCH V4 3/3] arm64: dts: imx8ulp-evk: Add the fec support
>
> From: Wei Fang <[email protected]>
>
> Enable the fec on i.MX8ULP EVK board.
>
> Signed-off-by: Wei Fang <[email protected]>
> ---
> V2 change:
> Add clock_ext_rmii and clock_ext_ts. They are both related to EVK board.
> V3 change:
> No change.
> V4 change:
> Add ethernet-phy address "@1".
> ---
> arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 57
> +++++++++++++++++++
> 1 file changed, 57 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
> b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
> index 33e84c4e9ed8..f1c6d933a17c 100644
> --- a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
> @@ -19,6 +19,21 @@ memory@80000000 {
> device_type = "memory";
> reg = <0x0 0x80000000 0 0x80000000>;
> };
> +
> + clock_ext_rmii: clock-ext-rmii {
> + compatible = "fixed-clock";
> + clock-frequency = <50000000>;
> + clock-output-names = "ext_rmii_clk";
> + #clock-cells = <0>;
> + };
> +
> + clock_ext_ts: clock-ext-ts {
> + compatible = "fixed-clock";
> + /* External ts clock is 50MHZ from PHY on EVK board. */
> + clock-frequency = <50000000>;
> + clock-output-names = "ext_ts_clk";
> + #clock-cells = <0>;
> + };
> };
>
> &lpuart5 {
> @@ -38,7 +53,49 @@ &usdhc0 {
> status = "okay";
> };
>
> +&fec {
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <&pinctrl_enet>;
> + pinctrl-1 = <&pinctrl_enet>;
> + clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
> + <&pcc4 IMX8ULP_CLK_ENET>,
> + <&cgc1 IMX8ULP_CLK_ENET_TS_SEL>,
> + <&clock_ext_rmii>;
> + clock-names = "ipg", "ahb", "ptp", "enet_clk_ref";
> + assigned-clocks = <&cgc1 IMX8ULP_CLK_ENET_TS_SEL>;
> + assigned-clock-parents = <&clock_ext_ts>;
> + phy-mode = "rmii";
> + phy-handle = <&ethphy>;
> + status = "okay";
> +
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + ethphy: ethernet-phy@1 {
> + reg = <1>;
> + micrel,led-mode = <1>;
> + };
> + };
> +};
> +
> &iomuxc1 {
> + pinctrl_enet: enetgrp {
> + fsl,pins = <
> + MX8ULP_PAD_PTE15__ENET0_MDC 0x43
> + MX8ULP_PAD_PTE14__ENET0_MDIO 0x43
> + MX8ULP_PAD_PTE17__ENET0_RXER 0x43
> + MX8ULP_PAD_PTE18__ENET0_CRS_DV 0x43
> + MX8ULP_PAD_PTF1__ENET0_RXD0 0x43
> + MX8ULP_PAD_PTE20__ENET0_RXD1 0x43
> + MX8ULP_PAD_PTE16__ENET0_TXEN 0x43
> + MX8ULP_PAD_PTE23__ENET0_TXD0 0x43
> + MX8ULP_PAD_PTE22__ENET0_TXD1 0x43
> + MX8ULP_PAD_PTE19__ENET0_REFCLK 0x43
> + MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x43
> + >;
> + };
> +
> pinctrl_lpuart5: lpuart5grp {
> fsl,pins = <
> MX8ULP_PAD_PTF14__LPUART5_TX 0x3
> --
> 2.25.1

2022-08-21 03:06:32

by Shawn Guo

Subject: Re: [PATCH V4 3/3] arm64: dts: imx8ulp-evk: Add the fec support

On Wed, Jul 27, 2022 at 12:38:53AM +1000, [email protected] wrote:
> From: Wei Fang <[email protected]>
>
> Enable the fec on i.MX8ULP EVK board.
>
> Signed-off-by: Wei Fang <[email protected]>

Applied, thanks!