P1021RDB Combo Board CPLD Design is used on following Freescale boards:
P1021RDB-PC, P1020RDB-PD, P1020MBG-PC, P1020UTM-PC and P2020RDB-PCA.
Add CPLD definitions for all these boards for which already exist DTS file.
CPLD has bank size 128kB, it is connected via CS3 on LBC and mapped to
memory range 0xFFA00000~0xFFA1FFFF.
As CPLD firmware is common on all these boards, use just one compatible
string "fsl,p1021rdb-pc-cpld".
In some DTS files is CPLD already defined, but definition is either
incomplete or wrong. So fix it.
All these boards have via CPLD connected max6370 watchdog at offset 0x2
with GPIO 11, status led at offset 0x8 and reset controller at offset 0xd.
Additionally P1020MBG-PC and P1020RDB-PD boards have FXO led at offset 0x9
and FXS leds at offset 0xa.
Signed-off-by: Pali Rohár <[email protected]>
---
arch/powerpc/boot/dts/fsl/p1020mbg-pc.dtsi | 92 +++++++++++++++++++
arch/powerpc/boot/dts/fsl/p1020mbg-pc_32b.dts | 6 +-
arch/powerpc/boot/dts/fsl/p1020mbg-pc_36b.dts | 6 +-
arch/powerpc/boot/dts/fsl/p1020rdb-pd.dts | 44 +++++++--
arch/powerpc/boot/dts/fsl/p1020utm-pc.dtsi | 37 ++++++++
arch/powerpc/boot/dts/fsl/p1020utm-pc_32b.dts | 4 +-
arch/powerpc/boot/dts/fsl/p1020utm-pc_36b.dts | 4 +-
arch/powerpc/boot/dts/fsl/p1021rdb-pc.dtsi | 37 ++++++++
arch/powerpc/boot/dts/fsl/p1021rdb-pc_32b.dts | 5 +-
arch/powerpc/boot/dts/fsl/p1021rdb-pc_36b.dts | 5 +-
arch/powerpc/boot/dts/fsl/p2020rdb-pc.dtsi | 33 ++++++-
11 files changed, 251 insertions(+), 22 deletions(-)
diff --git a/arch/powerpc/boot/dts/fsl/p1020mbg-pc.dtsi b/arch/powerpc/boot/dts/fsl/p1020mbg-pc.dtsi
index a24699cfea9c..c73996dcd809 100644
--- a/arch/powerpc/boot/dts/fsl/p1020mbg-pc.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p1020mbg-pc.dtsi
@@ -83,6 +83,95 @@
compatible = "vitesse-7385";
reg = <0x2 0x0 0x20000>;
};
+
+ cpld@3,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,p1021rdb-pc-cpld", "simple-bus", "syscon";
+ reg = <0x3 0x0 0x20000>;
+ ranges = <0x0 0x3 0x0 0x20000>;
+
+ watchdog@2 {
+ compatible = "maxim,max6370";
+ reg = <0x2 0x1>;
+ gpios = <&gpio 11 1>;
+ };
+
+ led@8 {
+ compatible = "register-bit-led";
+ reg = <0x8 0x1>;
+ offset = <0x8>;
+ mask = <0x1>;
+ active-low;
+ default-state = "keep";
+ label = "status";
+ function = "status";
+ color = <6>; /* LED_COLOR_ID_YELLOW */
+ };
+
+ led@9 {
+ compatible = "register-bit-led";
+ reg = <0x9 0x1>;
+ offset = <0x9>;
+ mask = <0x1>;
+ active-low;
+ default-state = "keep";
+ label = "fxo";
+ color = <2>; /* LED_COLOR_ID_GREEN */
+ };
+
+ led@a,0 {
+ compatible = "register-bit-led";
+ reg = <0xa 0x1>;
+ offset = <0xa>;
+ mask = <0x1>;
+ active-low;
+ default-state = "keep";
+ label = "fxs0";
+ color = <2>; /* LED_COLOR_ID_GREEN */
+ };
+
+ led@a,1 {
+ compatible = "register-bit-led";
+ reg = <0xa 0x1>;
+ offset = <0xa>;
+ mask = <0x2>;
+ active-low;
+ default-state = "keep";
+ label = "fxs1";
+ color = <2>; /* LED_COLOR_ID_GREEN */
+ };
+
+ led@a,2 {
+ compatible = "register-bit-led";
+ reg = <0xa 0x1>;
+ offset = <0xa>;
+ mask = <0x4>;
+ active-low;
+ default-state = "keep";
+ label = "fxs2";
+ color = <2>; /* LED_COLOR_ID_GREEN */
+ };
+
+ led@a,3 {
+ compatible = "register-bit-led";
+ reg = <0xa 0x1>;
+ offset = <0xa>;
+ mask = <0x8>;
+ active-low;
+ default-state = "keep";
+ label = "fxs3";
+ color = <2>; /* LED_COLOR_ID_GREEN */
+ };
+
+ reboot@d {
+ compatible = "syscon-reboot";
+ reg = <0xd 0x1>;
+ offset = <0xd>;
+ mask = <0x1>;
+ value = <0x1>;
+ };
+ };
};
&soc {
@@ -93,6 +182,9 @@
};
};
+ gpio: gpio-controller@fc00 {
+ };
+
mdio@24000 {
phy0: ethernet-phy@0 {
interrupts = <3 1 0 0>;
diff --git a/arch/powerpc/boot/dts/fsl/p1020mbg-pc_32b.dts b/arch/powerpc/boot/dts/fsl/p1020mbg-pc_32b.dts
index b29d1fcb5e6b..29847d395f1f 100644
--- a/arch/powerpc/boot/dts/fsl/p1020mbg-pc_32b.dts
+++ b/arch/powerpc/boot/dts/fsl/p1020mbg-pc_32b.dts
@@ -44,10 +44,10 @@
lbc: localbus@ffe05000 {
reg = <0x0 0xffe05000 0x0 0x1000>;
- /* NOR and L2 switch */
+ /* NOR, L2 switch and CPLD */
ranges = <0x0 0x0 0x0 0xec000000 0x04000000
- 0x1 0x0 0x0 0xffa00000 0x00040000
- 0x2 0x0 0x0 0xffb00000 0x00020000>;
+ 0x2 0x0 0x0 0xffb00000 0x00020000
+ 0x3 0x0 0x0 0xffa00000 0x00040000>;
};
soc: soc@ffe00000 {
diff --git a/arch/powerpc/boot/dts/fsl/p1020mbg-pc_36b.dts b/arch/powerpc/boot/dts/fsl/p1020mbg-pc_36b.dts
index 678d0eec24e2..b0ce561c38ff 100644
--- a/arch/powerpc/boot/dts/fsl/p1020mbg-pc_36b.dts
+++ b/arch/powerpc/boot/dts/fsl/p1020mbg-pc_36b.dts
@@ -44,10 +44,10 @@
lbc: localbus@fffe05000 {
reg = <0xf 0xffe05000 0x0 0x1000>;
- /* NOR and L2 switch */
+ /* NOR, L2 switch and CPLD */
ranges = <0x0 0x0 0xf 0xec000000 0x04000000
- 0x1 0x0 0xf 0xffa00000 0x00040000
- 0x2 0x0 0xf 0xffb00000 0x00020000>;
+ 0x2 0x0 0xf 0xffb00000 0x00020000
+ 0x3 0x0 0xf 0xffa00000 0x00040000>;
};
soc: soc@fffe00000 {
diff --git a/arch/powerpc/boot/dts/fsl/p1020rdb-pd.dts b/arch/powerpc/boot/dts/fsl/p1020rdb-pd.dts
index f2dc6c09be52..1c44a1690065 100644
--- a/arch/powerpc/boot/dts/fsl/p1020rdb-pd.dts
+++ b/arch/powerpc/boot/dts/fsl/p1020rdb-pd.dts
@@ -47,8 +47,8 @@
/* NOR, NAND flash, L2 switch and CPLD */
ranges = <0x0 0x0 0x0 0xec000000 0x04000000
0x1 0x0 0x0 0xff800000 0x00040000
- 0x2 0x0 0x0 0xffa00000 0x00020000
- 0x3 0x0 0x0 0xffb00000 0x00020000>;
+ 0x2 0x0 0x0 0xffb00000 0x00020000
+ 0x3 0x0 0x0 0xffa00000 0x00020000>;
nor@0,0 {
#address-cells = <1>;
@@ -128,16 +128,45 @@
};
};
- cpld@2,0 {
- compatible = "fsl,p1020rdb-pd-cpld";
+ L2switch@2,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "vitesse-7385";
reg = <0x2 0x0 0x20000>;
};
- L2switch@3,0 {
+ cpld@3,0 {
#address-cells = <1>;
#size-cells = <1>;
- compatible = "vitesse-7385";
+ compatible = "fsl,p1021rdb-pc-cpld", "simple-bus", "syscon";
reg = <0x3 0x0 0x20000>;
+ ranges = <0x0 0x3 0x0 0x20000>;
+
+ watchdog@2 {
+ compatible = "maxim,max6370";
+ reg = <0x2 0x1>;
+ gpios = <&gpio 11 1>;
+ };
+
+ led@8 {
+ compatible = "register-bit-led";
+ reg = <0x8 0x1>;
+ offset = <0x8>;
+ mask = <0x1>;
+ active-low;
+ default-state = "keep";
+ label = "status";
+ function = "status";
+ color = <6>; /* LED_COLOR_ID_YELLOW */
+ };
+
+ reboot@d {
+ compatible = "syscon-reboot";
+ reg = <0xd 0x1>;
+ offset = <0xd>;
+ mask = <0x1>;
+ value = <0x1>;
+ };
};
};
@@ -199,6 +228,9 @@
};
};
+ gpio: gpio-controller@fc00 {
+ };
+
mdio@24000 {
phy0: ethernet-phy@0 {
interrupts = <3 1 0 0>;
diff --git a/arch/powerpc/boot/dts/fsl/p1020utm-pc.dtsi b/arch/powerpc/boot/dts/fsl/p1020utm-pc.dtsi
index 7ea85eabcc5c..070296d96aac 100644
--- a/arch/powerpc/boot/dts/fsl/p1020utm-pc.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p1020utm-pc.dtsi
@@ -68,6 +68,40 @@
read-only;
};
};
+
+ cpld@3,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,p1021rdb-pc-cpld", "simple-bus", "syscon";
+ reg = <0x3 0x0 0x20000>;
+ ranges = <0x0 0x3 0x0 0x20000>;
+
+ watchdog@2 {
+ compatible = "maxim,max6370";
+ reg = <0x2 0x1>;
+ gpios = <&gpio 11 1>;
+ };
+
+ led@8 {
+ compatible = "register-bit-led";
+ reg = <0x8 0x1>;
+ offset = <0x8>;
+ mask = <0x1>;
+ active-low;
+ default-state = "keep";
+ label = "status";
+ function = "status";
+ color = <6>; /* LED_COLOR_ID_YELLOW */
+ };
+
+ reboot@d {
+ compatible = "syscon-reboot";
+ reg = <0xd 0x1>;
+ offset = <0xd>;
+ mask = <0x1>;
+ value = <0x1>;
+ };
+ };
};
&soc {
@@ -78,6 +112,9 @@
};
};
+ gpio: gpio-controller@fc00 {
+ };
+
mdio@24000 {
phy0: ethernet-phy@0 {
interrupts = <3 1 0 0>;
diff --git a/arch/powerpc/boot/dts/fsl/p1020utm-pc_32b.dts b/arch/powerpc/boot/dts/fsl/p1020utm-pc_32b.dts
index bc03ef611f98..9cc8f6726ca7 100644
--- a/arch/powerpc/boot/dts/fsl/p1020utm-pc_32b.dts
+++ b/arch/powerpc/boot/dts/fsl/p1020utm-pc_32b.dts
@@ -46,8 +46,8 @@
/* NOR */
ranges = <0x0 0x0 0x0 0xec000000 0x02000000
- 0x1 0x0 0x0 0xffa00000 0x00040000
- 0x2 0x0 0x0 0xffb00000 0x00020000>;
+ 0x2 0x0 0x0 0xffb00000 0x00020000
+ 0x3 0x0 0x0 0xffa00000 0x00040000>;
};
soc: soc@ffe00000 {
diff --git a/arch/powerpc/boot/dts/fsl/p1020utm-pc_36b.dts b/arch/powerpc/boot/dts/fsl/p1020utm-pc_36b.dts
index 32766f6a475e..d60fb898399f 100644
--- a/arch/powerpc/boot/dts/fsl/p1020utm-pc_36b.dts
+++ b/arch/powerpc/boot/dts/fsl/p1020utm-pc_36b.dts
@@ -46,8 +46,8 @@
/* NOR */
ranges = <0x0 0x0 0xf 0xec000000 0x02000000
- 0x1 0x0 0xf 0xffa00000 0x00040000
- 0x2 0x0 0xf 0xffb00000 0x00020000>;
+ 0x2 0x0 0xf 0xffb00000 0x00020000
+ 0x3 0x0 0xf 0xffa00000 0x00040000>;
};
soc: soc@fffe00000 {
diff --git a/arch/powerpc/boot/dts/fsl/p1021rdb-pc.dtsi b/arch/powerpc/boot/dts/fsl/p1021rdb-pc.dtsi
index 18f9b31602d0..e2c56ee01039 100644
--- a/arch/powerpc/boot/dts/fsl/p1021rdb-pc.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p1021rdb-pc.dtsi
@@ -136,6 +136,40 @@
compatible = "vitesse-7385";
reg = <0x2 0x0 0x20000>;
};
+
+ cpld@3,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,p1021rdb-pc-cpld", "simple-bus", "syscon";
+ reg = <0x3 0x0 0x20000>;
+ ranges = <0x0 0x3 0x0 0x20000>;
+
+ watchdog@2 {
+ compatible = "maxim,max6370";
+ reg = <0x2 0x1>;
+ gpios = <&gpio 11 1>;
+ };
+
+ led@8 {
+ compatible = "register-bit-led";
+ reg = <0x8 0x1>;
+ offset = <0x8>;
+ mask = <0x1>;
+ active-low;
+ default-state = "keep";
+ label = "status";
+ function = "status";
+ color = <6>; /* LED_COLOR_ID_YELLOW */
+ };
+
+ reboot@d {
+ compatible = "syscon-reboot";
+ reg = <0xd 0x1>;
+ offset = <0xd>;
+ mask = <0x1>;
+ value = <0x1>;
+ };
+ };
};
&soc {
@@ -187,6 +221,9 @@
};
};
+ gpio: gpio-controller@fc00 {
+ };
+
usb@22000 {
phy_type = "ulpi";
};
diff --git a/arch/powerpc/boot/dts/fsl/p1021rdb-pc_32b.dts b/arch/powerpc/boot/dts/fsl/p1021rdb-pc_32b.dts
index d2b4710357ac..9721e5ecc86b 100644
--- a/arch/powerpc/boot/dts/fsl/p1021rdb-pc_32b.dts
+++ b/arch/powerpc/boot/dts/fsl/p1021rdb-pc_32b.dts
@@ -44,10 +44,11 @@
lbc: localbus@ffe05000 {
reg = <0 0xffe05000 0 0x1000>;
- /* NOR, NAND Flashes and Vitesse 5 port L2 switch */
+ /* NOR, NAND Flashes, Vitesse 5 port L2 switch and CPLD */
ranges = <0x0 0x0 0x0 0xef000000 0x01000000
0x1 0x0 0x0 0xff800000 0x00040000
- 0x2 0x0 0x0 0xffb00000 0x00020000>;
+ 0x2 0x0 0x0 0xffb00000 0x00020000
+ 0x3 0x0 0x0 0xffa00000 0x00020000>;
};
soc: soc@ffe00000 {
diff --git a/arch/powerpc/boot/dts/fsl/p1021rdb-pc_36b.dts b/arch/powerpc/boot/dts/fsl/p1021rdb-pc_36b.dts
index e298c29e5606..edea14e5d806 100644
--- a/arch/powerpc/boot/dts/fsl/p1021rdb-pc_36b.dts
+++ b/arch/powerpc/boot/dts/fsl/p1021rdb-pc_36b.dts
@@ -44,10 +44,11 @@
lbc: localbus@fffe05000 {
reg = <0xf 0xffe05000 0 0x1000>;
- /* NOR, NAND Flashes and Vitesse 5 port L2 switch */
+ /* NOR, NAND Flashes, Vitesse 5 port L2 switch and CPLD */
ranges = <0x0 0x0 0xf 0xef000000 0x01000000
0x1 0x0 0xf 0xff800000 0x00040000
- 0x2 0x0 0xf 0xffb00000 0x00020000>;
+ 0x2 0x0 0xf 0xffb00000 0x00020000
+ 0x3 0x0 0xf 0xffa00000 0x00020000>;
};
soc: soc@fffe00000 {
diff --git a/arch/powerpc/boot/dts/fsl/p2020rdb-pc.dtsi b/arch/powerpc/boot/dts/fsl/p2020rdb-pc.dtsi
index 03c9afc82436..0be63fa76422 100644
--- a/arch/powerpc/boot/dts/fsl/p2020rdb-pc.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p2020rdb-pc.dtsi
@@ -133,9 +133,35 @@
cpld@3,0 {
#address-cells = <1>;
#size-cells = <1>;
- compatible = "cpld";
+ compatible = "fsl,p1021rdb-pc-cpld", "simple-bus", "syscon";
reg = <0x3 0x0 0x20000>;
- read-only;
+ ranges = <0x0 0x3 0x0 0x20000>;
+
+ watchdog@2 {
+ compatible = "maxim,max6370";
+ reg = <0x2 0x1>;
+ gpios = <&gpio 11 1>;
+ };
+
+ led@8 {
+ compatible = "register-bit-led";
+ reg = <0x8 0x1>;
+ offset = <0x8>;
+ mask = <0x1>;
+ active-low;
+ default-state = "keep";
+ label = "status";
+ function = "status";
+ color = <6>; /* LED_COLOR_ID_YELLOW */
+ };
+
+ reboot@d {
+ compatible = "syscon-reboot";
+ reg = <0xd 0x1>;
+ offset = <0xd>;
+ mask = <0x1>;
+ value = <0x1>;
+ };
};
};
@@ -188,6 +214,9 @@
};
};
+ gpio: gpio-controller@fc00 {
+ };
+
usb@22000 {
phy_type = "ulpi";
};
--
2.20.1
On Fri, Aug 19, 2022 at 10:44:33AM +0200, Pali Roh?r wrote:
> P1021RDB Combo Board CPLD Design is used on following Freescale boards:
> P1021RDB-PC, P1020RDB-PD, P1020MBG-PC, P1020UTM-PC and P2020RDB-PCA.
>
> Add CPLD definitions for all these boards for which already exist DTS file.
>
> CPLD has bank size 128kB, it is connected via CS3 on LBC and mapped to
> memory range 0xFFA00000~0xFFA1FFFF.
>
> As CPLD firmware is common on all these boards, use just one compatible
> string "fsl,p1021rdb-pc-cpld".
>
> In some DTS files is CPLD already defined, but definition is either
> incomplete or wrong. So fix it.
>
> All these boards have via CPLD connected max6370 watchdog at offset 0x2
> with GPIO 11, status led at offset 0x8 and reset controller at offset 0xd.
> Additionally P1020MBG-PC and P1020RDB-PD boards have FXO led at offset 0x9
> and FXS leds at offset 0xa.
>
> Signed-off-by: Pali Roh?r <[email protected]>
> ---
> arch/powerpc/boot/dts/fsl/p1020mbg-pc.dtsi | 92 +++++++++++++++++++
> arch/powerpc/boot/dts/fsl/p1020mbg-pc_32b.dts | 6 +-
> arch/powerpc/boot/dts/fsl/p1020mbg-pc_36b.dts | 6 +-
> arch/powerpc/boot/dts/fsl/p1020rdb-pd.dts | 44 +++++++--
> arch/powerpc/boot/dts/fsl/p1020utm-pc.dtsi | 37 ++++++++
> arch/powerpc/boot/dts/fsl/p1020utm-pc_32b.dts | 4 +-
> arch/powerpc/boot/dts/fsl/p1020utm-pc_36b.dts | 4 +-
> arch/powerpc/boot/dts/fsl/p1021rdb-pc.dtsi | 37 ++++++++
> arch/powerpc/boot/dts/fsl/p1021rdb-pc_32b.dts | 5 +-
> arch/powerpc/boot/dts/fsl/p1021rdb-pc_36b.dts | 5 +-
> arch/powerpc/boot/dts/fsl/p2020rdb-pc.dtsi | 33 ++++++-
> 11 files changed, 251 insertions(+), 22 deletions(-)
>
> diff --git a/arch/powerpc/boot/dts/fsl/p1020mbg-pc.dtsi b/arch/powerpc/boot/dts/fsl/p1020mbg-pc.dtsi
> index a24699cfea9c..c73996dcd809 100644
> --- a/arch/powerpc/boot/dts/fsl/p1020mbg-pc.dtsi
> +++ b/arch/powerpc/boot/dts/fsl/p1020mbg-pc.dtsi
> @@ -83,6 +83,95 @@
> compatible = "vitesse-7385";
> reg = <0x2 0x0 0x20000>;
> };
> +
> + cpld@3,0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "fsl,p1021rdb-pc-cpld", "simple-bus", "syscon";
> + reg = <0x3 0x0 0x20000>;
> + ranges = <0x0 0x3 0x0 0x20000>;
> +
> + watchdog@2 {
> + compatible = "maxim,max6370";
> + reg = <0x2 0x1>;
> + gpios = <&gpio 11 1>;
> + };
> +
> + led@8 {
The register-bit-led schema says this should be 'led@8,0'. Did you
run 'dtbs_check'?
But that's going to conflict with what simple-bus schema says. I don't
know that 'simple-bus' is really appropriate here. The CPLD isn't really
just a bus. 'simple-mfd' is what's more commonly used with 'syscon'.
> + compatible = "register-bit-led";
> + reg = <0x8 0x1>;
> + offset = <0x8>;
> + mask = <0x1>;
> + active-low;
> + default-state = "keep";
> + label = "status";
> + function = "status";
> + color = <6>; /* LED_COLOR_ID_YELLOW */
> + };
On Monday 22 August 2022 12:00:56 Rob Herring wrote:
> On Fri, Aug 19, 2022 at 10:44:33AM +0200, Pali Rohár wrote:
> > P1021RDB Combo Board CPLD Design is used on following Freescale boards:
> > P1021RDB-PC, P1020RDB-PD, P1020MBG-PC, P1020UTM-PC and P2020RDB-PCA.
> >
> > Add CPLD definitions for all these boards for which already exist DTS file.
> >
> > CPLD has bank size 128kB, it is connected via CS3 on LBC and mapped to
> > memory range 0xFFA00000~0xFFA1FFFF.
> >
> > As CPLD firmware is common on all these boards, use just one compatible
> > string "fsl,p1021rdb-pc-cpld".
> >
> > In some DTS files is CPLD already defined, but definition is either
> > incomplete or wrong. So fix it.
> >
> > All these boards have via CPLD connected max6370 watchdog at offset 0x2
> > with GPIO 11, status led at offset 0x8 and reset controller at offset 0xd.
> > Additionally P1020MBG-PC and P1020RDB-PD boards have FXO led at offset 0x9
> > and FXS leds at offset 0xa.
> >
> > Signed-off-by: Pali Rohár <[email protected]>
> > ---
> > arch/powerpc/boot/dts/fsl/p1020mbg-pc.dtsi | 92 +++++++++++++++++++
> > arch/powerpc/boot/dts/fsl/p1020mbg-pc_32b.dts | 6 +-
> > arch/powerpc/boot/dts/fsl/p1020mbg-pc_36b.dts | 6 +-
> > arch/powerpc/boot/dts/fsl/p1020rdb-pd.dts | 44 +++++++--
> > arch/powerpc/boot/dts/fsl/p1020utm-pc.dtsi | 37 ++++++++
> > arch/powerpc/boot/dts/fsl/p1020utm-pc_32b.dts | 4 +-
> > arch/powerpc/boot/dts/fsl/p1020utm-pc_36b.dts | 4 +-
> > arch/powerpc/boot/dts/fsl/p1021rdb-pc.dtsi | 37 ++++++++
> > arch/powerpc/boot/dts/fsl/p1021rdb-pc_32b.dts | 5 +-
> > arch/powerpc/boot/dts/fsl/p1021rdb-pc_36b.dts | 5 +-
> > arch/powerpc/boot/dts/fsl/p2020rdb-pc.dtsi | 33 ++++++-
> > 11 files changed, 251 insertions(+), 22 deletions(-)
> >
> > diff --git a/arch/powerpc/boot/dts/fsl/p1020mbg-pc.dtsi b/arch/powerpc/boot/dts/fsl/p1020mbg-pc.dtsi
> > index a24699cfea9c..c73996dcd809 100644
> > --- a/arch/powerpc/boot/dts/fsl/p1020mbg-pc.dtsi
> > +++ b/arch/powerpc/boot/dts/fsl/p1020mbg-pc.dtsi
> > @@ -83,6 +83,95 @@
> > compatible = "vitesse-7385";
> > reg = <0x2 0x0 0x20000>;
> > };
> > +
> > + cpld@3,0 {
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + compatible = "fsl,p1021rdb-pc-cpld", "simple-bus", "syscon";
> > + reg = <0x3 0x0 0x20000>;
> > + ranges = <0x0 0x3 0x0 0x20000>;
> > +
> > + watchdog@2 {
> > + compatible = "maxim,max6370";
> > + reg = <0x2 0x1>;
> > + gpios = <&gpio 11 1>;
> > + };
> > +
> > + led@8 {
>
> The register-bit-led schema says this should be 'led@8,0'. Did you
> run 'dtbs_check'?
No, it does not work and I lost interest to trying setup machine for it again.
> But that's going to conflict with what simple-bus schema says.
Another reason why not try it again. Lot of schemas says that are in
conflict, nobody understand it and when I ask how to do it, I just get
silence or answer which does not work on the real hw. And if there is
some schema error message then it looks like it was generated by random
word generator.
> I don't
> know that 'simple-bus' is really appropriate here. The CPLD isn't really
> just a bus. 'simple-mfd' is what's more commonly used with 'syscon'.
Sorry, I do not understand those schemas anymore. And based on previous
failures, I'm not going to try it again.
It is a _bus_ and it was tested that it works as a bus with more
existing drivers.
> > + compatible = "register-bit-led";
> > + reg = <0x8 0x1>;
> > + offset = <0x8>;
> > + mask = <0x1>;
> > + active-low;
> > + default-state = "keep";
> > + label = "status";
> > + function = "status";
> > + color = <6>; /* LED_COLOR_ID_YELLOW */
> > + };
>