This is a backport of commit 34fc9cc3aebe to v5.15.
The "PolarFire SoC MSS Technical Reference Manual" documents the
following PLIC interrupts:
1 - L2 Cache Controller Signals when a metadata correction event occurs
2 - L2 Cache Controller Signals when an uncorrectable metadata event occurs
3 - L2 Cache Controller Signals when a data correction event occurs
4 - L2 Cache Controller Signals when an uncorrectable data event occurs
This differs from the SiFive FU540 which only has three L2 cache related
interrupts.
The sequence in the device tree is defined by an enum:
enum {
DIR_CORR = 0,
DATA_CORR,
DATA_UNCORR,
DIR_UNCORR,
};
So the correct sequence of the L2 cache interrupts is
interrupts = <1>, <3>, <4>, <2>;
This manifests as an unusable system if the l2-cache driver is enabled,
as the wrong interrupt gets cleared & the handler prints errors to the
console ad infinitum.
Fixes: 0fa6107eca41 ("RISC-V: Initial DTS for Microchip ICICLE board")
CC: [email protected] # 5.15: e35b07a7df9b: riscv: dts: microchip: mpfs: Group tuples in interrupt properties
Link: https://lore.kernel.org/all/[email protected]/
Signed-off-by: Heinrich Schuchardt <[email protected]>
---
arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
index 4ef4bcb74872..57989b2ac186 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
@@ -153,7 +153,7 @@ cache-controller@2010000 {
cache-size = <2097152>;
cache-unified;
interrupt-parent = <&plic>;
- interrupts = <1 2 3>;
+ interrupts = <1>, <3>, <4>, <2>;
reg = <0x0 0x2010000 0x0 0x1000>;
};
--
2.37.2
On 29/08/2022 10:10, Heinrich Schuchardt wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> This is a backport of commit 34fc9cc3aebe to v5.15.
>
> The "PolarFire SoC MSS Technical Reference Manual" documents the
> following PLIC interrupts:
>
> 1 - L2 Cache Controller Signals when a metadata correction event occurs
> 2 - L2 Cache Controller Signals when an uncorrectable metadata event occurs
> 3 - L2 Cache Controller Signals when a data correction event occurs
> 4 - L2 Cache Controller Signals when an uncorrectable data event occurs
>
> This differs from the SiFive FU540 which only has three L2 cache related
> interrupts.
>
> The sequence in the device tree is defined by an enum:
>
> enum {
> DIR_CORR = 0,
> DATA_CORR,
> DATA_UNCORR,
> DIR_UNCORR,
> };
>
> So the correct sequence of the L2 cache interrupts is
>
> interrupts = <1>, <3>, <4>, <2>;
>
> This manifests as an unusable system if the l2-cache driver is enabled,
> as the wrong interrupt gets cleared & the handler prints errors to the
> console ad infinitum.
>
> Fixes: 0fa6107eca41 ("RISC-V: Initial DTS for Microchip ICICLE board")
> CC: [email protected] # 5.15: e35b07a7df9b: riscv: dts: microchip: mpfs: Group tuples in interrupt properties
Looks like I screwed up here... I assume the non-application is due
to the rename.
> Link: https://lore.kernel.org/all/[email protected]/
> Signed-off-by: Heinrich Schuchardt <[email protected]>
> ---
> arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> index 4ef4bcb74872..57989b2ac186 100644
> --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> @@ -153,7 +153,7 @@ cache-controller@2010000 {
> cache-size = <2097152>;
> cache-unified;
> interrupt-parent = <&plic>;
> - interrupts = <1 2 3>;
> + interrupts = <1>, <3>, <4>, <2>;
Acked-by: Conor Dooley <[email protected]>
Thanks Heinrich.
> reg = <0x0 0x2010000 0x0 0x1000>;
> };
>
> --
> 2.37.2
>