2022-08-29 08:34:53

by Richard Zhu

Subject: [PATCH v4 0/6] Add iMX8MP PCIe support

Based on the 6.0-rc1 of the pci/next branch.
This series adds the i.MX8MP PCIe support and tested on i.MX8MP
EVK board when one PCIe NVME device is used.

- i.MX8MP PCIe has reversed initial PERST bit value refer to i.MX8MQ/i.MX8MM.
Add the PHY PERST explicitly for i.MX8MP PCIe PHY.
- Add the i.MX8MP PCIe PHY support in the i.MX8M PCIe PHY driver.
And share as much as possible codes with i.MX8MM PCIe PHY.
- Add the i.MX8MP PCIe support in binding document, DTS files, and PCIe
driver.

Main changes v3-->v4:
- Regarding Phillip's suggestions, add fix tag into the first commit.
- Add Reviewed and Tested tags.

Main changes v2-->v3:
- Fix the schema checking error in the PHY dt-binding patch.
- Inspired by Lucas, the PLL configurations might not required when
external OSC is used as PCIe referrence clock. It's true. Remove all
the HSIO PLL bit manipulations, and PCIe works fine on i.MX8MP EVK board
with one NVME device is used.
- Drop the #4 patch of v2, since it had been applied by Rob.

Main changes v1-->v2:
- It's my fault forget including Vinod, re-send v2 after include Vinod
and [email protected].
- List the basements of this patch-set. The branch, codes changes and so on.
- Clean up some useless register and bit definitions in #3 patch.

Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml | 16 +++++++--
arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 53 +++++++++++++++++++++++++++++
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 46 ++++++++++++++++++++++++-
drivers/pci/controller/dwc/pci-imx6.c | 17 +++++++++-
drivers/phy/freescale/phy-fsl-imx8m-pcie.c | 150 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++-------------------------
drivers/reset/reset-imx7.c | 1 +
6 files changed, 232 insertions(+), 51 deletions(-)

[PATCH v4 1/6] reset: imx7: Fix the iMX8MP PCIe PHY PERST support
[PATCH v4 2/6] dt-binding: phy: Add iMX8MP PCIe PHY binding
[PATCH v4 3/6] phy: freescale: imx8m-pcie: Add iMX8MP PCIe PHY
[PATCH v4 4/6] arm64: dts: imx8mp: Add iMX8MP PCIe support
[PATCH v4 5/6] arm64: dts: imx8mp-evk: Add PCIe support
[PATCH v4 6/6] PCI: imx6: Add iMX8MP PCIe support

2022-08-29 08:35:15

by Richard Zhu

Subject: [PATCH v4 3/6] phy: freescale: imx8m-pcie: Add iMX8MP PCIe PHY support

Add i.MX8MP PCIe PHY support

Signed-off-by: Richard Zhu <[email protected]>
Tested-by: Marek Vasut <[email protected]>
Tested-by: Richard Leitner <[email protected]>
Tested-by: Alexander Stein <[email protected]>
---
drivers/phy/freescale/phy-fsl-imx8m-pcie.c | 150 ++++++++++++++-------
1 file changed, 104 insertions(+), 46 deletions(-)

diff --git a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
index ad7d2edfc414..3463b4299f2f 100644
--- a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
+++ b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
@@ -11,6 +11,8 @@
#include <linux/mfd/syscon.h>
#include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
@@ -31,12 +33,10 @@
#define IMX8MM_PCIE_PHY_CMN_REG065 0x194
#define ANA_AUX_RX_TERM (BIT(7) | BIT(4))
#define ANA_AUX_TX_LVL GENMASK(3, 0)
-#define IMX8MM_PCIE_PHY_CMN_REG75 0x1D4
-#define PCIE_PHY_CMN_REG75_PLL_DONE 0x3
+#define IMX8MM_PCIE_PHY_CMN_REG075 0x1D4
+#define ANA_PLL_DONE 0x3
#define PCIE_PHY_TRSV_REG5 0x414
-#define PCIE_PHY_TRSV_REG5_GEN1_DEEMP 0x2D
#define PCIE_PHY_TRSV_REG6 0x418
-#define PCIE_PHY_TRSV_REG6_GEN2_DEEMP 0xF

#define IMX8MM_GPR_PCIE_REF_CLK_SEL GENMASK(25, 24)
#define IMX8MM_GPR_PCIE_REF_CLK_PLL FIELD_PREP(IMX8MM_GPR_PCIE_REF_CLK_SEL, 0x3)
@@ -47,16 +47,29 @@
#define IMX8MM_GPR_PCIE_SSC_EN BIT(16)
#define IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE BIT(9)

+#define IMX8MP_GPR_REG0 0x0
+#define IMX8MP_GPR_PHY_APB_RST BIT(4)
+#define IMX8MP_GPR_PHY_INIT_RST BIT(5)
+
+enum imx8_pcie_phy_type {
+ IMX8MM,
+ IMX8MP,
+};
+
struct imx8_pcie_phy {
void __iomem *base;
+ struct device *dev;
struct clk *clk;
struct phy *phy;
+ struct regmap *hsio_blk_ctrl;
struct regmap *iomuxc_gpr;
struct reset_control *reset;
+ struct reset_control *perst;
u32 refclk_pad_mode;
u32 tx_deemph_gen1;
u32 tx_deemph_gen2;
bool clkreq_unused;
+ enum imx8_pcie_phy_type variant;
};

static int imx8_pcie_phy_init(struct phy *phy)
@@ -68,31 +81,27 @@ static int imx8_pcie_phy_init(struct phy *phy)
reset_control_assert(imx8_phy->reset);

pad_mode = imx8_phy->refclk_pad_mode;
- /* Set AUX_EN_OVERRIDE 1'b0, when the CLKREQ# isn't hooked */
- regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
- IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE,
- imx8_phy->clkreq_unused ?
- 0 : IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE);
- regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
- IMX8MM_GPR_PCIE_AUX_EN,
- IMX8MM_GPR_PCIE_AUX_EN);
- regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
- IMX8MM_GPR_PCIE_POWER_OFF, 0);
- regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
- IMX8MM_GPR_PCIE_SSC_EN, 0);
-
- regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
- IMX8MM_GPR_PCIE_REF_CLK_SEL,
- pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ?
- IMX8MM_GPR_PCIE_REF_CLK_EXT :
- IMX8MM_GPR_PCIE_REF_CLK_PLL);
- usleep_range(100, 200);
-
- /* Do the PHY common block reset */
- regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
- IMX8MM_GPR_PCIE_CMN_RST,
- IMX8MM_GPR_PCIE_CMN_RST);
- usleep_range(200, 500);
+ switch (imx8_phy->variant) {
+ case IMX8MM:
+ /* Tune PHY de-emphasis setting to pass PCIe compliance. */
+ if (imx8_phy->tx_deemph_gen1)
+ writel(imx8_phy->tx_deemph_gen1,
+ imx8_phy->base + PCIE_PHY_TRSV_REG5);
+ if (imx8_phy->tx_deemph_gen2)
+ writel(imx8_phy->tx_deemph_gen2,
+ imx8_phy->base + PCIE_PHY_TRSV_REG6);
+ break;
+ case IMX8MP:
+ reset_control_assert(imx8_phy->perst);
+
+ /* release pcie_phy_apb_reset and pcie_phy_init_resetn */
+ regmap_update_bits(imx8_phy->hsio_blk_ctrl, IMX8MP_GPR_REG0,
+ IMX8MP_GPR_PHY_APB_RST |
+ IMX8MP_GPR_PHY_INIT_RST,
+ IMX8MP_GPR_PHY_APB_RST |
+ IMX8MP_GPR_PHY_INIT_RST);
+ break;
+ }

if (pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ||
pad_mode == IMX8_PCIE_REFCLK_PAD_UNUSED) {
@@ -120,20 +129,44 @@ static int imx8_pcie_phy_init(struct phy *phy)
imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG065);
}

- /* Tune PHY de-emphasis setting to pass PCIe compliance. */
- if (imx8_phy->tx_deemph_gen1)
- writel(imx8_phy->tx_deemph_gen1,
- imx8_phy->base + PCIE_PHY_TRSV_REG5);
- if (imx8_phy->tx_deemph_gen2)
- writel(imx8_phy->tx_deemph_gen2,
- imx8_phy->base + PCIE_PHY_TRSV_REG6);
+ /* Set AUX_EN_OVERRIDE 1'b0, when the CLKREQ# isn't hooked */
+ regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
+ IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE,
+ imx8_phy->clkreq_unused ?
+ 0 : IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE);
+ regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
+ IMX8MM_GPR_PCIE_AUX_EN,
+ IMX8MM_GPR_PCIE_AUX_EN);
+ regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
+ IMX8MM_GPR_PCIE_POWER_OFF, 0);
+ regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
+ IMX8MM_GPR_PCIE_SSC_EN, 0);
+
+ regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
+ IMX8MM_GPR_PCIE_REF_CLK_SEL,
+ pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ?
+ IMX8MM_GPR_PCIE_REF_CLK_EXT :
+ IMX8MM_GPR_PCIE_REF_CLK_PLL);
+ usleep_range(100, 200);

- reset_control_deassert(imx8_phy->reset);
+ /* Do the PHY common block reset */
+ regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
+ IMX8MM_GPR_PCIE_CMN_RST,
+ IMX8MM_GPR_PCIE_CMN_RST);
+
+ switch (imx8_phy->variant) {
+ case IMX8MP:
+ reset_control_deassert(imx8_phy->perst);
+ fallthrough;
+ case IMX8MM:
+ reset_control_deassert(imx8_phy->reset);
+ usleep_range(200, 500);
+ break;
+ }

/* Polling to check the phy is ready or not. */
- ret = readl_poll_timeout(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG75,
- val, val == PCIE_PHY_CMN_REG75_PLL_DONE,
- 10, 20000);
+ ret = readl_poll_timeout(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG075,
+ val, val == ANA_PLL_DONE, 10, 20000);
return ret;
}

@@ -160,18 +193,33 @@ static const struct phy_ops imx8_pcie_phy_ops = {
.owner = THIS_MODULE,
};

+static const struct of_device_id imx8_pcie_phy_of_match[] = {
+ {.compatible = "fsl,imx8mm-pcie-phy", .data = (void *)IMX8MM},
+ {.compatible = "fsl,imx8mp-pcie-phy", .data = (void *)IMX8MP},
+ { },
+};
+MODULE_DEVICE_TABLE(of, imx8_pcie_phy_of_match);
+
static int imx8_pcie_phy_probe(struct platform_device *pdev)
{
struct phy_provider *phy_provider;
struct device *dev = &pdev->dev;
+ const struct of_device_id *of_id;
struct device_node *np = dev->of_node;
struct imx8_pcie_phy *imx8_phy;
struct resource *res;

+ of_id = of_match_device(imx8_pcie_phy_of_match, dev);
+ if (!of_id)
+ return -EINVAL;
+
imx8_phy = devm_kzalloc(dev, sizeof(*imx8_phy), GFP_KERNEL);
if (!imx8_phy)
return -ENOMEM;

+ imx8_phy->dev = dev;
+ imx8_phy->variant = (enum imx8_pcie_phy_type)of_id->data;
+
/* get PHY refclk pad mode */
of_property_read_u32(np, "fsl,refclk-pad-mode",
&imx8_phy->refclk_pad_mode);
@@ -208,6 +256,22 @@ static int imx8_pcie_phy_probe(struct platform_device *pdev)
dev_err(dev, "Failed to get PCIEPHY reset control\n");
return PTR_ERR(imx8_phy->reset);
}
+ if (imx8_phy->variant == IMX8MP) {
+ /* Grab HSIO MIX config register range */
+ imx8_phy->hsio_blk_ctrl =
+ syscon_regmap_lookup_by_compatible("fsl,imx8mp-hsio-blk-ctrl");
+ if (IS_ERR(imx8_phy->hsio_blk_ctrl)) {
+ dev_err(dev, "Unable to find HSIO MIX registers\n");
+ return PTR_ERR(imx8_phy->hsio_blk_ctrl);
+ }
+
+ imx8_phy->perst =
+ devm_reset_control_get_exclusive(dev, "perst");
+ if (IS_ERR(imx8_phy->perst)) {
+ dev_err(dev, "Failed to get PCIE PHY PERST control\n");
+ return PTR_ERR(imx8_phy->perst);
+ }
+ }

res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
imx8_phy->base = devm_ioremap_resource(dev, res);
@@ -225,12 +289,6 @@ static int imx8_pcie_phy_probe(struct platform_device *pdev)
return PTR_ERR_OR_ZERO(phy_provider);
}

-static const struct of_device_id imx8_pcie_phy_of_match[] = {
- {.compatible = "fsl,imx8mm-pcie-phy",},
- { },
-};
-MODULE_DEVICE_TABLE(of, imx8_pcie_phy_of_match);
-
static struct platform_driver imx8_pcie_phy_driver = {
.probe = imx8_pcie_phy_probe,
.driver = {
--
2.25.1

2022-08-29 08:35:29

by Richard Zhu

Subject: [PATCH v4 1/6] reset: imx7: Fix the iMX8MP PCIe PHY PERST support

On i.MX7/iMX8MM/iMX8MQ, the initialized default value of PERST bit(BIT3)
of SRC_PCIEPHY_RCR is 1b'1.
But i.MX8MP has one inversed default value 1b'0 of PERST bit.

And the PERST bit should be kept 1b'1 after power and clocks are stable.
So fix the i.MX8MP PCIe PHY PERST support here.

Fixes: e08672c03981 ("reset: imx7: Add support for i.MX8MP SoC")
Signed-off-by: Richard Zhu <[email protected]>
Reviewed-by: Philipp Zabel <[email protected]>
Tested-by: Marek Vasut <[email protected]>
Tested-by: Richard Leitner <[email protected]>
Tested-by: Alexander Stein <[email protected]>
---
drivers/reset/reset-imx7.c | 1 +
1 file changed, 1 insertion(+)

diff --git a/drivers/reset/reset-imx7.c b/drivers/reset/reset-imx7.c
index 185a333df66c..d2408725eb2c 100644
--- a/drivers/reset/reset-imx7.c
+++ b/drivers/reset/reset-imx7.c
@@ -329,6 +329,7 @@ static int imx8mp_reset_set(struct reset_controller_dev *rcdev,
break;

case IMX8MP_RESET_PCIE_CTRL_APPS_EN:
+ case IMX8MP_RESET_PCIEPHY_PERST:
value = assert ? 0 : bit;
break;
}
--
2.25.1

2022-08-29 08:35:46

by Richard Zhu

Subject: [PATCH v4 2/6] dt-binding: phy: Add iMX8MP PCIe PHY binding

Add i.MX8MP PCIe PHY binding.
On iMX8MM, the initialized default value of PERST bit(BIT3) of
SRC_PCIEPHY_RCR is 1b'1.
But i.MX8MP has one inversed default value 1b'0 of PERST bit.

And the PERST bit should be kept 1b'1 after power and clocks are stable.
So add one more PERST explicitly for i.MX8MP PCIe PHY.

Signed-off-by: Richard Zhu <[email protected]>
Tested-by: Marek Vasut <[email protected]>
Tested-by: Richard Leitner <[email protected]>
Tested-by: Alexander Stein <[email protected]>
---
.../bindings/phy/fsl,imx8-pcie-phy.yaml | 16 +++++++++++++---
1 file changed, 13 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
index b6421eedece3..692783c7fd69 100644
--- a/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
@@ -16,6 +16,7 @@ properties:
compatible:
enum:
- fsl,imx8mm-pcie-phy
+ - fsl,imx8mp-pcie-phy

reg:
maxItems: 1
@@ -28,11 +29,16 @@ properties:
- const: ref

resets:
- maxItems: 1
+ minItems: 1
+ maxItems: 2

reset-names:
- items:
- - const: pciephy
+ oneOf:
+ - items: # for iMX8MM
+ - const: pciephy
+ - items: # for IMX8MP
+ - const: pciephy
+ - const: perst

fsl,refclk-pad-mode:
description: |
@@ -60,6 +66,10 @@ properties:
description: A boolean property indicating the CLKREQ# signal is
not supported in the board design (optional)

+ power-domains:
+ description: PCIe PHY power domain (optional).
+ maxItems: 1
+
required:
- "#phy-cells"
- compatible
--
2.25.1

2022-08-29 08:36:12

by Richard Zhu

Subject: [PATCH v4 4/6] arm64: dts: imx8mp: Add iMX8MP PCIe support

Add i.MX8MP PCIe support.

Signed-off-by: Richard Zhu <[email protected]>
Tested-by: Marek Vasut <[email protected]>
Tested-by: Richard Leitner <[email protected]>
Tested-by: Alexander Stein <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 46 ++++++++++++++++++++++-
1 file changed, 45 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index fe178b7d063c..d11f079fd1f3 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -5,6 +5,7 @@

#include <dt-bindings/clock/imx8mp-clock.h>
#include <dt-bindings/power/imx8mp-power.h>
+#include <dt-bindings/reset/imx8mp-reset.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -410,7 +411,8 @@ iomuxc: pinctrl@30330000 {
};

gpr: iomuxc-gpr@30340000 {
- compatible = "fsl,imx8mp-iomuxc-gpr", "syscon";
+ compatible = "fsl,imx8mp-iomuxc-gpr",
+ "fsl,imx6q-iomuxc-gpr", "syscon";
reg = <0x30340000 0x10000>;
};

@@ -1084,6 +1086,17 @@ media_blk_ctrl: blk-ctrl@32ec0000 {
#power-domain-cells = <1>;
};

+ pcie_phy: pcie-phy@32f00000 {
+ compatible = "fsl,imx8mp-pcie-phy";
+ reg = <0x32f00000 0x10000>;
+ resets = <&src IMX8MP_RESET_PCIEPHY>,
+ <&src IMX8MP_RESET_PCIEPHY_PERST>;
+ reset-names = "pciephy", "perst";
+ power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE_PHY>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
hsio_blk_ctrl: blk-ctrl@32f10000 {
compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon";
reg = <0x32f10000 0x24>;
@@ -1099,6 +1112,37 @@ hsio_blk_ctrl: blk-ctrl@32f10000 {
};
};

+ pcie: pcie@33800000 {
+ compatible = "fsl,imx8mp-pcie";
+ reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>;
+ reg-names = "dbi", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x00 0xff>;
+ ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */
+ <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
+ num-lanes = <1>;
+ num-viewport = <4>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,max-link-speed = <3>;
+ linux,pci-domain = <0>;
+ power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>;
+ resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>,
+ <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>;
+ reset-names = "apps", "turnoff";
+ phys = <&pcie_phy>;
+ phy-names = "pcie-phy";
+ status = "disabled";
+ };
+
gpu3d: gpu@38000000 {
compatible = "vivante,gc";
reg = <0x38000000 0x8000>;
--
2.25.1

2022-08-29 08:56:13

by Richard Zhu

Subject: [PATCH v4 6/6] PCI: imx6: Add iMX8MP PCIe support

Add i.MX8MP PCIe support.

Signed-off-by: Richard Zhu <[email protected]>
Tested-by: Marek Vasut <[email protected]>
Tested-by: Richard Leitner <[email protected]>
Tested-by: Alexander Stein <[email protected]>
---
drivers/pci/controller/dwc/pci-imx6.c | 17 ++++++++++++++++-
1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 6e5debdbc55b..786f5737ca6a 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -51,6 +51,7 @@ enum imx6_pcie_variants {
IMX7D,
IMX8MQ,
IMX8MM,
+ IMX8MP,
};

#define IMX6_PCIE_FLAG_IMX6_PHY BIT(0)
@@ -150,7 +151,8 @@ struct imx6_pcie {
static unsigned int imx6_pcie_grp_offset(const struct imx6_pcie *imx6_pcie)
{
WARN_ON(imx6_pcie->drvdata->variant != IMX8MQ &&
- imx6_pcie->drvdata->variant != IMX8MM);
+ imx6_pcie->drvdata->variant != IMX8MM &&
+ imx6_pcie->drvdata->variant != IMX8MP);
return imx6_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14;
}

@@ -301,6 +303,7 @@ static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
{
switch (imx6_pcie->drvdata->variant) {
case IMX8MM:
+ case IMX8MP:
/*
* The PHY initialization had been done in the PHY
* driver, break here directly.
@@ -558,6 +561,7 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
break;
case IMX8MM:
case IMX8MQ:
+ case IMX8MP:
ret = clk_prepare_enable(imx6_pcie->pcie_aux);
if (ret) {
dev_err(dev, "unable to enable pcie_aux clock\n");
@@ -602,6 +606,7 @@ static void imx6_pcie_disable_ref_clk(struct imx6_pcie *imx6_pcie)
break;
case IMX8MM:
case IMX8MQ:
+ case IMX8MP:
clk_disable_unprepare(imx6_pcie->pcie_aux);
break;
default:
@@ -669,6 +674,7 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
reset_control_assert(imx6_pcie->pciephy_reset);
fallthrough;
case IMX8MM:
+ case IMX8MP:
reset_control_assert(imx6_pcie->apps_reset);
break;
case IMX6SX:
@@ -744,6 +750,7 @@ static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
break;
case IMX6Q: /* Nothing to do */
case IMX8MM:
+ case IMX8MP:
break;
}

@@ -793,6 +800,7 @@ static void imx6_pcie_ltssm_enable(struct device *dev)
case IMX7D:
case IMX8MQ:
case IMX8MM:
+ case IMX8MP:
reset_control_deassert(imx6_pcie->apps_reset);
break;
}
@@ -812,6 +820,7 @@ static void imx6_pcie_ltssm_disable(struct device *dev)
case IMX7D:
case IMX8MQ:
case IMX8MM:
+ case IMX8MP:
reset_control_assert(imx6_pcie->apps_reset);
break;
}
@@ -1179,6 +1188,7 @@ static int imx6_pcie_probe(struct platform_device *pdev)
}
break;
case IMX8MM:
+ case IMX8MP:
imx6_pcie->pcie_aux = devm_clk_get(dev, "pcie_aux");
if (IS_ERR(imx6_pcie->pcie_aux))
return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_aux),
@@ -1320,6 +1330,10 @@ static const struct imx6_pcie_drvdata drvdata[] = {
.variant = IMX8MM,
.flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND,
},
+ [IMX8MP] = {
+ .variant = IMX8MP,
+ .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND,
+ },
};

static const struct of_device_id imx6_pcie_of_match[] = {
@@ -1329,6 +1343,7 @@ static const struct of_device_id imx6_pcie_of_match[] = {
{ .compatible = "fsl,imx7d-pcie", .data = &drvdata[IMX7D], },
{ .compatible = "fsl,imx8mq-pcie", .data = &drvdata[IMX8MQ], },
{ .compatible = "fsl,imx8mm-pcie", .data = &drvdata[IMX8MM], },
+ { .compatible = "fsl,imx8mp-pcie", .data = &drvdata[IMX8MP], },
{},
};

--
2.25.1

2022-08-29 08:58:18

by Richard Zhu

Subject: [PATCH v4 5/6] arm64: dts: imx8mp-evk: Add PCIe support

Add PCIe support on i.MX8MP EVK board.

Signed-off-by: Richard Zhu <[email protected]>
Tested-by: Marek Vasut <[email protected]>
Tested-by: Richard Leitner <[email protected]>
Tested-by: Alexander Stein <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 53 ++++++++++++++++++++
1 file changed, 53 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
index f6b017ab5f53..defc92a8bb60 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
@@ -5,6 +5,7 @@

/dts-v1/;

+#include <dt-bindings/phy/phy-imx8-pcie.h>
#include "imx8mp.dtsi"

/ {
@@ -33,6 +34,12 @@ memory@40000000 {
<0x1 0x00000000 0 0xc0000000>;
};

+ pcie0_refclk: pcie0-refclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ };
+
reg_can1_stby: regulator-can1-stby {
compatible = "regulator-fixed";
regulator-name = "can1-stby";
@@ -55,6 +62,17 @@ reg_can2_stby: regulator-can2-stby {
enable-active-high;
};

+ reg_pcie0: regulator-pcie {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie0_reg>;
+ regulator-name = "MPCIE_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
pinctrl-names = "default";
@@ -350,6 +368,28 @@ &i2c5 {
*/
};

+&pcie_phy {
+ fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
+ clocks = <&pcie0_refclk>;
+ clock-names = "ref";
+ status = "okay";
+};
+
+&pcie{
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie0>;
+ reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>;
+ clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
+ <&clk IMX8MP_CLK_PCIE_ROOT>,
+ <&clk IMX8MP_CLK_HSIO_AXI>;
+ clock-names = "pcie", "pcie_aux", "pcie_bus";
+ assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
+ assigned-clock-rates = <10000000>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
+ vpcie-supply = <&reg_pcie0>;
+ status = "okay";
+};
+
&snvs_pwrkey {
status = "okay";
};
@@ -502,6 +542,19 @@ MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c2
>;
};

+ pinctrl_pcie0: pcie0grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x61 /* open drain, pull up */
+ MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x41
+ >;
+ };
+
+ pinctrl_pcie0_reg: pcie0reggrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x41
+ >;
+ };
+
pinctrl_pmic: pmicgrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x000001c0
--
2.25.1

2022-08-29 15:38:29

by Lucas Stach

Subject: [PATCH 1/2] soc: imx: imx8mp-blk-ctrl: handle PCIe PHY resets

Dessert the PHY reset when powering up the domain and put it back
into reset when the domain is powered down.

Signed-off-by: Lucas Stach <[email protected]>
---
drivers/soc/imx/imx8mp-blk-ctrl.c | 10 ++++++++++
1 file changed, 10 insertions(+)

diff --git a/drivers/soc/imx/imx8mp-blk-ctrl.c b/drivers/soc/imx/imx8mp-blk-ctrl.c
index 4ca2ede6871b..6c939d68ba9a 100644
--- a/drivers/soc/imx/imx8mp-blk-ctrl.c
+++ b/drivers/soc/imx/imx8mp-blk-ctrl.c
@@ -18,6 +18,8 @@
#define GPR_REG0 0x0
#define PCIE_CLOCK_MODULE_EN BIT(0)
#define USB_CLOCK_MODULE_EN BIT(1)
+#define PCIE_PHY_APB_RST BIT(4)
+#define PCIE_PHY_INIT_RST BIT(5)

struct imx8mp_blk_ctrl_domain;

@@ -75,6 +77,10 @@ static void imx8mp_hsio_blk_ctrl_power_on(struct imx8mp_blk_ctrl *bc,
case IMX8MP_HSIOBLK_PD_PCIE:
regmap_set_bits(bc->regmap, GPR_REG0, PCIE_CLOCK_MODULE_EN);
break;
+ case IMX8MP_HSIOBLK_PD_PCIE_PHY:
+ regmap_set_bits(bc->regmap, GPR_REG0,
+ PCIE_PHY_APB_RST | PCIE_PHY_INIT_RST);
+ break;
default:
break;
}
@@ -90,6 +96,10 @@ static void imx8mp_hsio_blk_ctrl_power_off(struct imx8mp_blk_ctrl *bc,
case IMX8MP_HSIOBLK_PD_PCIE:
regmap_clear_bits(bc->regmap, GPR_REG0, PCIE_CLOCK_MODULE_EN);
break;
+ case IMX8MP_HSIOBLK_PD_PCIE_PHY:
+ regmap_clear_bits(bc->regmap, GPR_REG0,
+ PCIE_PHY_APB_RST | PCIE_PHY_INIT_RST);
+ break;
default:
break;
}
--
2.30.2

2022-08-29 16:44:04

by Lucas Stach

Subject: Re: [PATCH v4 0/6] Add iMX8MP PCIe support

Hi Richard,

instead of review comments I sent you a two patches to rework things
more to my liking. Hope you agree with the approach.

One question, though: did you test this with devices with Gen2/3
speeds? The Marvell WiFi module on my EVK board only links with Gen1,
while it claims Gen2 speed in the LnkCap register. However, it does
seem to come up with Gen1 as the target link speed in LnkCtl2, so maybe
the device is at fault here.

Regards,
Lucas

Am Montag, dem 29.08.2022 um 16:15 +0800 schrieb Richard Zhu:
> Based on the 6.0-rc1 of the pci/next branch.
> This series adds the i.MX8MP PCIe support and tested on i.MX8MP
> EVK board when one PCIe NVME device is used.
>
> - i.MX8MP PCIe has reversed initial PERST bit value refer to i.MX8MQ/i.MX8MM.
> Add the PHY PERST explicitly for i.MX8MP PCIe PHY.
> - Add the i.MX8MP PCIe PHY support in the i.MX8M PCIe PHY driver.
> And share as much as possible codes with i.MX8MM PCIe PHY.
> - Add the i.MX8MP PCIe support in binding document, DTS files, and PCIe
> driver.
>
> Main changes v3-->v4:
> - Regarding Phillip's suggestions, add fix tag into the first commit.
> - Add Reviewed and Tested tags.
>
> Main changes v2-->v3:
> - Fix the schema checking error in the PHY dt-binding patch.
> - Inspired by Lucas, the PLL configurations might not required when
> external OSC is used as PCIe referrence clock. It's true. Remove all
> the HSIO PLL bit manipulations, and PCIe works fine on i.MX8MP EVK board
> with one NVME device is used.
> - Drop the #4 patch of v2, since it had been applied by Rob.
>
> Main changes v1-->v2:
> - It's my fault forget including Vinod, re-send v2 after include Vinod
> and [email protected].
> - List the basements of this patch-set. The branch, codes changes and so on.
> - Clean up some useless register and bit definitions in #3 patch.
>
> Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml | 16 +++++++--
> arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 53 +++++++++++++++++++++++++++++
> arch/arm64/boot/dts/freescale/imx8mp.dtsi | 46 ++++++++++++++++++++++++-
> drivers/pci/controller/dwc/pci-imx6.c | 17 +++++++++-
> drivers/phy/freescale/phy-fsl-imx8m-pcie.c | 150 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++-------------------------
> drivers/reset/reset-imx7.c | 1 +
> 6 files changed, 232 insertions(+), 51 deletions(-)
>
> [PATCH v4 1/6] reset: imx7: Fix the iMX8MP PCIe PHY PERST support
> [PATCH v4 2/6] dt-binding: phy: Add iMX8MP PCIe PHY binding
> [PATCH v4 3/6] phy: freescale: imx8m-pcie: Add iMX8MP PCIe PHY
> [PATCH v4 4/6] arm64: dts: imx8mp: Add iMX8MP PCIe support
> [PATCH v4 5/6] arm64: dts: imx8mp-evk: Add PCIe support
> [PATCH v4 6/6] PCI: imx6: Add iMX8MP PCIe support

2022-08-29 16:47:13

by Lucas Stach

Subject: Re: [PATCH v4 4/6] arm64: dts: imx8mp: Add iMX8MP PCIe support

Am Montag, dem 29.08.2022 um 16:15 +0800 schrieb Richard Zhu:
> Add i.MX8MP PCIe support.
>
> Signed-off-by: Richard Zhu <[email protected]>
> Tested-by: Marek Vasut <[email protected]>
> Tested-by: Richard Leitner <[email protected]>
> Tested-by: Alexander Stein <[email protected]>
> ---
> arch/arm64/boot/dts/freescale/imx8mp.dtsi | 46 ++++++++++++++++++++++-
> 1 file changed, 45 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> index fe178b7d063c..d11f079fd1f3 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> @@ -5,6 +5,7 @@
>
> #include <dt-bindings/clock/imx8mp-clock.h>
> #include <dt-bindings/power/imx8mp-power.h>
> +#include <dt-bindings/reset/imx8mp-reset.h>
> #include <dt-bindings/gpio/gpio.h>
> #include <dt-bindings/input/input.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> @@ -410,7 +411,8 @@ iomuxc: pinctrl@30330000 {
> };
>
> gpr: iomuxc-gpr@30340000 {
> - compatible = "fsl,imx8mp-iomuxc-gpr", "syscon";
> + compatible = "fsl,imx8mp-iomuxc-gpr",
> + "fsl,imx6q-iomuxc-gpr", "syscon";

I don't like this part. The iomux GPR in the i.MX8M* is not really
compatible with the i.MX6Q, so I think it's a pretty bad idea to claim
it is. Why can't we have this syscon looked up by phandle, like we
discussed in some early version of the i.MX8MM patchset? Sorry, for not
catching this on the 8MM submission, I was pretty busy back then.

Regards,
Lucas

> reg = <0x30340000 0x10000>;
> };
>
> @@ -1084,6 +1086,17 @@ media_blk_ctrl: blk-ctrl@32ec0000 {
> #power-domain-cells = <1>;
> };
>
> + pcie_phy: pcie-phy@32f00000 {
> + compatible = "fsl,imx8mp-pcie-phy";
> + reg = <0x32f00000 0x10000>;
> + resets = <&src IMX8MP_RESET_PCIEPHY>,
> + <&src IMX8MP_RESET_PCIEPHY_PERST>;
> + reset-names = "pciephy", "perst";
> + power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE_PHY>;
> + #phy-cells = <0>;
> + status = "disabled";
> + };
> +
> hsio_blk_ctrl: blk-ctrl@32f10000 {
> compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon";
> reg = <0x32f10000 0x24>;
> @@ -1099,6 +1112,37 @@ hsio_blk_ctrl: blk-ctrl@32f10000 {
> };
> };
>
> + pcie: pcie@33800000 {
> + compatible = "fsl,imx8mp-pcie";
> + reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>;
> + reg-names = "dbi", "config";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + device_type = "pci";
> + bus-range = <0x00 0xff>;
> + ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */
> + <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
> + num-lanes = <1>;
> + num-viewport = <4>;
> + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "msi";
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0x7>;
> + interrupt-map = <0 0 0 1 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 2 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 3 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 4 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
> + fsl,max-link-speed = <3>;
> + linux,pci-domain = <0>;
> + power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>;
> + resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>,
> + <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>;
> + reset-names = "apps", "turnoff";
> + phys = <&pcie_phy>;
> + phy-names = "pcie-phy";
> + status = "disabled";
> + };
> +
> gpu3d: gpu@38000000 {
> compatible = "vivante,gc";
> reg = <0x38000000 0x8000>;

2022-08-30 03:08:45

by Richard Zhu

Subject: RE: [PATCH v4 0/6] Add iMX8MP PCIe support

> -----Original Message-----
> From: Lucas Stach <[email protected]>
> Sent: 2022年8月29日 23:20
> To: Hongxing Zhu <[email protected]>; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]
> Cc: [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected]; dl-linux-imx
> <[email protected]>
> Subject: Re: [PATCH v4 0/6] Add iMX8MP PCIe support
>
> Hi Richard,
>
> instead of review comments I sent you a two patches to rework things more to
> my liking. Hope you agree with the approach.
>
> One question, though: did you test this with devices with Gen2/3 speeds? The
> Marvell WiFi module on my EVK board only links with Gen1, while it claims
> Gen2 speed in the LnkCap register. However, it does seem to come up with
> Gen1 as the target link speed in LnkCtl2, so maybe the device is at fault here.
Hi Lucas:
Thanks for your help on this series.
I'm agree with your approach, and let blk-ctrl driver do the hsiomix resets.
Can I include the #1 patch into this series, and rebase the 2# fixup! patch
into the phy changes patch with your sign-off?

Yes, I did the Gen3 NVEM device tests on i.MX8MP EVK board.
The Gen3 works fine.
Logs:
"
[ 1.808033] phy phy-32f00000.pcie-phy.1: phy_power_on was called before phy_init
[ 1.822609] imx6q-pcie 33800000.pcie: iATU unroll: enabled
[ 1.836620] imx6q-pcie 33800000.pcie: iATU regions: 4 ob, 4 ib, align 64K, limit 16G
[ 1.950427] imx6q-pcie 33800000.pcie: PCIe Gen.1 x1 link up
[ 2.058138] imx6q-pcie 33800000.pcie: PCIe Gen.3 x1 link up
[ 2.063731] imx6q-pcie 33800000.pcie: Link up, Gen3
[ 2.068619] imx6q-pcie 33800000.pcie: PCIe Gen.3 x1 link up
"

Best Regards
Richard Zhu
>
> Regards,
> Lucas
>
> Am Montag, dem 29.08.2022 um 16:15 +0800 schrieb Richard Zhu:
> > Based on the 6.0-rc1 of the pci/next branch.
> > This series adds the i.MX8MP PCIe support and tested on i.MX8MP EVK
> > board when one PCIe NVME device is used.
> >
> > - i.MX8MP PCIe has reversed initial PERST bit value refer to
> i.MX8MQ/i.MX8MM.
> > Add the PHY PERST explicitly for i.MX8MP PCIe PHY.
> > - Add the i.MX8MP PCIe PHY support in the i.MX8M PCIe PHY driver.
> > And share as much as possible codes with i.MX8MM PCIe PHY.
> > - Add the i.MX8MP PCIe support in binding document, DTS files, and PCIe
> > driver.
> >
> > Main changes v3-->v4:
> > - Regarding Phillip's suggestions, add fix tag into the first commit.
> > - Add Reviewed and Tested tags.
> >
> > Main changes v2-->v3:
> > - Fix the schema checking error in the PHY dt-binding patch.
> > - Inspired by Lucas, the PLL configurations might not required when
> > external OSC is used as PCIe referrence clock. It's true. Remove all
> > the HSIO PLL bit manipulations, and PCIe works fine on i.MX8MP EVK
> board
> > with one NVME device is used.
> > - Drop the #4 patch of v2, since it had been applied by Rob.
> >
> > Main changes v1-->v2:
> > - It's my fault forget including Vinod, re-send v2 after include Vinod
> > and [email protected].
> > - List the basements of this patch-set. The branch, codes changes and so on.
> > - Clean up some useless register and bit definitions in #3 patch.
> >
> > Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml | 16
> +++++++--
> > arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 53
> +++++++++++++++++++++++++++++
> > arch/arm64/boot/dts/freescale/imx8mp.dtsi | 46
> ++++++++++++++++++++++++-
> > drivers/pci/controller/dwc/pci-imx6.c | 17
> +++++++++-
> > drivers/phy/freescale/phy-fsl-imx8m-pcie.c | 150
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++++-------
> ------------------
> > drivers/reset/reset-imx7.c | 1 +
> > 6 files changed, 232 insertions(+), 51 deletions(-)
> >
> > [PATCH v4 1/6] reset: imx7: Fix the iMX8MP PCIe PHY PERST support
> > [PATCH v4 2/6] dt-binding: phy: Add iMX8MP PCIe PHY binding [PATCH v4
> > 3/6] phy: freescale: imx8m-pcie: Add iMX8MP PCIe PHY [PATCH v4 4/6]
> > arm64: dts: imx8mp: Add iMX8MP PCIe support [PATCH v4 5/6] arm64: dts:
> > imx8mp-evk: Add PCIe support [PATCH v4 6/6] PCI: imx6: Add iMX8MP PCIe
> > support
>

2022-08-30 03:31:05

by Richard Zhu

Subject: RE: [PATCH v4 4/6] arm64: dts: imx8mp: Add iMX8MP PCIe support

> -----Original Message-----
> From: Lucas Stach <[email protected]>
> Sent: 2022年8月29日 23:23
> To: Hongxing Zhu <[email protected]>; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]
> Cc: [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected]; dl-linux-imx
> <[email protected]>
> Subject: Re: [PATCH v4 4/6] arm64: dts: imx8mp: Add iMX8MP PCIe support
>
> Am Montag, dem 29.08.2022 um 16:15 +0800 schrieb Richard Zhu:
> > Add i.MX8MP PCIe support.
> >
> > Signed-off-by: Richard Zhu <[email protected]>
> > Tested-by: Marek Vasut <[email protected]>
> > Tested-by: Richard Leitner <[email protected]>
> > Tested-by: Alexander Stein <[email protected]>
> > ---
> > arch/arm64/boot/dts/freescale/imx8mp.dtsi | 46
> > ++++++++++++++++++++++-
> > 1 file changed, 45 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > index fe178b7d063c..d11f079fd1f3 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > @@ -5,6 +5,7 @@
> >
> > #include <dt-bindings/clock/imx8mp-clock.h>
> > #include <dt-bindings/power/imx8mp-power.h>
> > +#include <dt-bindings/reset/imx8mp-reset.h>
> > #include <dt-bindings/gpio/gpio.h>
> > #include <dt-bindings/input/input.h>
> > #include <dt-bindings/interrupt-controller/arm-gic.h>
> > @@ -410,7 +411,8 @@ iomuxc: pinctrl@30330000 {
> > };
> >
> > gpr: iomuxc-gpr@30340000 {
> > - compatible = "fsl,imx8mp-iomuxc-gpr", "syscon";
> > + compatible = "fsl,imx8mp-iomuxc-gpr",
> > + "fsl,imx6q-iomuxc-gpr", "syscon";
>
> I don't like this part. The iomux GPR in the i.MX8M* is not really compatible
> with the i.MX6Q, so I think it's a pretty bad idea to claim it is. Why can't we
> have this syscon looked up by phandle, like we discussed in some early version
> of the i.MX8MM patchset? Sorry, for not catching this on the 8MM submission,
> I was pretty busy back then.
Okay, got that. Thanks.
Would be changed, and fetch the gpr regmap by phandle in v5 later.

Best Regards
Richard Zhu

>
> Regards,
> Lucas
>
> > reg = <0x30340000 0x10000>;
> > };
> >
> > @@ -1084,6 +1086,17 @@ media_blk_ctrl: blk-ctrl@32ec0000 {
> > #power-domain-cells = <1>;
> > };
> >
> > + pcie_phy: pcie-phy@32f00000 {
> > + compatible = "fsl,imx8mp-pcie-phy";
> > + reg = <0x32f00000 0x10000>;
> > + resets = <&src IMX8MP_RESET_PCIEPHY>,
> > + <&src IMX8MP_RESET_PCIEPHY_PERST>;
> > + reset-names = "pciephy", "perst";
> > + power-domains = <&hsio_blk_ctrl
> IMX8MP_HSIOBLK_PD_PCIE_PHY>;
> > + #phy-cells = <0>;
> > + status = "disabled";
> > + };
> > +
> > hsio_blk_ctrl: blk-ctrl@32f10000 {
> > compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon";
> > reg = <0x32f10000 0x24>;
> > @@ -1099,6 +1112,37 @@ hsio_blk_ctrl: blk-ctrl@32f10000 {
> > };
> > };
> >
> > + pcie: pcie@33800000 {
> > + compatible = "fsl,imx8mp-pcie";
> > + reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>;
> > + reg-names = "dbi", "config";
> > + #address-cells = <3>;
> > + #size-cells = <2>;
> > + device_type = "pci";
> > + bus-range = <0x00 0xff>;
> > + ranges = <0x81000000 0 0x00000000 0x1ff80000 0
> 0x00010000>, /* downstream I/O 64KB */
> > + <0x82000000 0 0x18000000 0x18000000 0
> 0x07f00000>; /* non-prefetchable memory */
> > + num-lanes = <1>;
> > + num-viewport = <4>;
> > + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-names = "msi";
> > + #interrupt-cells = <1>;
> > + interrupt-map-mask = <0 0 0 0x7>;
> > + interrupt-map = <0 0 0 1 &gic GIC_SPI 126
> IRQ_TYPE_LEVEL_HIGH>,
> > + <0 0 0 2 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
> > + <0 0 0 3 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
> > + <0 0 0 4 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
> > + fsl,max-link-speed = <3>;
> > + linux,pci-domain = <0>;
> > + power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>;
> > + resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>,
> > + <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>;
> > + reset-names = "apps", "turnoff";
> > + phys = <&pcie_phy>;
> > + phy-names = "pcie-phy";
> > + status = "disabled";
> > + };
> > +
> > gpu3d: gpu@38000000 {
> > compatible = "vivante,gc";
> > reg = <0x38000000 0x8000>;
>

2022-08-30 08:03:45

by Richard Zhu

Subject: RE: [PATCH v4 0/6] Add iMX8MP PCIe support

> -----Original Message-----
> From: Lucas Stach <[email protected]>
> Sent: 2022年8月30日 15:46
> To: Hongxing Zhu <[email protected]>; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]
> Cc: [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected]; dl-linux-imx
> <[email protected]>
> Subject: Re: [PATCH v4 0/6] Add iMX8MP PCIe support
>
> Am Dienstag, dem 30.08.2022 um 02:58 +0000 schrieb Hongxing Zhu:
> > > -----Original Message-----
> > > From: Lucas Stach <[email protected]>
> > > Sent: 2022年8月29日 23:20
> > > To: Hongxing Zhu <[email protected]>; [email protected];
> > > [email protected]; [email protected]; [email protected];
> > > [email protected]; [email protected];
> > > [email protected]; [email protected];
> > > [email protected]
> > > Cc: [email protected]; [email protected];
> > > [email protected]; [email protected];
> > > [email protected]; [email protected]; dl-linux-imx
> > > <[email protected]>
> > > Subject: Re: [PATCH v4 0/6] Add iMX8MP PCIe support
> > >
> > > Hi Richard,
> > >
> > > instead of review comments I sent you a two patches to rework things
> > > more to my liking. Hope you agree with the approach.
> > >
> > > One question, though: did you test this with devices with Gen2/3
> > > speeds? The Marvell WiFi module on my EVK board only links with
> > > Gen1, while it claims
> > > Gen2 speed in the LnkCap register. However, it does seem to come up
> > > with
> > > Gen1 as the target link speed in LnkCtl2, so maybe the device is at fault
> here.
> > Hi Lucas:
> > Thanks for your help on this series.
> > I'm agree with your approach, and let blk-ctrl driver do the hsiomix resets.
> > Can I include the #1 patch into this series, and rebase the 2# fixup!
> > patch
> >  into the phy changes patch with your sign-off?
> >
> Sure, that's why I sent them this way. Feel free to include them in your series
> with my sign-off.
Got that, thanks a lot.

>
> > Yes, I did the Gen3 NVEM device tests on i.MX8MP EVK board.
> > The Gen3 works fine.
> > Logs:
> > "
> > [ 1.808033] phy phy-32f00000.pcie-phy.1: phy_power_on was called
> before phy_init
> > [ 1.822609] imx6q-pcie 33800000.pcie: iATU unroll: enabled
> > [ 1.836620] imx6q-pcie 33800000.pcie: iATU regions: 4 ob, 4 ib, align
> 64K, limit 16G
> > [ 1.950427] imx6q-pcie 33800000.pcie: PCIe Gen.1 x1 link up
> > [ 2.058138] imx6q-pcie 33800000.pcie: PCIe Gen.3 x1 link up
> > [ 2.063731] imx6q-pcie 33800000.pcie: Link up, Gen3
> > [ 2.068619] imx6q-pcie 33800000.pcie: PCIe Gen.3 x1 link up
> > "
> Thanks for the confirmation.
>
> Also can you please reorder the series, to have the DT changes at the end?

Okay, would reorder the DT changes at the begin in next version.

Best Regards
Richard Zhu

>
> Regards,
> Lucas
>
> >
> > Best Regards
> > Richard Zhu
> > >
> > > Regards,
> > > Lucas
> > >
> > > Am Montag, dem 29.08.2022 um 16:15 +0800 schrieb Richard Zhu:
> > > > Based on the 6.0-rc1 of the pci/next branch.
> > > > This series adds the i.MX8MP PCIe support and tested on i.MX8MP
> > > > EVK board when one PCIe NVME device is used.
> > > >
> > > > - i.MX8MP PCIe has reversed initial PERST bit value refer to
> > > i.MX8MQ/i.MX8MM.
> > > >   Add the PHY PERST explicitly for i.MX8MP PCIe PHY.
> > > > - Add the i.MX8MP PCIe PHY support in the i.MX8M PCIe PHY driver.
> > > >   And share as much as possible codes with i.MX8MM PCIe PHY.
> > > > - Add the i.MX8MP PCIe support in binding document, DTS files, and
> > > > PCIe
> > > >   driver.
> > > >
> > > > Main changes v3-->v4:
> > > > - Regarding Phillip's suggestions, add fix tag into the first commit.
> > > > - Add Reviewed and Tested tags.
> > > >
> > > > Main changes v2-->v3:
> > > > - Fix the schema checking error in the PHY dt-binding patch.
> > > > - Inspired by Lucas, the PLL configurations might not required
> > > > when
> > > >   external OSC is used as PCIe referrence clock. It's true. Remove
> > > > all
> > > >   the HSIO PLL bit manipulations, and PCIe works fine on i.MX8MP
> > > > EVK
> > > board
> > > >   with one NVME device is used.
> > > > - Drop the #4 patch of v2, since it had been applied by Rob.
> > > >
> > > > Main changes v1-->v2:
> > > > - It's my fault forget including Vinod, re-send v2 after include
> > > > Vinod
> > > >   and [email protected].
> > > > - List the basements of this patch-set. The branch, codes changes and so
> on.
> > > > - Clean up some useless register and bit definitions in #3 patch.
> > > >
> > > > Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml | 16
> > > +++++++--
> > > > arch/arm64/boot/dts/freescale/imx8mp-evk.dts |
> 53
> > > +++++++++++++++++++++++++++++
> > > > arch/arm64/boot/dts/freescale/imx8mp.dtsi |
> 46
> > > ++++++++++++++++++++++++-
> > > > drivers/pci/controller/dwc/pci-imx6.c | 17
> > > +++++++++-
> > > > drivers/phy/freescale/phy-fsl-imx8m-pcie.c | 150
> > >
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++++-------
> > > ------------------
> > > > drivers/reset/reset-imx7.c | 1
> +
> > > > 6 files changed, 232 insertions(+), 51 deletions(-)
> > > >
> > > > [PATCH v4 1/6] reset: imx7: Fix the iMX8MP PCIe PHY PERST support
> > > > [PATCH v4 2/6] dt-binding: phy: Add iMX8MP PCIe PHY binding [PATCH
> > > > v4 3/6] phy: freescale: imx8m-pcie: Add iMX8MP PCIe PHY [PATCH v4
> > > > 4/6]
> > > > arm64: dts: imx8mp: Add iMX8MP PCIe support [PATCH v4 5/6] arm64:
> dts:
> > > > imx8mp-evk: Add PCIe support [PATCH v4 6/6] PCI: imx6: Add iMX8MP
> > > > PCIe support
> > >
> >
>

2022-08-30 08:06:23

by Lucas Stach

Subject: Re: [PATCH v4 0/6] Add iMX8MP PCIe support

Am Dienstag, dem 30.08.2022 um 02:58 +0000 schrieb Hongxing Zhu:
> > -----Original Message-----
> > From: Lucas Stach <[email protected]>
> > Sent: 2022年8月29日 23:20
> > To: Hongxing Zhu <[email protected]>; [email protected];
> > [email protected]; [email protected]; [email protected];
> > [email protected]; [email protected]; [email protected];
> > [email protected]; [email protected]
> > Cc: [email protected]; [email protected];
> > [email protected]; [email protected];
> > [email protected]; [email protected]; dl-linux-imx
> > <[email protected]>
> > Subject: Re: [PATCH v4 0/6] Add iMX8MP PCIe support
> >
> > Hi Richard,
> >
> > instead of review comments I sent you a two patches to rework things more to
> > my liking. Hope you agree with the approach.
> >
> > One question, though: did you test this with devices with Gen2/3 speeds? The
> > Marvell WiFi module on my EVK board only links with Gen1, while it claims
> > Gen2 speed in the LnkCap register. However, it does seem to come up with
> > Gen1 as the target link speed in LnkCtl2, so maybe the device is at fault here.
> Hi Lucas:
> Thanks for your help on this series.
> I'm agree with your approach, and let blk-ctrl driver do the hsiomix resets.
> Can I include the #1 patch into this series, and rebase the 2# fixup! patch
>  into the phy changes patch with your sign-off?
>
Sure, that's why I sent them this way. Feel free to include them in
your series with my sign-off.

> Yes, I did the Gen3 NVEM device tests on i.MX8MP EVK board.
> The Gen3 works fine.
> Logs:
> "
> [ 1.808033] phy phy-32f00000.pcie-phy.1: phy_power_on was called before phy_init
> [ 1.822609] imx6q-pcie 33800000.pcie: iATU unroll: enabled
> [ 1.836620] imx6q-pcie 33800000.pcie: iATU regions: 4 ob, 4 ib, align 64K, limit 16G
> [ 1.950427] imx6q-pcie 33800000.pcie: PCIe Gen.1 x1 link up
> [ 2.058138] imx6q-pcie 33800000.pcie: PCIe Gen.3 x1 link up
> [ 2.063731] imx6q-pcie 33800000.pcie: Link up, Gen3
> [ 2.068619] imx6q-pcie 33800000.pcie: PCIe Gen.3 x1 link up
> "
Thanks for the confirmation.

Also can you please reorder the series, to have the DT changes at the
end?

Regards,
Lucas

>
> Best Regards
> Richard Zhu
> >
> > Regards,
> > Lucas
> >
> > Am Montag, dem 29.08.2022 um 16:15 +0800 schrieb Richard Zhu:
> > > Based on the 6.0-rc1 of the pci/next branch.
> > > This series adds the i.MX8MP PCIe support and tested on i.MX8MP EVK
> > > board when one PCIe NVME device is used.
> > >
> > > - i.MX8MP PCIe has reversed initial PERST bit value refer to
> > i.MX8MQ/i.MX8MM.
> > >   Add the PHY PERST explicitly for i.MX8MP PCIe PHY.
> > > - Add the i.MX8MP PCIe PHY support in the i.MX8M PCIe PHY driver.
> > >   And share as much as possible codes with i.MX8MM PCIe PHY.
> > > - Add the i.MX8MP PCIe support in binding document, DTS files, and PCIe
> > >   driver.
> > >
> > > Main changes v3-->v4:
> > > - Regarding Phillip's suggestions, add fix tag into the first commit.
> > > - Add Reviewed and Tested tags.
> > >
> > > Main changes v2-->v3:
> > > - Fix the schema checking error in the PHY dt-binding patch.
> > > - Inspired by Lucas, the PLL configurations might not required when
> > >   external OSC is used as PCIe referrence clock. It's true. Remove all
> > >   the HSIO PLL bit manipulations, and PCIe works fine on i.MX8MP EVK
> > board
> > >   with one NVME device is used.
> > > - Drop the #4 patch of v2, since it had been applied by Rob.
> > >
> > > Main changes v1-->v2:
> > > - It's my fault forget including Vinod, re-send v2 after include Vinod
> > >   and [email protected].
> > > - List the basements of this patch-set. The branch, codes changes and so on.
> > > - Clean up some useless register and bit definitions in #3 patch.
> > >
> > > Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml | 16
> > +++++++--
> > > arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 53
> > +++++++++++++++++++++++++++++
> > > arch/arm64/boot/dts/freescale/imx8mp.dtsi | 46
> > ++++++++++++++++++++++++-
> > > drivers/pci/controller/dwc/pci-imx6.c | 17
> > +++++++++-
> > > drivers/phy/freescale/phy-fsl-imx8m-pcie.c | 150
> > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++-------
> > ------------------
> > > drivers/reset/reset-imx7.c | 1 +
> > > 6 files changed, 232 insertions(+), 51 deletions(-)
> > >
> > > [PATCH v4 1/6] reset: imx7: Fix the iMX8MP PCIe PHY PERST support
> > > [PATCH v4 2/6] dt-binding: phy: Add iMX8MP PCIe PHY binding [PATCH v4
> > > 3/6] phy: freescale: imx8m-pcie: Add iMX8MP PCIe PHY [PATCH v4 4/6]
> > > arm64: dts: imx8mp: Add iMX8MP PCIe support [PATCH v4 5/6] arm64: dts:
> > > imx8mp-evk: Add PCIe support [PATCH v4 6/6] PCI: imx6: Add iMX8MP PCIe
> > > support
> >
>