This series documents the DMA capability of the I2C offload engine in
Allwinner V536 and newer SoCs. This includes the following SoCs which
have some support in mainline Linux:
- A100 (updated by this series)
- H616 (missing DMA controller binding/support)
- D1 (initial DT submission is on the ML; this series resolves some
dtbs_check warnings with that DT)
Samuel Holland (2):
dt-bindings: i2c: mv64xxx: Document DMA properties
arm64: dts: allwinner: a100: Add I2C DMA requests
Yangtao Li (1):
arm64: dts: allwinner: a100: Add device node for DMA controller
.../bindings/i2c/marvell,mv64xxx-i2c.yaml | 13 ++++++++++
.../arm64/boot/dts/allwinner/sun50i-a100.dtsi | 24 +++++++++++++++++++
2 files changed, 37 insertions(+)
--
2.35.1
From: Yangtao Li <[email protected]>
The A100 SoC has a DMA controller that supports 8 DMA channels
to and from various peripherals.
Add a device node for it.
Signed-off-by: Yangtao Li <[email protected]>
Signed-off-by: Samuel Holland <[email protected]>
---
Changes in v1:
- From previous submission: fixed off-by-one in dma-requests property
arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
index 548539c93ab0..5453a3bb7d81 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
@@ -101,6 +101,18 @@ ccu: clock@3001000 {
#reset-cells = <1>;
};
+ dma: dma-controller@3002000 {
+ compatible = "allwinner,sun50i-a100-dma";
+ reg = <0x03002000 0x1000>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>;
+ clock-names = "bus", "mbus";
+ resets = <&ccu RST_BUS_DMA>;
+ dma-channels = <8>;
+ dma-requests = <52>;
+ #dma-cells = <1>;
+ };
+
gic: interrupt-controller@3021000 {
compatible = "arm,gic-400";
reg = <0x03021000 0x1000>, <0x03022000 0x2000>,
--
2.35.1
The I2C controllers in the A100 SoC are all connected to the DMA engine.
Signed-off-by: Samuel Holland <[email protected]>
---
arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
index 5453a3bb7d81..97e3e6907acd 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
@@ -221,6 +221,8 @@ i2c0: i2c@5002000 {
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2C0>;
resets = <&ccu RST_BUS_I2C0>;
+ dmas = <&dma 43>, <&dma 43>;
+ dma-names = "rx", "tx";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
@@ -234,6 +236,8 @@ i2c1: i2c@5002400 {
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2C1>;
resets = <&ccu RST_BUS_I2C1>;
+ dmas = <&dma 44>, <&dma 44>;
+ dma-names = "rx", "tx";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
@@ -247,6 +251,8 @@ i2c2: i2c@5002800 {
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2C2>;
resets = <&ccu RST_BUS_I2C2>;
+ dmas = <&dma 45>, <&dma 45>;
+ dma-names = "rx", "tx";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
@@ -260,6 +266,8 @@ i2c3: i2c@5002c00 {
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2C3>;
resets = <&ccu RST_BUS_I2C3>;
+ dmas = <&dma 46>, <&dma 46>;
+ dma-names = "rx", "tx";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
@@ -337,6 +345,8 @@ r_i2c0: i2c@7081400 {
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&r_ccu CLK_R_APB2_I2C0>;
resets = <&r_ccu RST_R_APB2_I2C0>;
+ dmas = <&dma 50>, <&dma 50>;
+ dma-names = "rx", "tx";
pinctrl-names = "default";
pinctrl-0 = <&r_i2c0_pins>;
status = "disabled";
@@ -352,6 +362,8 @@ r_i2c1: i2c@7081800 {
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&r_ccu CLK_R_APB2_I2C1>;
resets = <&r_ccu RST_R_APB2_I2C1>;
+ dmas = <&dma 51>, <&dma 51>;
+ dma-names = "rx", "tx";
pinctrl-names = "default";
pinctrl-0 = <&r_i2c1_pins>;
status = "disabled";
--
2.35.1
Allwinner's I2C offload engine includes bidirectional DMA support. Add
the properties for describing this in the devicetree. "dmas" is optional
because not all instances of the controller have their DRQs hooked up.
For example, R_I2C0 and R_I2C1 on V536 have no DRQ number assigned.
Signed-off-by: Samuel Holland <[email protected]>
---
.../bindings/i2c/marvell,mv64xxx-i2c.yaml | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml b/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml
index 0ec033e48830..63d665a4f9bb 100644
--- a/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml
+++ b/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml
@@ -66,6 +66,19 @@ properties:
resets:
maxItems: 1
+ dmas:
+ items:
+ - description: RX DMA Channel
+ - description: TX DMA Channel
+
+ dma-names:
+ items:
+ - const: rx
+ - const: tx
+
+dependencies:
+ dmas: [ dma-names ]
+
required:
- compatible
- reg
--
2.35.1
On 30/08/2022 05:08, Samuel Holland wrote:
> Allwinner's I2C offload engine includes bidirectional DMA support. Add
> the properties for describing this in the devicetree. "dmas" is optional
> because not all instances of the controller have their DRQs hooked up.
> For example, R_I2C0 and R_I2C1 on V536 have no DRQ number assigned.
>
> Signed-off-by: Samuel Holland <[email protected]>
Thank you for your patch. There is something to discuss/improve.
> ---
>
> .../bindings/i2c/marvell,mv64xxx-i2c.yaml | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml b/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml
> index 0ec033e48830..63d665a4f9bb 100644
> --- a/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml
> +++ b/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml
> @@ -66,6 +66,19 @@ properties:
> resets:
> maxItems: 1
>
> + dmas:
> + items:
> + - description: RX DMA Channel
> + - description: TX DMA Channel
> +
> + dma-names:
> + items:
> + - const: rx
> + - const: tx
> +
> +dependencies:
> + dmas: [ dma-names ]
Dependency is not needed. meta-schema has it.
Best regards,
Krzysztof
On 30/08/2022 16:10, Samuel Holland wrote:
> On 8/30/22 4:36 AM, Krzysztof Kozlowski wrote:
>> On 30/08/2022 05:08, Samuel Holland wrote:
>>> Allwinner's I2C offload engine includes bidirectional DMA support. Add
>>> the properties for describing this in the devicetree. "dmas" is optional
>>> because not all instances of the controller have their DRQs hooked up.
>>> For example, R_I2C0 and R_I2C1 on V536 have no DRQ number assigned.
>>>
>>> Signed-off-by: Samuel Holland <[email protected]>
>>
>> Thank you for your patch. There is something to discuss/improve.
>>
>>> ---
>>>
>>> .../bindings/i2c/marvell,mv64xxx-i2c.yaml | 13 +++++++++++++
>>> 1 file changed, 13 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml b/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml
>>> index 0ec033e48830..63d665a4f9bb 100644
>>> --- a/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml
>>> +++ b/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml
>>> @@ -66,6 +66,19 @@ properties:
>>> resets:
>>> maxItems: 1
>>>
>>> + dmas:
>>> + items:
>>> + - description: RX DMA Channel
>>> + - description: TX DMA Channel
>>> +
>>> + dma-names:
>>> + items:
>>> + - const: rx
>>> + - const: tx
>>> +
>>> +dependencies:
>>> + dmas: [ dma-names ]
>>
>> Dependency is not needed. meta-schema has it.
>
> The only dma-names dependencies I see in dtschema (meta-schemas/dma.yaml and
> schemas/dma/dma.yaml) are in the other direction. Those are saying that
> dma-names only makes sense if dmas is provided.
>
> Here I am saying that the two DMA requests are optional, but only optional
> "together". The node must either have no DMA properties or both DMA properties.
Right, that's correct.
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
On 8/30/22 4:36 AM, Krzysztof Kozlowski wrote:
> On 30/08/2022 05:08, Samuel Holland wrote:
>> Allwinner's I2C offload engine includes bidirectional DMA support. Add
>> the properties for describing this in the devicetree. "dmas" is optional
>> because not all instances of the controller have their DRQs hooked up.
>> For example, R_I2C0 and R_I2C1 on V536 have no DRQ number assigned.
>>
>> Signed-off-by: Samuel Holland <[email protected]>
>
> Thank you for your patch. There is something to discuss/improve.
>
>> ---
>>
>> .../bindings/i2c/marvell,mv64xxx-i2c.yaml | 13 +++++++++++++
>> 1 file changed, 13 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml b/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml
>> index 0ec033e48830..63d665a4f9bb 100644
>> --- a/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml
>> +++ b/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml
>> @@ -66,6 +66,19 @@ properties:
>> resets:
>> maxItems: 1
>>
>> + dmas:
>> + items:
>> + - description: RX DMA Channel
>> + - description: TX DMA Channel
>> +
>> + dma-names:
>> + items:
>> + - const: rx
>> + - const: tx
>> +
>> +dependencies:
>> + dmas: [ dma-names ]
>
> Dependency is not needed. meta-schema has it.
The only dma-names dependencies I see in dtschema (meta-schemas/dma.yaml and
schemas/dma/dma.yaml) are in the other direction. Those are saying that
dma-names only makes sense if dmas is provided.
Here I am saying that the two DMA requests are optional, but only optional
"together". The node must either have no DMA properties or both DMA properties.
Regards,
Samuel
Dne torek, 30. avgust 2022 ob 04:08:24 CEST je Samuel Holland napisal(a):
> The I2C controllers in the A100 SoC are all connected to the DMA engine.
>
> Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Jernej Skrabec <[email protected]>
Best regards,
Jernej
Dne torek, 30. avgust 2022 ob 04:08:23 CEST je Samuel Holland napisal(a):
> From: Yangtao Li <[email protected]>
>
> The A100 SoC has a DMA controller that supports 8 DMA channels
> to and from various peripherals.
>
> Add a device node for it.
>
> Signed-off-by: Yangtao Li <[email protected]>
> Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Jernej Skrabec <[email protected]>
Best regards,
Jernej
On Mon, Aug 29, 2022 at 09:08:22PM -0500, Samuel Holland wrote:
> Allwinner's I2C offload engine includes bidirectional DMA support. Add
> the properties for describing this in the devicetree. "dmas" is optional
> because not all instances of the controller have their DRQs hooked up.
> For example, R_I2C0 and R_I2C1 on V536 have no DRQ number assigned.
>
> Signed-off-by: Samuel Holland <[email protected]>
Applied to for-next, thanks!
Dne torek, 06. september 2022 ob 23:11:02 CEST je Jernej Škrabec napisal(a):
> Dne torek, 30. avgust 2022 ob 04:08:24 CEST je Samuel Holland napisal(a):
> > The I2C controllers in the A100 SoC are all connected to the DMA engine.
> >
> > Signed-off-by: Samuel Holland <[email protected]>
>
> Reviewed-by: Jernej Skrabec <[email protected]>
Applied, thanks!
Best regards,
Jernej
Dne torek, 06. september 2022 ob 23:09:38 CEST je Jernej Škrabec napisal(a):
> Dne torek, 30. avgust 2022 ob 04:08:23 CEST je Samuel Holland napisal(a):
> > From: Yangtao Li <[email protected]>
> >
> > The A100 SoC has a DMA controller that supports 8 DMA channels
> > to and from various peripherals.
> >
> > Add a device node for it.
> >
> > Signed-off-by: Yangtao Li <[email protected]>
> > Signed-off-by: Samuel Holland <[email protected]>
>
> Reviewed-by: Jernej Skrabec <[email protected]>
Applied, thanks!
Best regards,
Jernej