2022-09-01 07:30:57

by Iskren Chernev

Subject: [PATCH 06/14] arm64: dts: qcom: sm6115: Add usb and related phy nodes

Add support for the USB controller and its HS PHY to SM6115.

Signed-off-by: Iskren Chernev <[email protected]>
---
arch/arm64/boot/dts/qcom/sm6115.dtsi | 62 ++++++++++++++++++++++++++++
1 file changed, 62 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi
index a6be8b93a44d..00fd185c87aa 100644
--- a/arch/arm64/boot/dts/qcom/sm6115.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi
@@ -412,6 +412,21 @@ gcc: clock-controller@1400000 {
#power-domain-cells = <1>;
};

+ hsusb_phy: phy@1613000 {
+ compatible = "qcom,sm6115-qusb2-phy";
+ reg = <0x1613000 0x180>;
+ #phy-cells = <0>;
+
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
+ <&gcc GCC_AHB2PHY_USB_CLK>;
+ clock-names = "ref", "cfg_ahb";
+
+ resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
+ nvmem-cells = <&qusb2_hstx_trim>;
+
+ status = "disabled";
+ };
+
qfprom@1b40000 {
compatible = "qcom,qfprom";
reg = <0x1b40000 0x7000>;
@@ -434,6 +449,53 @@ rpm_msg_ram: memory@45f0000 {
reg = <0x45f0000 0x7000>;
};

+ usb3: usb@4ef8800 {
+ compatible = "qcom,sm6115-dwc3", "qcom,dwc3";
+ reg = <0x04ef8800 0x400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
+ <&gcc GCC_USB30_PRIM_MASTER_CLK>,
+ <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>,
+ <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
+ <&gcc GCC_USB3_PRIM_CLKREF_CLK>;
+ clock-names = "cfg_noc", "core", "iface", "mock_utmi",
+ "sleep", "xo";
+
+ assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB30_PRIM_MASTER_CLK>;
+ assigned-clock-rates = <19200000>, <66666667>;
+
+ interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hs_phy_irq", "ss_phy_irq";
+
+ resets = <&gcc GCC_USB30_PRIM_BCR>;
+ power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
+ qcom,select-utmi-as-pipe-clk;
+ status = "disabled";
+
+ usb3_dwc3: dwc3@4e00000 {
+ compatible = "snps,dwc3";
+ reg = <0x04e00000 0xcd00>;
+ interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&hsusb_phy>;
+ phy-names = "usb2-phy";
+ iommus = <&apps_smmu 0x120 0x0>;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_enblslpm_quirk;
+ snps,has-lpm-erratum;
+ snps,hird-threshold = /bits/ 8 <0x10>;
+ snps,usb3_lpm_capable;
+ imod-interval-ns = <160>;
+ maximum-speed = "high-speed";
+ dr_mode = "peripheral";
+ };
+ };
+
apps_smmu: iommu@c600000 {
compatible = "qcom,sm6115-smmu-500", "arm,mmu-500";
reg = <0xc600000 0x80000>;
--
2.37.2

2022-09-01 17:08:18

by Krzysztof Kozlowski

Subject: Re: [PATCH 06/14] arm64: dts: qcom: sm6115: Add usb and related phy nodes

On 01/09/2022 10:24, Iskren Chernev wrote:
> Add support for the USB controller and its HS PHY to SM6115.
>
> Signed-off-by: Iskren Chernev <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/sm6115.dtsi | 62 ++++++++++++++++++++++++++++
> 1 file changed, 62 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi
> index a6be8b93a44d..00fd185c87aa 100644
> --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi
> @@ -412,6 +412,21 @@ gcc: clock-controller@1400000 {
> #power-domain-cells = <1>;
> };
>
> + hsusb_phy: phy@1613000 {
> + compatible = "qcom,sm6115-qusb2-phy";
> + reg = <0x1613000 0x180>;
> + #phy-cells = <0>;
> +
> + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
> + <&gcc GCC_AHB2PHY_USB_CLK>;
> + clock-names = "ref", "cfg_ahb";
> +
> + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
> + nvmem-cells = <&qusb2_hstx_trim>;
> +
> + status = "disabled";
> + };
> +
> qfprom@1b40000 {
> compatible = "qcom,qfprom";
> reg = <0x1b40000 0x7000>;
> @@ -434,6 +449,53 @@ rpm_msg_ram: memory@45f0000 {
> reg = <0x45f0000 0x7000>;
> };
>
> + usb3: usb@4ef8800 {
> + compatible = "qcom,sm6115-dwc3", "qcom,dwc3";
> + reg = <0x04ef8800 0x400>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
> + <&gcc GCC_USB30_PRIM_MASTER_CLK>,
> + <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>,
> + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
> + <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
> + <&gcc GCC_USB3_PRIM_CLKREF_CLK>;
> + clock-names = "cfg_noc", "core", "iface", "mock_utmi",
> + "sleep", "xo";
> +
> + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
> + <&gcc GCC_USB30_PRIM_MASTER_CLK>;
> + assigned-clock-rates = <19200000>, <66666667>;
> +
> + interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "hs_phy_irq", "ss_phy_irq";
> +
> + resets = <&gcc GCC_USB30_PRIM_BCR>;
> + power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
> + qcom,select-utmi-as-pipe-clk;
> + status = "disabled";
> +
> + usb3_dwc3: dwc3@4e00000 {

Node name: usb

Does not look like you tested the DTS against bindings. Please run `make
dtbs_check` (see Documentation/devicetree/bindings/writing-schema.rst
for instructions).

Best regards,
Krzysztof