From: Mikko Perttunen <[email protected]>
Hi all,
this series adds support for the HW video decoder, NVDEC,
on Tegra234 (Orin). The main change is a switch from Falcon
to RISC-V for the internal microcontroller, which brings along
a change in how the engine is booted. Otherwise it is backwards
compatible with earlier versions.
In previous iterations, firmware was simply loaded from disk and
written into engine internal memory. Now, the engine has a
bootrom that loads the firmware from a carveout where it has been
loaded by the system bootloader; however, we still need to tell it
where that carveout is loaded and some offsets into it. For that,
the first patch adds a new memory controller API to query the
carveout address. The offsets are read from device tree -- the
expectation is that at flashing time (when the firmware is also
flashed), the flasher also delivers a device tree overlay with
values corresponding to the flashed firmware.
The currently available Linux for Tegra release doesn't yet
include this device tree overlay flashing, and the firmware version
it contains is incompatible with this series. The plan is to fix
that for the next Linux for Tegra release, but if necessary, we
can postpone merging of this series to once those changes are
available.
Thanks!
Mikko
Mikko Perttunen (8):
memory: tegra: Add API for retrieving carveout bounds
dt-bindings: Add headers for NVDEC on Tegra234
dt-bindings: Add bindings for Tegra234 NVDEC
arm64: tegra: Add NVDEC on Tegra234
gpu: host1x: Add stream ID register data for NVDEC on Tegra234
drm/tegra: nvdec: Support multiple clocks
drm/tegra: Add code for booting RISC-V based engines
drm/tegra: Add Tegra234 support to NVDEC driver
.../gpu/host1x/nvidia,tegra210-nvdec.yaml | 118 ++++++++++--
arch/arm64/boot/dts/nvidia/tegra234.dtsi | 27 +++
drivers/gpu/drm/tegra/Makefile | 3 +-
drivers/gpu/drm/tegra/drm.c | 1 +
drivers/gpu/drm/tegra/nvdec.c | 171 +++++++++++++++---
drivers/gpu/drm/tegra/riscv.c | 106 +++++++++++
drivers/gpu/drm/tegra/riscv.h | 30 +++
drivers/gpu/host1x/dev.c | 12 ++
drivers/memory/tegra/mc.c | 23 +++
drivers/memory/tegra/tegra234.c | 5 +
include/dt-bindings/clock/tegra234-clock.h | 4 +
include/dt-bindings/memory/tegra234-mc.h | 3 +
.../dt-bindings/power/tegra234-powergate.h | 1 +
include/dt-bindings/reset/tegra234-reset.h | 1 +
include/soc/tegra/mc.h | 11 ++
15 files changed, 470 insertions(+), 46 deletions(-)
create mode 100644 drivers/gpu/drm/tegra/riscv.c
create mode 100644 drivers/gpu/drm/tegra/riscv.h
--
2.37.0
From: Mikko Perttunen <[email protected]>
NVDEC on Tegra234 requires multiple clocks. Add support for that.
Signed-off-by: Mikko Perttunen <[email protected]>
---
drivers/gpu/drm/tegra/nvdec.c | 31 +++++++++++++++++++++----------
1 file changed, 21 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/tegra/nvdec.c b/drivers/gpu/drm/tegra/nvdec.c
index 276fe0472730..05af4d107421 100644
--- a/drivers/gpu/drm/tegra/nvdec.c
+++ b/drivers/gpu/drm/tegra/nvdec.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (c) 2015-2021, NVIDIA Corporation.
+ * Copyright (c) 2015-2022, NVIDIA Corporation.
*/
#include <linux/clk.h>
@@ -28,6 +28,7 @@ struct nvdec_config {
const char *firmware;
unsigned int version;
bool supports_sid;
+ bool has_extra_clocks;
};
struct nvdec {
@@ -37,7 +38,8 @@ struct nvdec {
struct tegra_drm_client client;
struct host1x_channel *channel;
struct device *dev;
- struct clk *clk;
+ struct clk_bulk_data clks[3];
+ unsigned int num_clks;
/* Platform configuration */
const struct nvdec_config *config;
@@ -258,7 +260,7 @@ static __maybe_unused int nvdec_runtime_resume(struct device *dev)
struct nvdec *nvdec = dev_get_drvdata(dev);
int err;
- err = clk_prepare_enable(nvdec->clk);
+ err = clk_bulk_prepare_enable(nvdec->num_clks, nvdec->clks);
if (err < 0)
return err;
@@ -275,7 +277,7 @@ static __maybe_unused int nvdec_runtime_resume(struct device *dev)
return 0;
disable:
- clk_disable_unprepare(nvdec->clk);
+ clk_bulk_disable_unprepare(nvdec->num_clks, nvdec->clks);
return err;
}
@@ -285,7 +287,7 @@ static __maybe_unused int nvdec_runtime_suspend(struct device *dev)
host1x_channel_stop(nvdec->channel);
- clk_disable_unprepare(nvdec->clk);
+ clk_bulk_disable_unprepare(nvdec->num_clks, nvdec->clks);
return 0;
}
@@ -383,13 +385,22 @@ static int nvdec_probe(struct platform_device *pdev)
if (IS_ERR(nvdec->regs))
return PTR_ERR(nvdec->regs);
- nvdec->clk = devm_clk_get(dev, NULL);
- if (IS_ERR(nvdec->clk)) {
- dev_err(&pdev->dev, "failed to get clock\n");
- return PTR_ERR(nvdec->clk);
+ nvdec->clks[0].id = "nvdec";
+ nvdec->num_clks = 1;
+
+ if (nvdec->config->has_extra_clocks) {
+ nvdec->num_clks = 3;
+ nvdec->clks[1].id = "fuse";
+ nvdec->clks[2].id = "tsec_pka";
+ }
+
+ err = devm_clk_bulk_get(dev, nvdec->num_clks, nvdec->clks);
+ if (err) {
+ dev_err(&pdev->dev, "failed to get clock(s)\n");
+ return err;
}
- err = clk_set_rate(nvdec->clk, ULONG_MAX);
+ err = clk_set_rate(nvdec->clks[0].clk, ULONG_MAX);
if (err < 0) {
dev_err(&pdev->dev, "failed to set clock rate\n");
return err;
--
2.37.0
From: Mikko Perttunen <[email protected]>
Add a device tree node for NVDEC on Tegra234.
Booting the firmware requires some information regarding offsets
within the firmware binary. These are passed through the device
tree, but since the values vary depending on the firmware version,
and the firmware itself is not available to the OS, the flasher is
expected to provide a device tree overlay with values corresponding
to the firmware it is flashing. The overlay then replaces the
placeholder values here.
Signed-off-by: Mikko Perttunen <[email protected]>
---
arch/arm64/boot/dts/nvidia/tegra234.dtsi | 27 ++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
index 81a0f599685f..65d49b27bc5f 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
@@ -586,6 +586,33 @@ vic@15340000 {
iommus = <&smmu_niso1 TEGRA234_SID_VIC>;
dma-coherent;
};
+
+ nvdec@15480000 {
+ compatible = "nvidia,tegra234-nvdec";
+ reg = <0x15480000 0x00040000>;
+ clocks = <&bpmp TEGRA234_CLK_NVDEC>,
+ <&bpmp TEGRA234_CLK_FUSE>,
+ <&bpmp TEGRA234_CLK_TSEC_PKA>;
+ clock-names = "nvdec", "fuse", "tsec_pka";
+ resets = <&bpmp TEGRA234_RESET_NVDEC>;
+ reset-names = "nvdec";
+ power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVDEC>;
+ interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVDECSRD &emc>,
+ <&mc TEGRA234_MEMORY_CLIENT_NVDECSWR &emc>;
+ interconnect-names = "dma-mem", "write";
+ iommus = <&smmu_niso1 TEGRA234_SID_NVDEC>;
+ dma-coherent;
+
+ nvidia,memory-controller = <&mc>;
+
+ /* Placeholder values, to be replaced with values from overlay */
+ nvidia,bl-manifest-offset = <0>;
+ nvidia,bl-data-offset = <0>;
+ nvidia,bl-code-offset = <0>;
+ nvidia,os-manifest-offset = <0>;
+ nvidia,os-data-offset = <0>;
+ nvidia,os-code-offset = <0>;
+ };
};
gpio: gpio@2200000 {
--
2.37.0
From: Mikko Perttunen <[email protected]>
Add support for the Tegra234 version of NVDEC to the NVDEC driver.
This version sports a RISC-V controller and requires a few additional
clocks. After firmware has been loaded, the behavior is, however,
backwards compatible.
Signed-off-by: Mikko Perttunen <[email protected]>
---
drivers/gpu/drm/tegra/drm.c | 1 +
drivers/gpu/drm/tegra/nvdec.c | 140 ++++++++++++++++++++++++++++++----
2 files changed, 126 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c
index 6748ec1e0005..a014f11e9edb 100644
--- a/drivers/gpu/drm/tegra/drm.c
+++ b/drivers/gpu/drm/tegra/drm.c
@@ -1382,6 +1382,7 @@ static const struct of_device_id host1x_drm_subdevs[] = {
{ .compatible = "nvidia,tegra194-vic", },
{ .compatible = "nvidia,tegra194-nvdec", },
{ .compatible = "nvidia,tegra234-vic", },
+ { .compatible = "nvidia,tegra234-nvdec", },
{ /* sentinel */ }
};
diff --git a/drivers/gpu/drm/tegra/nvdec.c b/drivers/gpu/drm/tegra/nvdec.c
index 05af4d107421..10fd21517281 100644
--- a/drivers/gpu/drm/tegra/nvdec.c
+++ b/drivers/gpu/drm/tegra/nvdec.c
@@ -8,6 +8,7 @@
#include <linux/dma-mapping.h>
#include <linux/host1x.h>
#include <linux/iommu.h>
+#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
@@ -16,18 +17,21 @@
#include <linux/pm_runtime.h>
#include <linux/reset.h>
-#include <soc/tegra/pmc.h>
+#include <soc/tegra/mc.h>
#include "drm.h"
#include "falcon.h"
+#include "riscv.h"
#include "vic.h"
+#define NVDEC_FALCON_DEBUGINFO 0x1094
#define NVDEC_TFBIF_TRANSCFG 0x2c44
struct nvdec_config {
const char *firmware;
unsigned int version;
bool supports_sid;
+ bool has_riscv;
bool has_extra_clocks;
};
@@ -40,9 +44,14 @@ struct nvdec {
struct device *dev;
struct clk_bulk_data clks[3];
unsigned int num_clks;
+ struct reset_control *reset;
/* Platform configuration */
const struct nvdec_config *config;
+
+ /* RISC-V specific data */
+ struct tegra_drm_riscv riscv;
+ phys_addr_t carveout_base;
};
static inline struct nvdec *to_nvdec(struct tegra_drm_client *client)
@@ -56,7 +65,7 @@ static inline void nvdec_writel(struct nvdec *nvdec, u32 value,
writel(value, nvdec->regs + offset);
}
-static int nvdec_boot(struct nvdec *nvdec)
+static int nvdec_boot_falcon(struct nvdec *nvdec)
{
#ifdef CONFIG_IOMMU_API
struct iommu_fwspec *spec = dev_iommu_fwspec_get(nvdec->dev);
@@ -92,6 +101,64 @@ static int nvdec_boot(struct nvdec *nvdec)
return 0;
}
+static int nvdec_wait_debuginfo(struct nvdec *nvdec, const char *phase)
+{
+ int err;
+ u32 val;
+
+ err = readl_poll_timeout(nvdec->regs + NVDEC_FALCON_DEBUGINFO, val, val == 0x0, 10, 100000);
+ if (err) {
+ dev_err(nvdec->dev, "failed to boot %s, debuginfo=0x%x\n", phase, val);
+ return err;
+ }
+
+ return 0;
+}
+
+static int nvdec_boot_riscv(struct nvdec *nvdec)
+{
+ int err;
+
+ err = reset_control_acquire(nvdec->reset);
+ if (err)
+ return err;
+
+ nvdec_writel(nvdec, 0xabcd1234, NVDEC_FALCON_DEBUGINFO);
+
+ err = tegra_drm_riscv_boot_bootrom(&nvdec->riscv, nvdec->carveout_base, 1,
+ &nvdec->riscv.bl_desc);
+ if (err) {
+ dev_err(nvdec->dev, "failed to execute bootloader\n");
+ goto release_reset;
+ }
+
+ err = nvdec_wait_debuginfo(nvdec, "bootloader");
+ if (err)
+ goto release_reset;
+
+ err = reset_control_reset(nvdec->reset);
+ if (err)
+ goto release_reset;
+
+ nvdec_writel(nvdec, 0xabcd1234, NVDEC_FALCON_DEBUGINFO);
+
+ err = tegra_drm_riscv_boot_bootrom(&nvdec->riscv, nvdec->carveout_base, 1,
+ &nvdec->riscv.os_desc);
+ if (err) {
+ dev_err(nvdec->dev, "failed to execute firmware\n");
+ goto release_reset;
+ }
+
+ err = nvdec_wait_debuginfo(nvdec, "firmware");
+ if (err)
+ goto release_reset;
+
+release_reset:
+ reset_control_release(nvdec->reset);
+
+ return err;
+}
+
static int nvdec_init(struct host1x_client *client)
{
struct tegra_drm_client *drm = host1x_to_drm_client(client);
@@ -191,7 +258,7 @@ static const struct host1x_client_ops nvdec_client_ops = {
.exit = nvdec_exit,
};
-static int nvdec_load_firmware(struct nvdec *nvdec)
+static int nvdec_load_falcon_firmware(struct nvdec *nvdec)
{
struct host1x_client *client = &nvdec->client.base;
struct tegra_drm *tegra = nvdec->client.drm;
@@ -254,7 +321,6 @@ static int nvdec_load_firmware(struct nvdec *nvdec)
return err;
}
-
static __maybe_unused int nvdec_runtime_resume(struct device *dev)
{
struct nvdec *nvdec = dev_get_drvdata(dev);
@@ -266,13 +332,19 @@ static __maybe_unused int nvdec_runtime_resume(struct device *dev)
usleep_range(10, 20);
- err = nvdec_load_firmware(nvdec);
- if (err < 0)
- goto disable;
+ if (nvdec->config->has_riscv) {
+ err = nvdec_boot_riscv(nvdec);
+ if (err < 0)
+ goto disable;
+ } else {
+ err = nvdec_load_falcon_firmware(nvdec);
+ if (err < 0)
+ goto disable;
- err = nvdec_boot(nvdec);
- if (err < 0)
- goto disable;
+ err = nvdec_boot_falcon(nvdec);
+ if (err < 0)
+ goto disable;
+ }
return 0;
@@ -348,10 +420,18 @@ static const struct nvdec_config nvdec_t194_config = {
.supports_sid = true,
};
+static const struct nvdec_config nvdec_t234_config = {
+ .version = 0x23,
+ .supports_sid = true,
+ .has_riscv = true,
+ .has_extra_clocks = true,
+};
+
static const struct of_device_id tegra_nvdec_of_match[] = {
{ .compatible = "nvidia,tegra210-nvdec", .data = &nvdec_t210_config },
{ .compatible = "nvidia,tegra186-nvdec", .data = &nvdec_t186_config },
{ .compatible = "nvidia,tegra194-nvdec", .data = &nvdec_t194_config },
+ { .compatible = "nvidia,tegra234-nvdec", .data = &nvdec_t234_config },
{ },
};
MODULE_DEVICE_TABLE(of, tegra_nvdec_of_match);
@@ -410,12 +490,42 @@ static int nvdec_probe(struct platform_device *pdev)
if (err < 0)
host_class = HOST1X_CLASS_NVDEC;
- nvdec->falcon.dev = dev;
- nvdec->falcon.regs = nvdec->regs;
+ if (nvdec->config->has_riscv) {
+ struct tegra_mc *mc;
- err = falcon_init(&nvdec->falcon);
- if (err < 0)
- return err;
+ mc = devm_tegra_memory_controller_get(dev);
+ if (IS_ERR(mc)) {
+ dev_err_probe(dev, PTR_ERR(mc),
+ "failed to get memory controller handle\n");
+ return PTR_ERR(mc);
+ }
+
+ err = tegra_mc_get_carveout_info(mc, 1, &nvdec->carveout_base, NULL);
+ if (err) {
+ dev_err(dev, "failed to get carveout info: %d\n", err);
+ return err;
+ }
+
+ nvdec->reset = devm_reset_control_get_exclusive_released(dev, "nvdec");
+ if (IS_ERR(nvdec->reset)) {
+ dev_err_probe(dev, PTR_ERR(nvdec->reset), "failed to get reset\n");
+ return PTR_ERR(nvdec->reset);
+ }
+
+ nvdec->riscv.dev = dev;
+ nvdec->riscv.regs = nvdec->regs;
+
+ err = tegra_drm_riscv_read_descriptors(&nvdec->riscv);
+ if (err < 0)
+ return err;
+ } else {
+ nvdec->falcon.dev = dev;
+ nvdec->falcon.regs = nvdec->regs;
+
+ err = falcon_init(&nvdec->falcon);
+ if (err < 0)
+ return err;
+ }
platform_set_drvdata(pdev, nvdec);
--
2.37.0
From: Mikko Perttunen <[email protected]>
On Tegra234 NVDEC firmware is loaded from a secure carveout, where it
has been loaded by a bootloader. When booting NVDEC, we need to tell it
the address of this firmware, which we can determine by checking the
starting address of the carveout. As such, add an MC API to query the
bounds of carveouts, and add related information on Tegra234.
Signed-off-by: Mikko Perttunen <[email protected]>
---
drivers/memory/tegra/mc.c | 23 +++++++++++++++++++++++
drivers/memory/tegra/tegra234.c | 5 +++++
include/soc/tegra/mc.h | 11 +++++++++++
3 files changed, 39 insertions(+)
diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c
index 2f7a58a9df1a..4650300d3ec3 100644
--- a/drivers/memory/tegra/mc.c
+++ b/drivers/memory/tegra/mc.c
@@ -107,6 +107,29 @@ int tegra_mc_probe_device(struct tegra_mc *mc, struct device *dev)
}
EXPORT_SYMBOL_GPL(tegra_mc_probe_device);
+int tegra_mc_get_carveout_info(struct tegra_mc *mc, unsigned int id,
+ phys_addr_t *base, u64 *size)
+{
+ u32 offset;
+
+ if (id < 1 || id >= mc->soc->num_carveouts)
+ return -EINVAL;
+
+ if (id < 6)
+ offset = 0xc0c + 0x50 * (id - 1);
+ else
+ offset = 0x2004 + 0x50 * (id - 6);
+
+ *base = mc_ch_readl(mc, MC_BROADCAST_CHANNEL, offset + 0x0);
+ *base |= (phys_addr_t)mc_ch_readl(mc, MC_BROADCAST_CHANNEL, offset + 0x4) << 32;
+
+ if (size)
+ *size = mc_ch_readl(mc, MC_BROADCAST_CHANNEL, offset + 0x8) << 17;
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(tegra_mc_get_carveout_info);
+
static int tegra_mc_block_dma_common(struct tegra_mc *mc,
const struct tegra_mc_reset *rst)
{
diff --git a/drivers/memory/tegra/tegra234.c b/drivers/memory/tegra/tegra234.c
index a9e8fd99730f..74d291d66366 100644
--- a/drivers/memory/tegra/tegra234.c
+++ b/drivers/memory/tegra/tegra234.c
@@ -187,4 +187,9 @@ const struct tegra_mc_soc tegra234_mc_soc = {
.ops = &tegra186_mc_ops,
.ch_intmask = 0x0000ff00,
.global_intstatus_channel_shift = 8,
+ /*
+ * Additionally, there are lite carveouts but those are not currently
+ * supported.
+ */
+ .num_carveouts = 32,
};
diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h
index 47ce6d434427..51a2263e1bc5 100644
--- a/include/soc/tegra/mc.h
+++ b/include/soc/tegra/mc.h
@@ -193,6 +193,8 @@ struct tegra_mc_soc {
unsigned int num_address_bits;
unsigned int atom_size;
+ unsigned int num_carveouts;
+
u16 client_id_mask;
u8 num_channels;
@@ -244,6 +246,8 @@ unsigned int tegra_mc_get_emem_device_count(struct tegra_mc *mc);
#ifdef CONFIG_TEGRA_MC
struct tegra_mc *devm_tegra_memory_controller_get(struct device *dev);
int tegra_mc_probe_device(struct tegra_mc *mc, struct device *dev);
+int tegra_mc_get_carveout_info(struct tegra_mc *mc, unsigned int id,
+ phys_addr_t *base, u64 *size);
#else
static inline struct tegra_mc *
devm_tegra_memory_controller_get(struct device *dev)
@@ -256,6 +260,13 @@ tegra_mc_probe_device(struct tegra_mc *mc, struct device *dev)
{
return -ENODEV;
}
+
+static inline int
+tegra_mc_get_carveout_info(struct tegra_mc *mc, unsigned int id,
+ phys_addr_t *base, u64 *size)
+{
+ return -ENODEV;
+}
#endif
#endif /* __SOC_TEGRA_MC_H__ */
--
2.37.0
From: Mikko Perttunen <[email protected]>
Update NVDEC bindings for Tegra234. This new engine version only has
two memory clients, but now requires three clocks, and as a bigger
change the engine loads firmware from a secure carveout configured by
the bootloader.
For the latter, we need to add a phandle to the memory controller
to query the location of this carveout, and several other properties
containing offsets into the firmware inside the carveout. These
properties are intended to be populated through a device tree overlay
configured at flashing time, so that the values correspond to the
flashed NVDEC firmware.
Signed-off-by: Mikko Perttunen <[email protected]>
---
.../gpu/host1x/nvidia,tegra210-nvdec.yaml | 118 +++++++++++++++---
1 file changed, 98 insertions(+), 20 deletions(-)
diff --git a/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvdec.yaml b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvdec.yaml
index 3cf862976448..27128a195b66 100644
--- a/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvdec.yaml
+++ b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvdec.yaml
@@ -24,17 +24,11 @@ properties:
- nvidia,tegra210-nvdec
- nvidia,tegra186-nvdec
- nvidia,tegra194-nvdec
+ - nvidia,tegra234-nvdec
reg:
maxItems: 1
- clocks:
- maxItems: 1
-
- clock-names:
- items:
- - const: nvdec
-
resets:
maxItems: 1
@@ -50,18 +44,6 @@ properties:
dma-coherent: true
- interconnects:
- items:
- - description: DMA read memory client
- - description: DMA read 2 memory client
- - description: DMA write memory client
-
- interconnect-names:
- items:
- - const: dma-mem
- - const: read-1
- - const: write
-
nvidia,host1x-class:
description: |
Host1x class of the engine, used to specify the targeted engine
@@ -79,7 +61,103 @@ required:
- reset-names
- power-domains
-additionalProperties: false
+unevaluatedProperties: false
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - nvidia,tegra234-nvdec
+ then:
+ properties:
+ clocks:
+ items:
+ - description: NVDEC clock
+ - description: FUSE clock
+ - description: TSEC_PKA clock
+ clock-names:
+ items:
+ - const: nvdec
+ - const: fuse
+ - const: tsec_pka
+ interconnects:
+ items:
+ - description: DMA read memory client
+ - description: DMA write memory client
+ interconnect-names:
+ items:
+ - const: dma-mem
+ - const: write
+ nvidia,memory-controller:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ phandle to the memory controller for determining carveout information.
+ nvidia,bl-manifest-offset:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Offset to bootloader manifest from beginning of firmware. Typically set as
+ part of a device tree overlay corresponding to flashed firmware.
+ nvidia,bl-code-offset:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Offset to bootloader code section from beginning of firmware. Typically set as
+ part of a device tree overlay corresponding to flashed firmware.
+ nvidia,bl-data-offset:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Offset to bootloader data section from beginning of firmware. Typically set as
+ part of a device tree overlay corresponding to flashed firmware.
+ nvidia,os-manifest-offset:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Offset to operating system manifest from beginning of firmware. Typically set as
+ part of a device tree overlay corresponding to flashed firmware.
+ nvidia,os-code-offset:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Offset to operating system code section from beginning of firmware. Typically set as
+ part of a device tree overlay corresponding to flashed firmware.
+ nvidia,os-data-offset:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Offset to operating system data section from beginning of firmware. Typically set as
+ part of a device tree overlay corresponding to flashed firmware.
+ required:
+ - nvidia,memory-controller
+ - nvidia,bl-manifest-offset
+ - nvidia,bl-code-offset
+ - nvidia,bl-data-offset
+ - nvidia,os-manifest-offset
+ - nvidia,os-code-offset
+ - nvidia,os-data-offset
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - nvidia,tegra210-nvdec
+ - nvidia,tegra186-nvdec
+ - nvidia,tegra194-nvdec
+ then:
+ properties:
+ clocks:
+ items:
+ - description: NVDEC clock
+ clock-names:
+ items:
+ - const: nvdec
+ interconnects:
+ items:
+ - description: DMA read memory client
+ - description: DMA read 2 memory client
+ - description: DMA write memory client
+ interconnect-names:
+ items:
+ - const: dma-mem
+ - const: read-1
+ - const: write
examples:
- |
--
2.37.0
From: Mikko Perttunen <[email protected]>
Add entries for NVDEC to the Tegra234 SID table.
Signed-off-by: Mikko Perttunen <[email protected]>
---
drivers/gpu/host1x/dev.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/host1x/dev.c b/drivers/gpu/host1x/dev.c
index 0cd3f97e7e49..d6b4614f968f 100644
--- a/drivers/gpu/host1x/dev.c
+++ b/drivers/gpu/host1x/dev.c
@@ -225,6 +225,18 @@ static const struct host1x_sid_entry tegra234_sid_table[] = {
.offset = 0x34,
.limit = 0x34
},
+ {
+ /* NVDEC channel */
+ .base = 0x17c8,
+ .offset = 0x30,
+ .limit = 0x30,
+ },
+ {
+ /* NVDEC MMIO */
+ .base = 0x1698,
+ .offset = 0x34,
+ .limit = 0x34,
+ },
};
static const struct host1x_info host1x08_info = {
--
2.37.0
Hi Mikko,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on robh/for-next]
[also build test WARNING on clk/clk-next krzk-mem-ctrl/for-next pza/reset/next linus/master v6.0-rc4 next-20220906]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Mikko-Perttunen/Support-for-NVDEC-on-Tegra234/20220906-215151
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: powerpc-allyesconfig (https://download.01.org/0day-ci/archive/20220906/[email protected]/config)
compiler: powerpc-linux-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/intel-lab-lkp/linux/commit/7e2bd1173420c8e09ec90e3322e059a7350482e3
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Mikko-Perttunen/Support-for-NVDEC-on-Tegra234/20220906-215151
git checkout 7e2bd1173420c8e09ec90e3322e059a7350482e3
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=powerpc SHELL=/bin/bash drivers/memory/tegra/
If you fix the issue, kindly add following tag where applicable
Reported-by: kernel test robot <[email protected]>
All warnings (new ones prefixed by >>):
drivers/memory/tegra/mc.c: In function 'tegra_mc_get_carveout_info':
>> drivers/memory/tegra/mc.c:124:83: warning: left shift count >= width of type [-Wshift-count-overflow]
124 | *base |= (phys_addr_t)mc_ch_readl(mc, MC_BROADCAST_CHANNEL, offset + 0x4) << 32;
| ^~
vim +124 drivers/memory/tegra/mc.c
109
110 int tegra_mc_get_carveout_info(struct tegra_mc *mc, unsigned int id,
111 phys_addr_t *base, u64 *size)
112 {
113 u32 offset;
114
115 if (id < 1 || id >= mc->soc->num_carveouts)
116 return -EINVAL;
117
118 if (id < 6)
119 offset = 0xc0c + 0x50 * (id - 1);
120 else
121 offset = 0x2004 + 0x50 * (id - 6);
122
123 *base = mc_ch_readl(mc, MC_BROADCAST_CHANNEL, offset + 0x0);
> 124 *base |= (phys_addr_t)mc_ch_readl(mc, MC_BROADCAST_CHANNEL, offset + 0x4) << 32;
125
126 if (size)
127 *size = mc_ch_readl(mc, MC_BROADCAST_CHANNEL, offset + 0x8) << 17;
128
129 return 0;
130 }
131 EXPORT_SYMBOL_GPL(tegra_mc_get_carveout_info);
132
--
0-DAY CI Kernel Test Service
https://01.org/lkp
On 06/09/2022 15:28, Mikko Perttunen wrote:
> From: Mikko Perttunen <[email protected]>
>
> Hi all,
>
> this series adds support for the HW video decoder, NVDEC,
> on Tegra234 (Orin). The main change is a switch from Falcon
> to RISC-V for the internal microcontroller, which brings along
> a change in how the engine is booted. Otherwise it is backwards
> compatible with earlier versions.
You need to describe the dependencies, otherwise I would be free to go
with applying memory controllers part.
Best regards,
Krzysztof
Hi Mikko,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on robh/for-next]
[also build test WARNING on clk/clk-next krzk-mem-ctrl/for-next pza/reset/next linus/master v6.0-rc4 next-20220906]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Mikko-Perttunen/Support-for-NVDEC-on-Tegra234/20220906-215151
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: mips-randconfig-r026-20220906
compiler: clang version 16.0.0 (https://github.com/llvm/llvm-project c55b41d5199d2394dd6cdb8f52180d8b81d809d4)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install mips cross compiling tool for clang build
# apt-get install binutils-mipsel-linux-gnu
# https://github.com/intel-lab-lkp/linux/commit/7e2bd1173420c8e09ec90e3322e059a7350482e3
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Mikko-Perttunen/Support-for-NVDEC-on-Tegra234/20220906-215151
git checkout 7e2bd1173420c8e09ec90e3322e059a7350482e3
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=mips SHELL=/bin/bash drivers/memory/tegra/
If you fix the issue, kindly add following tag where applicable
Reported-by: kernel test robot <[email protected]>
All warnings (new ones prefixed by >>):
>> drivers/memory/tegra/mc.c:124:76: warning: shift count >= width of type [-Wshift-count-overflow]
*base |= (phys_addr_t)mc_ch_readl(mc, MC_BROADCAST_CHANNEL, offset + 0x4) << 32;
^ ~~
1 warning generated.
vim +124 drivers/memory/tegra/mc.c
109
110 int tegra_mc_get_carveout_info(struct tegra_mc *mc, unsigned int id,
111 phys_addr_t *base, u64 *size)
112 {
113 u32 offset;
114
115 if (id < 1 || id >= mc->soc->num_carveouts)
116 return -EINVAL;
117
118 if (id < 6)
119 offset = 0xc0c + 0x50 * (id - 1);
120 else
121 offset = 0x2004 + 0x50 * (id - 6);
122
123 *base = mc_ch_readl(mc, MC_BROADCAST_CHANNEL, offset + 0x0);
> 124 *base |= (phys_addr_t)mc_ch_readl(mc, MC_BROADCAST_CHANNEL, offset + 0x4) << 32;
125
126 if (size)
127 *size = mc_ch_readl(mc, MC_BROADCAST_CHANNEL, offset + 0x8) << 17;
128
129 return 0;
130 }
131 EXPORT_SYMBOL_GPL(tegra_mc_get_carveout_info);
132
--
0-DAY CI Kernel Test Service
https://01.org/lkp
On 9/6/22 20:50, Krzysztof Kozlowski wrote:
> On 06/09/2022 15:28, Mikko Perttunen wrote:
>> From: Mikko Perttunen <[email protected]>
>>
>> Hi all,
>>
>> this series adds support for the HW video decoder, NVDEC,
>> on Tegra234 (Orin). The main change is a switch from Falcon
>> to RISC-V for the internal microcontroller, which brings along
>> a change in how the engine is booted. Otherwise it is backwards
>> compatible with earlier versions.
>
> You need to describe the dependencies, otherwise I would be free to go
> with applying memory controllers part.
Hi Krzysztof,
the memory controller patch can be applied independently.
Thanks,
Mikko
>
> Best regards,
> Krzysztof
On 7.9.2022 13.58, Krzysztof Kozlowski wrote:
> On 07/09/2022 07:27, Mikko Perttunen wrote:
>> On 9/6/22 20:50, Krzysztof Kozlowski wrote:
>>> On 06/09/2022 15:28, Mikko Perttunen wrote:
>>>> From: Mikko Perttunen <[email protected]>
>>>>
>>>> Hi all,
>>>>
>>>> this series adds support for the HW video decoder, NVDEC,
>>>> on Tegra234 (Orin). The main change is a switch from Falcon
>>>> to RISC-V for the internal microcontroller, which brings along
>>>> a change in how the engine is booted. Otherwise it is backwards
>>>> compatible with earlier versions.
>>>
>>> You need to describe the dependencies, otherwise I would be free to go
>>> with applying memory controllers part.
>>
>> Hi Krzysztof,
>>
>> the memory controller patch can be applied independently.
>
> OK then... but looking at the code it does not seem to. Anyway kbuild
> robot complained so I expect v2.
Ah, indeed, though patch 1 can be applied on top of current trees, patch
8 does require patch 1 to be there first. Which is, thinking about it
now, necessary information as well..
Thanks for the reviews.
Mikko
>
> Best regards,
> Krzysztof
On 07/09/2022 07:27, Mikko Perttunen wrote:
> On 9/6/22 20:50, Krzysztof Kozlowski wrote:
>> On 06/09/2022 15:28, Mikko Perttunen wrote:
>>> From: Mikko Perttunen <[email protected]>
>>>
>>> Hi all,
>>>
>>> this series adds support for the HW video decoder, NVDEC,
>>> on Tegra234 (Orin). The main change is a switch from Falcon
>>> to RISC-V for the internal microcontroller, which brings along
>>> a change in how the engine is booted. Otherwise it is backwards
>>> compatible with earlier versions.
>>
>> You need to describe the dependencies, otherwise I would be free to go
>> with applying memory controllers part.
>
> Hi Krzysztof,
>
> the memory controller patch can be applied independently.
OK then... but looking at the code it does not seem to. Anyway kbuild
robot complained so I expect v2.
Best regards,
Krzysztof
On 06/09/2022 15:28, Mikko Perttunen wrote:
> From: Mikko Perttunen <[email protected]>
>
> Update NVDEC bindings for Tegra234. This new engine version only has
> two memory clients, but now requires three clocks, and as a bigger
> change the engine loads firmware from a secure carveout configured by
> the bootloader.
>
> For the latter, we need to add a phandle to the memory controller
> to query the location of this carveout, and several other properties
> containing offsets into the firmware inside the carveout. These
> properties are intended to be populated through a device tree overlay
> configured at flashing time, so that the values correspond to the
> flashed NVDEC firmware.
>
> Signed-off-by: Mikko Perttunen <[email protected]>
> ---
> .../gpu/host1x/nvidia,tegra210-nvdec.yaml | 118 +++++++++++++++---
> 1 file changed, 98 insertions(+), 20 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvdec.yaml b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvdec.yaml
> index 3cf862976448..27128a195b66 100644
> --- a/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvdec.yaml
> +++ b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvdec.yaml
> @@ -24,17 +24,11 @@ properties:
> - nvidia,tegra210-nvdec
> - nvidia,tegra186-nvdec
> - nvidia,tegra194-nvdec
> + - nvidia,tegra234-nvdec
>
> reg:
> maxItems: 1
>
> - clocks:
> - maxItems: 1
> -
> - clock-names:
> - items:
> - - const: nvdec
Please leave them here with wide constraints (min/maxItems).
> -
> resets:
> maxItems: 1
>
> @@ -50,18 +44,6 @@ properties:
>
> dma-coherent: true
>
> - interconnects:
> - items:
> - - description: DMA read memory client
> - - description: DMA read 2 memory client
> - - description: DMA write memory client
> -
> - interconnect-names:
> - items:
> - - const: dma-mem
> - - const: read-1
> - - const: write
Please leave them here with wide constraints (min/maxItems).
> -
> nvidia,host1x-class:
> description: |
> Host1x class of the engine, used to specify the targeted engine
> @@ -79,7 +61,103 @@ required:
> - reset-names
> - power-domains
>
> -additionalProperties: false
> +unevaluatedProperties: false
This looks not needed/related.
> +
> +allOf:
Put allOf before additionalProperties:false.
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - nvidia,tegra234-nvdec
> + then:
> + properties:
> + clocks:
> + items:
> + - description: NVDEC clock
> + - description: FUSE clock
> + - description: TSEC_PKA clock
> + clock-names:
> + items:
> + - const: nvdec
> + - const: fuse
> + - const: tsec_pka
> + interconnects:
> + items:
> + - description: DMA read memory client
> + - description: DMA write memory client
> + interconnect-names:
> + items:
> + - const: dma-mem
> + - const: write
> + nvidia,memory-controller:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description:
> + phandle to the memory controller for determining carveout information.
All fields should be defined in top-level. You can disallow them for
other variants, but if the allOf:if:then gets too big, it's a sign to
split the binding.
> + nvidia,bl-manifest-offset:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + Offset to bootloader manifest from beginning of firmware. Typically set as
> + part of a device tree overlay corresponding to flashed firmware.
> + nvidia,bl-code-offset:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + Offset to bootloader code section from beginning of firmware. Typically set as
> + part of a device tree overlay corresponding to flashed firmware.
> + nvidia,bl-data-offset:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + Offset to bootloader data section from beginning of firmware. Typically set as
> + part of a device tree overlay corresponding to flashed firmware.
> + nvidia,os-manifest-offset:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + Offset to operating system manifest from beginning of firmware. Typically set as
> + part of a device tree overlay corresponding to flashed firmware.
> + nvidia,os-code-offset:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + Offset to operating system code section from beginning of firmware. Typically set as
> + part of a device tree overlay corresponding to flashed firmware.
> + nvidia,os-data-offset:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + Offset to operating system data section from beginning of firmware. Typically set as
> + part of a device tree overlay corresponding to flashed firmware.
> + required:
> + - nvidia,memory-controller
> + - nvidia,bl-manifest-offset
> + - nvidia,bl-code-offset
> + - nvidia,bl-data-offset
> + - nvidia,os-manifest-offset
> + - nvidia,os-code-offset
> + - nvidia,os-data-offset
blank line
> + - if:
> + properties:
> + compatible:
> + contains:
Best regards,
Krzysztof