From: Aswath Govindraju <[email protected]>
Add support for single instance of USB 3.0 controller in J721S2 SoC.
Cc: Vignesh Raghavendra <[email protected]>
Cc: Nishanth Menon <[email protected]>
Acked-by: Matt Ranostay <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
---
arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 42 ++++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
index 34e7d577ae13..1f178ad3fa42 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
@@ -26,6 +26,20 @@ l3cache-sram@200000 {
};
};
+ scm_conf: syscon@104000 {
+ compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
+ reg = <0x00 0x00104000 0x00 0x18000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00 0x00 0x00104000 0x18000>;
+
+ usb_serdes_mux: mux-controller-0 {
+ compatible = "mmio-mux";
+ #mux-control-cells = <1>;
+ mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
+ };
+ };
+
gic500: interrupt-controller@1800000 {
compatible = "arm,gic-v3";
#address-cells = <2>;
@@ -686,6 +700,34 @@ cpts@310d0000 {
};
};
+ usbss0: cdns-usb@4104000 {
+ compatible = "ti,j721e-usb";
+ reg = <0x00 0x04104000 0x00 0x100>;
+ clocks = <&k3_clks 360 16>, <&k3_clks 360 15>;
+ clock-names = "ref", "lpm";
+ assigned-clocks = <&k3_clks 360 16>; /* USB2_REFCLK */
+ assigned-clock-parents = <&k3_clks 360 17>;
+ power-domains = <&k3_pds 360 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ dma-coherent;
+
+ usb0: usb@6000000 {
+ compatible = "cdns,usb3";
+ reg = <0x00 0x06000000 0x00 0x10000>,
+ <0x00 0x06010000 0x00 0x10000>,
+ <0x00 0x06020000 0x00 0x10000>;
+ reg-names = "otg", "xhci", "dev";
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "host", "peripheral", "otg";
+ maximum-speed = "super-speed";
+ dr_mode = "otg";
+ };
+ };
+
main_mcan0: can@2701000 {
compatible = "bosch,m_can";
reg = <0x00 0x02701000 0x00 0x200>,
--
2.30.2
From: Aswath Govindraju <[email protected]>
Add dt node for the single instance of WIZ (SERDES wrapper) and
SERDES module shared by PCIe, eDP and USB.
Cc: Vignesh Raghavendra <[email protected]>
Cc: Nishanth Menon <[email protected]>
Acked-by: Matt Ranostay <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
---
arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 70 ++++++++++++++++++++++
1 file changed, 70 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
index 1f178ad3fa42..6ca36f9075a5 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
@@ -5,6 +5,13 @@
* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
*/
+/ {
+ serdes_refclk: clock-cmnrefclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ };
+};
+
&cbass_main {
msmc_ram: sram@70000000 {
compatible = "mmio-sram";
@@ -38,6 +45,13 @@ usb_serdes_mux: mux-controller-0 {
#mux-control-cells = <1>;
mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
};
+
+ serdes_ln_ctrl: mux-controller-80 {
+ compatible = "mmio-mux";
+ #mux-control-cells = <1>;
+ mux-reg-masks = <0x80 0x3>, <0x84 0x3>, /* SERDES0 lane0/1 select */
+ <0x88 0x3>, <0x8c 0x3>; /* SERDES0 lane2/3 select */
+ };
};
gic500: interrupt-controller@1800000 {
@@ -728,6 +742,62 @@ usb0: usb@6000000 {
};
};
+ serdes_wiz0: wiz@5060000 {
+ compatible = "ti,j721e-wiz-10g";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ power-domains = <&k3_pds 365 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 365 0>, <&k3_clks 365 3>, <&serdes_refclk>;
+ clock-names = "fck", "core_ref_clk", "ext_ref_clk";
+ num-lanes = <4>;
+ #reset-cells = <1>;
+ ranges = <0x5060000 0x0 0x5060000 0x10000>;
+
+ assigned-clocks = <&k3_clks 365 3>;
+ assigned-clock-parents = <&k3_clks 365 7>;
+
+ wiz0_pll0_refclk: clock-refpll0 {
+ clocks = <&k3_clks 365 3>, <&serdes_refclk>;
+ clock-output-names = "wiz0_pll0_refclk";
+ #clock-cells = <0>;
+ assigned-clocks = <&wiz0_pll0_refclk>;
+ assigned-clock-parents = <&k3_clks 365 3>;
+ };
+
+ wiz0_pll1_refclk: clock-refpll1 {
+ clocks = <&k3_clks 365 3>, <&serdes_refclk>;
+ clock-output-names = "wiz0_pll1_refclk";
+ #clock-cells = <0>;
+ assigned-clocks = <&wiz0_pll1_refclk>;
+ assigned-clock-parents = <&k3_clks 365 3>;
+ };
+
+ wiz0_refclk_dig: clock-refdig {
+ clocks = <&k3_clks 365 3>, <&serdes_refclk>;
+ clock-output-names = "wiz0_refclk_dig";
+ #clock-cells = <0>;
+ assigned-clocks = <&wiz0_refclk_dig>;
+ assigned-clock-parents = <&k3_clks 365 3>;
+ };
+
+ wiz0_cmn_refclk_dig_div: clock-cmnref-dig-div {
+ clocks = <&wiz0_refclk_dig>;
+ #clock-cells = <0>;
+ };
+
+ serdes0: serdes@5060000 {
+ compatible = "ti,j721e-serdes-10g";
+ reg = <0x05060000 0x00010000>;
+ reg-names = "torrent_phy";
+ resets = <&serdes_wiz0 0>;
+ reset-names = "torrent_reset";
+ clocks = <&wiz0_pll0_refclk>;
+ clock-names = "refclk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
main_mcan0: can@2701000 {
compatible = "bosch,m_can";
reg = <0x00 0x02701000 0x00 0x200>,
--
2.30.2