v2 updates:
- Use MACROs for interrupts and gpio property
Hou Zhiqiang (2):
arm64: dts: ls1043a: Add SCFG phandle for PCIe nodes
arm64: dts: ls1043a: Add big-endian property for PCIe nodes
Laurentiu Tudor (2):
arm64: dts: ls1043a: add missing dma ranges property
arm64: dts: ls1043a: use a pseudo-bus to constrain usb and sata dma
size
Li Yang (7):
arm64: dts: ls1043a: fix the wrong size of dcfg space
arm64: dts: ls1043a: Enable usb3-lpm-capable for usb3 node
arm64: dts: ls1043a: use pcie aer/pme interrupts
arm64: dts: ls1043a: make dma-coherent global to the SoC
arm64: dts: ls1043a: add gpio based i2c recovery information
arm64: dts: ls1043a-qds: add mmio based mdio-mux support
arm64: dts: ls1043a-rdb: add pcf85263 rtc node
.../boot/dts/freescale/fsl-ls1043a-qds.dts | 173 +++++++++++++++++-
.../boot/dts/freescale/fsl-ls1043a-rdb.dts | 10 +
.../arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 132 +++++++------
3 files changed, 257 insertions(+), 58 deletions(-)
--
2.37.1
Add the missing node for rtc device under i2c and fix style problems at
the same time.
Signed-off-by: Li Yang <[email protected]>
---
arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
index b290605e92cf..26f8540cb101 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
@@ -29,23 +29,33 @@ chosen {
&i2c0 {
status = "okay";
+
ina220@40 {
compatible = "ti,ina220";
reg = <0x40>;
shunt-resistor = <1000>;
};
+
adt7461a@4c {
compatible = "adi,adt7461";
reg = <0x4c>;
};
+
+ rtc@51 {
+ compatible = "nxp,pcf85263";
+ reg = <0x51>;
+ };
+
eeprom@52 {
compatible = "atmel,24c512";
reg = <0x52>;
};
+
eeprom@53 {
compatible = "atmel,24c512";
reg = <0x53>;
};
+
rtc@68 {
compatible = "pericom,pt7c4338";
reg = <0x68>;
--
2.37.1
There is mmio based mdio mux function in the FPGA device on ls1043a-qds
board. Add the mmio based mdio-mux nodes to ls1043a-qds boards and
add simple-mfd as a compatbile for the FPGA node to reflect the
multi-function nature of it. Also connect the ethernet interfaces to
these phy interfaces.
Signed-off-by: Li Yang <[email protected]>
---
.../boot/dts/freescale/fsl-ls1043a-qds.dts | 173 +++++++++++++++++-
1 file changed, 171 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
index fea167d222cf..9b726c2a4842 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
@@ -3,7 +3,7 @@
* Device Tree Include file for Freescale Layerscape-1043A family SoC.
*
* Copyright 2014-2015 Freescale Semiconductor, Inc.
- * Copyright 2018 NXP
+ * Copyright 2018-2021 NXP
*
* Mingkai Hu <[email protected]>
*/
@@ -24,6 +24,22 @@ aliases {
serial1 = &duart1;
serial2 = &duart2;
serial3 = &duart3;
+ sgmii-riser-s1-p1 = &sgmii_phy_s1_p1;
+ sgmii-riser-s2-p1 = &sgmii_phy_s2_p1;
+ sgmii-riser-s3-p1 = &sgmii_phy_s3_p1;
+ sgmii-riser-s4-p1 = &sgmii_phy_s4_p1;
+ qsgmii-s1-p1 = &qsgmii_phy_s1_p1;
+ qsgmii-s1-p2 = &qsgmii_phy_s1_p2;
+ qsgmii-s1-p3 = &qsgmii_phy_s1_p3;
+ qsgmii-s1-p4 = &qsgmii_phy_s1_p4;
+ qsgmii-s2-p1 = &qsgmii_phy_s2_p1;
+ qsgmii-s2-p2 = &qsgmii_phy_s2_p2;
+ qsgmii-s2-p3 = &qsgmii_phy_s2_p3;
+ qsgmii-s2-p4 = &qsgmii_phy_s2_p4;
+ emi1-slot1 = &ls1043mdio_s1;
+ emi1-slot2 = &ls1043mdio_s2;
+ emi1-slot3 = &ls1043mdio_s3;
+ emi1-slot4 = &ls1043mdio_s4;
};
chosen {
@@ -62,8 +78,11 @@ nand@1,0 {
};
fpga: board-control@2,0 {
- compatible = "fsl,ls1043aqds-fpga", "fsl,fpga-qixis";
+ compatible = "fsl,ls1043aqds-fpga", "fsl,fpga-qixis", "simple-mfd";
reg = <0x2 0x0 0x0000100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 2 0 0x100>;
};
};
@@ -153,3 +172,153 @@ &usb0 {
};
#include "fsl-ls1043-post.dtsi"
+
+&fman0 {
+ ethernet@e0000 {
+ phy-handle = <&qsgmii_phy_s2_p1>;
+ phy-connection-type = "sgmii";
+ };
+
+ ethernet@e2000 {
+ phy-handle = <&qsgmii_phy_s2_p2>;
+ phy-connection-type = "sgmii";
+ };
+
+ ethernet@e4000 {
+ phy-handle = <&rgmii_phy1>;
+ phy-connection-type = "rgmii";
+ };
+
+ ethernet@e6000 {
+ phy-handle = <&rgmii_phy2>;
+ phy-connection-type = "rgmii";
+ };
+
+ ethernet@e8000 {
+ phy-handle = <&qsgmii_phy_s2_p3>;
+ phy-connection-type = "sgmii";
+ };
+
+ ethernet@ea000 {
+ phy-handle = <&qsgmii_phy_s2_p4>;
+ phy-connection-type = "sgmii";
+ };
+
+ ethernet@f0000 { /* DTSEC9/10GEC1 */
+ fixed-link = <1 1 10000 0 0>;
+ phy-connection-type = "xgmii";
+ };
+};
+
+&fpga {
+ mdio-mux-emi1@54 {
+ compatible = "mdio-mux-mmioreg", "mdio-mux";
+ mdio-parent-bus = <&mdio0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x54 1>; /* BRDCFG4 */
+ mux-mask = <0xe0>; /* EMI1 */
+
+ /* On-board RGMII1 PHY */
+ ls1043mdio0: mdio@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rgmii_phy1: ethernet-phy@1 { /* MAC3 */
+ reg = <0x1>;
+ };
+ };
+
+ /* On-board RGMII2 PHY */
+ ls1043mdio1: mdio@20 {
+ reg = <0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rgmii_phy2: ethernet-phy@2 { /* MAC4 */
+ reg = <0x2>;
+ };
+ };
+
+ /* Slot 1 */
+ ls1043mdio_s1: mdio@40 {
+ reg = <0x40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ qsgmii_phy_s1_p1: ethernet-phy@4 {
+ reg = <0x4>;
+ };
+
+ qsgmii_phy_s1_p2: ethernet-phy@5 {
+ reg = <0x5>;
+ };
+
+ qsgmii_phy_s1_p3: ethernet-phy@6 {
+ reg = <0x6>;
+ };
+
+ qsgmii_phy_s1_p4: ethernet-phy@7 {
+ reg = <0x7>;
+ };
+
+ sgmii_phy_s1_p1: ethernet-phy@1c {
+ reg = <0x1c>;
+ };
+ };
+
+ /* Slot 2 */
+ ls1043mdio_s2: mdio@60 {
+ reg = <0x60>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ qsgmii_phy_s2_p1: ethernet-phy@8 {
+ reg = <0x8>;
+ };
+
+ qsgmii_phy_s2_p2: ethernet-phy@9 {
+ reg = <0x9>;
+ };
+
+ qsgmii_phy_s2_p3: ethernet-phy@a {
+ reg = <0xa>;
+ };
+
+ qsgmii_phy_s2_p4: ethernet-phy@b {
+ reg = <0xb>;
+ };
+
+ sgmii_phy_s2_p1: ethernet-phy@1c {
+ reg = <0x1c>;
+ };
+ };
+
+ /* Slot 3 */
+ ls1043mdio_s3: mdio@80 {
+ reg = <0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ sgmii_phy_s3_p1: ethernet-phy@1c {
+ reg = <0x1c>;
+ };
+ };
+
+ /* Slot 4 */
+ ls1043mdio_s4: mdio@a0 {
+ reg = <0xa0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ sgmii_phy_s4_p1: ethernet-phy@1c {
+ reg = <0x1c>;
+ };
+ };
+ };
+};
--
2.37.1
From: Hou Zhiqiang <[email protected]>
Add the big-endian property for LS1043A PCIe nodes for accessing PEX_LUT
and PF register block.
Signed-off-by: Hou Zhiqiang <[email protected]>
Signed-off-by: Li Yang <[email protected]>
---
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index e1c5d685a9e3..3cf6722e7555 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -902,6 +902,7 @@ pcie1: pcie@3400000 {
<0000 0 0 3 &gic 0 112 0x4>,
<0000 0 0 4 &gic 0 113 0x4>;
fsl,pcie-scfg = <&scfg 0>;
+ big-endian;
status = "disabled";
};
@@ -929,6 +930,7 @@ pcie2: pcie@3500000 {
<0000 0 0 3 &gic 0 122 0x4>,
<0000 0 0 4 &gic 0 123 0x4>;
fsl,pcie-scfg = <&scfg 1>;
+ big-endian;
status = "disabled";
};
@@ -956,6 +958,7 @@ pcie3: pcie@3600000 {
<0000 0 0 3 &gic 0 156 0x4>,
<0000 0 0 4 &gic 0 157 0x4>;
fsl,pcie-scfg = <&scfg 2>;
+ big-endian;
status = "disabled";
};
--
2.37.1
On Wed, Sep 14, 2022 at 04:46:52PM -0500, Li Yang wrote:
> v2 updates:
> - Use MACROs for interrupts and gpio property
>
> Hou Zhiqiang (2):
> arm64: dts: ls1043a: Add SCFG phandle for PCIe nodes
> arm64: dts: ls1043a: Add big-endian property for PCIe nodes
>
> Laurentiu Tudor (2):
> arm64: dts: ls1043a: add missing dma ranges property
> arm64: dts: ls1043a: use a pseudo-bus to constrain usb and sata dma
> size
>
> Li Yang (7):
> arm64: dts: ls1043a: fix the wrong size of dcfg space
> arm64: dts: ls1043a: Enable usb3-lpm-capable for usb3 node
> arm64: dts: ls1043a: use pcie aer/pme interrupts
> arm64: dts: ls1043a: make dma-coherent global to the SoC
> arm64: dts: ls1043a: add gpio based i2c recovery information
> arm64: dts: ls1043a-qds: add mmio based mdio-mux support
> arm64: dts: ls1043a-rdb: add pcf85263 rtc node
Applied all, thanks!