This series add MediaTek dp-intf nodes and dp nodes.
This series is based on linux-next-20220914.
Bo-Chen Chen (4):
arm64: dts: mt8195: Add dp-intf nodes
arm64: dts: mt8195: Add dptx nodes
arm64: dts: mediatek: cherry: Add dp-intf ports
arm64: dts: mediatek: cherry: Add edptx and dptx support
.../boot/dts/mediatek/mt8195-cherry.dtsi | 86 +++++++++++++++++++
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 48 +++++++++++
2 files changed, 134 insertions(+)
--
2.18.0
Add dp-intf0 and dp-intf1 ports.
Signed-off-by: Bo-Chen Chen <[email protected]>
---
.../arm64/boot/dts/mediatek/mt8195-cherry.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
index 9b62e161db26..303dc32c64dc 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
@@ -120,6 +120,24 @@
};
};
+&dp_intf0 {
+ status = "okay";
+
+ port {
+ dp_intf0_out: endpoint {
+ };
+ };
+};
+
+&dp_intf1 {
+ status = "okay";
+
+ port {
+ dp_intf1_out: endpoint {
+ };
+ };
+};
+
&i2c0 {
status = "okay";
--
2.18.0
Il 15/09/22 09:58, Bo-Chen Chen ha scritto:
> Add dp-intf0 and dp-intf1 ports.
>
> Signed-off-by: Bo-Chen Chen <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Add dp-intf0 and dp-intf1 nodes for MT8195.
Signed-off-by: Bo-Chen Chen <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 905d1a90b406..93e6a106a9b8 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -2155,5 +2155,28 @@
clock-names = "apb", "smi", "gals";
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
};
+
+ dp_intf0: dp-intf@1c015000 {
+ status = "disabled";
+ compatible = "mediatek,mt8195-dp-intf";
+ reg = <0 0x1c015000 0 0x1000>;
+ interrupts = <GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys0 CLK_VDO0_DP_INTF0>,
+ <&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>,
+ <&apmixedsys CLK_APMIXED_TVDPLL1>;
+ clock-names = "engine", "pixel", "pll";
+ };
+
+ dp_intf1: dp-intf@1c113000 {
+ compatible = "mediatek,mt8195-dp-intf";
+ reg = <0 0x1c113000 0 0x1000>;
+ interrupts = <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ clocks = <&vdosys1 CLK_VDO1_DP_INTF0_MM>,
+ <&vdosys1 CLK_VDO1_DPINTF>,
+ <&apmixedsys CLK_APMIXED_TVDPLL2>;
+ clock-names = "engine", "pixel", "pll";
+ status = "disabled";
+ };
};
};
--
2.18.0