Hey all,
Some 6.1 targeted changes here.
Firstly, two new dev kits (one first-party & one from Aries Embedded).
They've been sitting in our vendor tree, so are being sent where they
belong.
Secondly, another release of our reference design for the Icicle kit
is due in September. Usually these do not really change much for the
devicetree, but this time around a pair of changes impact the memory
map.
The first of these is adding dma-ranges to the pcie controller. The
controller had some issues to begin with & with the current reference
design (v2022.05) would not work with mainline Linux nor has it since
reference design v2021.08. A combination of the property, a change
to the FPGA design & a small fix to the driver will get it working
with mainline again. The other non-backwards compatible change to the
reference design is moves of the peripherals instantiated in the
fabric. Currently they are fairly spread out & a common complaint has
been that this leaves little room in the fic3 section of the memory map
for custom peripherals without removing the existing ones.
This series depends on [0] so as not to add dtbs_check warnings. The
fabric clock support is added by [1].
Thanks,
Conor.
Changes since v4:
- fix the incompatible interrupts on m100pfsevp
Changes since v3:
- add an extra patch reducing the fic3 clock rate
Changes since v2:
- drop the sd & emmc versions of the aries devicetree
- remove a extra newline
Changes since v1:
- made the polarberry part of an enum in patch 1
0 - https://lore.kernel.org/linux-gpio/[email protected]/
1 - https://lore.kernel.org/linux-clk/[email protected]/
Conor Dooley (8):
dt-bindings: riscv: microchip: document icicle reference design
dt-bindings: riscv: microchip: document the aries m100pfsevp
riscv: dts: microchip: add pci dma ranges for the icicle kit
riscv: dts: microchip: move the mpfs' pci node to -fabric.dtsi
riscv: dts: microchip: icicle: update pci address properties
riscv: dts: microchip: icicle: re-jig fabric peripheral addresses
riscv: dts: microchip: reduce the fic3 clock rate
riscv: dts: microchip: add a devicetree for aries' m100pfsevp
Shravan Chippa (1):
dt-bindings: riscv: microchip: document the sev kit
Vattipalli Praveen (1):
riscv: dts: microchip: add sevkit device tree
.../devicetree/bindings/riscv/microchip.yaml | 20 +-
arch/riscv/boot/dts/microchip/Makefile | 2 +
.../dts/microchip/mpfs-icicle-kit-fabric.dtsi | 44 ++++-
.../boot/dts/microchip/mpfs-icicle-kit.dts | 3 +-
.../dts/microchip/mpfs-m100pfs-fabric.dtsi | 45 +++++
.../boot/dts/microchip/mpfs-m100pfsevp.dts | 179 ++++++++++++++++++
.../dts/microchip/mpfs-polarberry-fabric.dtsi | 29 +++
.../dts/microchip/mpfs-sev-kit-fabric.dtsi | 45 +++++
.../riscv/boot/dts/microchip/mpfs-sev-kit.dts | 145 ++++++++++++++
arch/riscv/boot/dts/microchip/mpfs.dtsi | 29 ---
10 files changed, 499 insertions(+), 42 deletions(-)
create mode 100644 arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi
create mode 100644 arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts
create mode 100644 arch/riscv/boot/dts/microchip/mpfs-sev-kit-fabric.dtsi
create mode 100644 arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts
--
2.36.1
Add a compatible for the Aries Embedded M100PFSEVP SOM + EVK platform.
Link: https://www.aries-embedded.com/polarfire-soc-fpga-microsemi-m100pfs-som-mpfs025t-pcie-serdes
Signed-off-by: Conor Dooley <[email protected]>
Acked-by: Rob Herring <[email protected]>
---
Documentation/devicetree/bindings/riscv/microchip.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Documentation/devicetree/bindings/riscv/microchip.yaml
index 485981fbfb4b..630f82c85a0c 100644
--- a/Documentation/devicetree/bindings/riscv/microchip.yaml
+++ b/Documentation/devicetree/bindings/riscv/microchip.yaml
@@ -27,6 +27,7 @@ properties:
- items:
- enum:
+ - aries,m100pfsevp
- sundance,polarberry
- const: microchip,mpfs
--
2.36.1
From: Shravan Chippa <[email protected]>
Update devicetree bindings document with PolarFire SoC Video Kit, known
by its "sev-kit" product code.
Link: https://onlinedocs.microchip.com/pr/GUID-404D3738-DC76-46BA-8683-6A77E837C2DD-en-US-1/index.html?GUID-065AEBEE-7B2C-4895-8579-B1D73D797F06
Signed-off-by: Shravan Chippa <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Conor Dooley <[email protected]>
---
Documentation/devicetree/bindings/riscv/microchip.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Documentation/devicetree/bindings/riscv/microchip.yaml
index 630f82c85a0c..ab0a64cd5386 100644
--- a/Documentation/devicetree/bindings/riscv/microchip.yaml
+++ b/Documentation/devicetree/bindings/riscv/microchip.yaml
@@ -28,6 +28,7 @@ properties:
- items:
- enum:
- aries,m100pfsevp
+ - microchip,mpfs-sev-kit
- sundance,polarberry
- const: microchip,mpfs
--
2.36.1
From: Vattipalli Praveen <[email protected]>
Add a basic dts for the Microchip Smart Embedded Vision dev kit.
The SEV kit is an upcoming first party board, featuring an MPFS250T and:
- Dual Sony Camera Sensors (IMX334)
- IEEE 802.11 b/g/n 20MHz (1x1) Wi-Fi
- Bluetooth 5 Low Energy
- 4 GB DDR4 x64
- 2 GB LPDDR4 x32
- 1 GB SPI Flash
- 8 GB eMMC flash & SD card slot (multiplexed)
- HDMI2.0 Video Input/Output
- MIPI DSI Output
- MIPI CSI-2 Input
Link: https://onlinedocs.microchip.com/pr/GUID-404D3738-DC76-46BA-8683-6A77E837C2DD-en-US-1/index.html?GUID-065AEBEE-7B2C-4895-8579-B1D73D797F06
Signed-off-by: Vattipalli Praveen <[email protected]>
Signed-off-by: Conor Dooley <[email protected]>
---
arch/riscv/boot/dts/microchip/Makefile | 1 +
.../dts/microchip/mpfs-sev-kit-fabric.dtsi | 45 ++++++
.../riscv/boot/dts/microchip/mpfs-sev-kit.dts | 145 ++++++++++++++++++
3 files changed, 191 insertions(+)
create mode 100644 arch/riscv/boot/dts/microchip/mpfs-sev-kit-fabric.dtsi
create mode 100644 arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts
diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile
index 39aae7b04f1c..f18477b2e86d 100644
--- a/arch/riscv/boot/dts/microchip/Makefile
+++ b/arch/riscv/boot/dts/microchip/Makefile
@@ -1,4 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb
dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-polarberry.dtb
+dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-sev-kit.dtb
obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
diff --git a/arch/riscv/boot/dts/microchip/mpfs-sev-kit-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-sev-kit-fabric.dtsi
new file mode 100644
index 000000000000..8545baf4d129
--- /dev/null
+++ b/arch/riscv/boot/dts/microchip/mpfs-sev-kit-fabric.dtsi
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2022 Microchip Technology Inc */
+
+/ {
+ fabric_clk3: fabric-clk3 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ fabric_clk1: fabric-clk1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+
+ pcie: pcie@2000000000 {
+ compatible = "microchip,pcie-host-1.0";
+ #address-cells = <0x3>;
+ #interrupt-cells = <0x1>;
+ #size-cells = <0x2>;
+ device_type = "pci";
+ reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
+ reg-names = "cfg", "apb";
+ bus-range = <0x0 0x7f>;
+ interrupt-parent = <&plic>;
+ interrupts = <119>;
+ interrupt-map = <0 0 0 1 &pcie_intc 0>,
+ <0 0 0 2 &pcie_intc 1>,
+ <0 0 0 3 &pcie_intc 2>,
+ <0 0 0 4 &pcie_intc 3>;
+ interrupt-map-mask = <0 0 0 7>;
+ clocks = <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>;
+ clock-names = "fic0", "fic1", "fic3";
+ ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>;
+ msi-parent = <&pcie>;
+ msi-controller;
+ status = "disabled";
+ pcie_intc: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+};
diff --git a/arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts
new file mode 100644
index 000000000000..013cb666c72d
--- /dev/null
+++ b/arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts
@@ -0,0 +1,145 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2022 Microchip Technology Inc */
+
+/dts-v1/;
+
+#include "mpfs.dtsi"
+#include "mpfs-sev-kit-fabric.dtsi"
+
+/* Clock frequency (in Hz) of the rtcclk */
+#define MTIMER_FREQ 1000000
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ model = "Microchip PolarFire-SoC SEV Kit";
+ compatible = "microchip,mpfs-sev-kit", "microchip,mpfs";
+
+ aliases {
+ ethernet0 = &mac1;
+ serial0 = &mmuart0;
+ serial1 = &mmuart1;
+ serial2 = &mmuart2;
+ serial3 = &mmuart3;
+ serial4 = &mmuart4;
+ };
+
+ chosen {
+ stdout-path = "serial1:115200n8";
+ };
+
+ cpus {
+ timebase-frequency = <MTIMER_FREQ>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ fabricbuf0ddrc: buffer@80000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x80000000 0x0 0x2000000>;
+ };
+
+ fabricbuf1ddrnc: buffer@c4000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0xc4000000 0x0 0x4000000>;
+ };
+
+ fabricbuf2ddrncwcb: buffer@d4000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0xd4000000 0x0 0x4000000>;
+ };
+ };
+
+ ddrc_cache: memory@1000000000 {
+ device_type = "memory";
+ reg = <0x10 0x0 0x0 0x76000000>;
+ };
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&gpio2 {
+ interrupts = <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>;
+ status = "okay";
+};
+
+&mac0 {
+ status = "okay";
+ phy-mode = "sgmii";
+ phy-handle = <&phy0>;
+ phy1: ethernet-phy@9 {
+ reg = <9>;
+ };
+ phy0: ethernet-phy@8 {
+ reg = <8>;
+ };
+};
+
+&mac1 {
+ status = "okay";
+ phy-mode = "sgmii";
+ phy-handle = <&phy1>;
+};
+
+&mbox {
+ status = "okay";
+};
+
+&mmc {
+ status = "okay";
+ bus-width = <4>;
+ disable-wp;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+};
+
+&mmuart1 {
+ status = "okay";
+};
+
+&mmuart2 {
+ status = "okay";
+};
+
+&mmuart3 {
+ status = "okay";
+};
+
+&mmuart4 {
+ status = "okay";
+};
+
+&refclk {
+ clock-frequency = <125000000>;
+};
+
+&rtc {
+ status = "okay";
+};
+
+&syscontroller {
+ status = "okay";
+};
+
+&usb {
+ status = "okay";
+ dr_mode = "otg";
+};
--
2.36.1
On Fri, Sep 16, 2022 at 12:26:36PM +0100, Conor Dooley wrote:
> Hey all,
>
> Some 6.1 targeted changes here.
> Firstly, two new dev kits (one first-party & one from Aries Embedded).
> They've been sitting in our vendor tree, so are being sent where they
> belong.
>
> Secondly, another release of our reference design for the Icicle kit
> is due in September. Usually these do not really change much for the
> devicetree, but this time around a pair of changes impact the memory
> map.
>
> The first of these is adding dma-ranges to the pcie controller. The
> controller had some issues to begin with & with the current reference
> design (v2022.05) would not work with mainline Linux nor has it since
> reference design v2021.08. A combination of the property, a change
> to the FPGA design & a small fix to the driver will get it working
> with mainline again. The other non-backwards compatible change to the
> reference design is moves of the peripherals instantiated in the
> fabric. Currently they are fairly spread out & a common complaint has
> been that this leaves little room in the fic3 section of the memory map
> for custom peripherals without removing the existing ones.
>
> This series depends on [0] so as not to add dtbs_check warnings. The
> fabric clock support is added by [1].
I've pushed this series to dt-for-next:
https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/log/?h=dt-for-next
There's a minor conflict with dt-fixes as that branch deletes a property
from the pcie dt node which is moved in this series. I deleted the
property as I moved it in this series so the fix will be to take the
version in dt-for-next instead.
>
> Thanks,
> Conor.
>
> Changes since v4:
> - fix the incompatible interrupts on m100pfsevp
>
> Changes since v3:
> - add an extra patch reducing the fic3 clock rate
>
> Changes since v2:
> - drop the sd & emmc versions of the aries devicetree
> - remove a extra newline
>
> Changes since v1:
> - made the polarberry part of an enum in patch 1
>
> 0 - https://lore.kernel.org/linux-gpio/[email protected]/
> 1 - https://lore.kernel.org/linux-clk/[email protected]/
>
> Conor Dooley (8):
> dt-bindings: riscv: microchip: document icicle reference design
> dt-bindings: riscv: microchip: document the aries m100pfsevp
> riscv: dts: microchip: add pci dma ranges for the icicle kit
> riscv: dts: microchip: move the mpfs' pci node to -fabric.dtsi
> riscv: dts: microchip: icicle: update pci address properties
> riscv: dts: microchip: icicle: re-jig fabric peripheral addresses
> riscv: dts: microchip: reduce the fic3 clock rate
> riscv: dts: microchip: add a devicetree for aries' m100pfsevp
>
> Shravan Chippa (1):
> dt-bindings: riscv: microchip: document the sev kit
>
> Vattipalli Praveen (1):
> riscv: dts: microchip: add sevkit device tree
>
> .../devicetree/bindings/riscv/microchip.yaml | 20 +-
> arch/riscv/boot/dts/microchip/Makefile | 2 +
> .../dts/microchip/mpfs-icicle-kit-fabric.dtsi | 44 ++++-
> .../boot/dts/microchip/mpfs-icicle-kit.dts | 3 +-
> .../dts/microchip/mpfs-m100pfs-fabric.dtsi | 45 +++++
> .../boot/dts/microchip/mpfs-m100pfsevp.dts | 179 ++++++++++++++++++
> .../dts/microchip/mpfs-polarberry-fabric.dtsi | 29 +++
> .../dts/microchip/mpfs-sev-kit-fabric.dtsi | 45 +++++
> .../riscv/boot/dts/microchip/mpfs-sev-kit.dts | 145 ++++++++++++++
> arch/riscv/boot/dts/microchip/mpfs.dtsi | 29 ---
> 10 files changed, 499 insertions(+), 42 deletions(-)
> create mode 100644 arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi
> create mode 100644 arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts
> create mode 100644 arch/riscv/boot/dts/microchip/mpfs-sev-kit-fabric.dtsi
> create mode 100644 arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts
>
> --
> 2.36.1
>