When adding a check for overlapping register regions to the QMP PHY
drivers I noticed that the USB4/USB3/DP PHY nodes are currently broken
in multiple ways.
This series fixes the SS PHY nodes and drops the DP PHY nodes which can
be added back after the binding and driver has been updated.
These should ideally go into 6.0.
Johan
Johan Hovold (4):
arm64: dts: qcom: sc8280xp: fix USB0 PHY PCS_MISC registers
arm64: dts: qcom: sc8280xp: fix USB1 PHY RX1 registers
arm64: dts: qcom: sc8280xp: fix USB PHY PCS registers
arm64: dts: qcom: sc8280xp: drop broken DP PHY nodes
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 28 ++++----------------------
1 file changed, 4 insertions(+), 24 deletions(-)
--
2.35.1
The DP PHY register layout of the current binding do not apply to the
newer USB4/USB3/DP PHY which uses a different register layout entirely.
Drop the DP PHY subnodes until the binding has been updated to prevent
the driver from corrupting unrelated registers.
Note that this is also needed in order to not break USB with an upcoming
PHY driver change that checks for overlapping register regions.
Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform")
Signed-off-by: Johan Hovold <[email protected]>
---
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 20 --------------------
1 file changed, 20 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index c734cac84719..014d72e49c74 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -1191,16 +1191,6 @@ usb_0_ssphy: usb3-phy@88eb400 {
clock-names = "pipe0";
clock-output-names = "usb0_phy_pipe_clk_src";
};
-
- usb_0_dpphy: dp-phy@88ed200 {
- reg = <0 0x088ed200 0 0x200>,
- <0 0x088ed400 0 0x200>,
- <0 0x088eda00 0 0x200>,
- <0 0x088ea600 0 0x200>,
- <0 0x088ea800 0 0x200>;
- #clock-cells = <1>;
- #phy-cells = <0>;
- };
};
usb_1_hsphy: phy@8902000 {
@@ -1253,16 +1243,6 @@ usb_1_ssphy: usb3-phy@8903400 {
clock-names = "pipe0";
clock-output-names = "usb1_phy_pipe_clk_src";
};
-
- usb_1_dpphy: dp-phy@8904200 {
- reg = <0 0x08904200 0 0x200>,
- <0 0x08904400 0 0x200>,
- <0 0x08904a00 0 0x200>,
- <0 0x08904600 0 0x200>,
- <0 0x08904800 0 0x200>;
- #clock-cells = <1>;
- #phy-cells = <0>;
- };
};
system-cache-controller@9200000 {
--
2.35.1
With the current binding, the PCS register block (0x1400) needs to
include the PCS_USB registers (0x1700).
Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform")
Signed-off-by: Johan Hovold <[email protected]>
---
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index 9667eb1b7c61..c734cac84719 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -1181,7 +1181,7 @@ usb_0_qmpphy: phy-wrapper@88ec000 {
usb_0_ssphy: usb3-phy@88eb400 {
reg = <0 0x088eb400 0 0x100>,
<0 0x088eb600 0 0x3ec>,
- <0 0x088ec400 0 0x1f0>,
+ <0 0x088ec400 0 0x364>,
<0 0x088eba00 0 0x100>,
<0 0x088ebc00 0 0x3ec>,
<0 0x088ec200 0 0x18>;
@@ -1243,7 +1243,7 @@ usb_1_qmpphy: phy-wrapper@8904000 {
usb_1_ssphy: usb3-phy@8903400 {
reg = <0 0x08903400 0 0x100>,
<0 0x08903600 0 0x3ec>,
- <0 0x08904400 0 0x1f0>,
+ <0 0x08904400 0 0x364>,
<0 0x08903a00 0 0x100>,
<0 0x08903c00 0 0x3ec>,
<0 0x08904200 0 0x18>;
--
2.35.1
The USB0 SS PHY node had the PCS_MISC register block (0x1200) replaced
with PCS_USB (0x1700).
Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform")
Signed-off-by: Johan Hovold <[email protected]>
---
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index 49ea8b5612fc..e8905445ca19 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -1184,7 +1184,7 @@ usb_0_ssphy: usb3-phy@88eb400 {
<0 0x088ec400 0 0x1f0>,
<0 0x088eba00 0 0x100>,
<0 0x088ebc00 0 0x3ec>,
- <0 0x088ec700 0 0x64>;
+ <0 0x088ec200 0 0x18>;
#phy-cells = <0>;
#clock-cells = <0>;
clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
--
2.35.1
The USB1 SS PHY node had the RX1 register block (0x600) replaced with
RX2 (0xc00).
Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform")
Signed-off-by: Johan Hovold <[email protected]>
---
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index e8905445ca19..9667eb1b7c61 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -1242,7 +1242,7 @@ usb_1_qmpphy: phy-wrapper@8904000 {
usb_1_ssphy: usb3-phy@8903400 {
reg = <0 0x08903400 0 0x100>,
- <0 0x08903c00 0 0x3ec>,
+ <0 0x08903600 0 0x3ec>,
<0 0x08904400 0 0x1f0>,
<0 0x08903a00 0 0x100>,
<0 0x08903c00 0 0x3ec>,
--
2.35.1
Hi,
On Mon, Sep 19, 2022 at 11:44:51AM +0200, Johan Hovold wrote:
> The USB0 SS PHY node had the PCS_MISC register block (0x1200) replaced
> with PCS_USB (0x1700).
>
> Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform")
> Signed-off-by: Johan Hovold <[email protected]>
Reviewed-by: Andrew Halaney <[email protected]>
Thanks for the patch, I think this patch makes sense from what I'm
seeing of upstream's expectations (that register space should be
PCS_MISC's) downstream, register names, and offsets.
Being verbose because it took me a little bit to figure out, but here's
the offset and registers I found downstream which correlate to
your change:
/* Module: USB3_PCS_MISC_USB3_PCS_MISC_USB3_PCS_MISC */
#define USB3_PCS_MISC_TYPEC_CTRL 0x1200
#define USB3_PCS_MISC_TYPEC_PWRDN_CTRL 0x1204
#define USB3_PCS_MISC_PCS_MISC_CONFIG1 0x1208
#define USB3_PCS_MISC_CLAMP_ENABLE 0x120C
#define USB3_PCS_MISC_TYPEC_STATUS 0x1210
#define USB3_PCS_MISC_PLACEHOLDER_STATUS 0x1214
Your description of the PCS_USB region accidentally being used in the
prior version also adds up with what I see.
Thanks,
Andrew
> ---
> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> index 49ea8b5612fc..e8905445ca19 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> @@ -1184,7 +1184,7 @@ usb_0_ssphy: usb3-phy@88eb400 {
> <0 0x088ec400 0 0x1f0>,
> <0 0x088eba00 0 0x100>,
> <0 0x088ebc00 0 0x3ec>,
> - <0 0x088ec700 0 0x64>;
> + <0 0x088ec200 0 0x18>;
> #phy-cells = <0>;
> #clock-cells = <0>;
> clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
> --
> 2.35.1
>
On Mon, Sep 19, 2022 at 11:44:52AM +0200, Johan Hovold wrote:
> The USB1 SS PHY node had the RX1 register block (0x600) replaced with
> RX2 (0xc00).
>
> Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform")
> Signed-off-by: Johan Hovold <[email protected]>
Reviewed-by: Andrew Halaney <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> index e8905445ca19..9667eb1b7c61 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> @@ -1242,7 +1242,7 @@ usb_1_qmpphy: phy-wrapper@8904000 {
>
> usb_1_ssphy: usb3-phy@8903400 {
> reg = <0 0x08903400 0 0x100>,
> - <0 0x08903c00 0 0x3ec>,
> + <0 0x08903600 0 0x3ec>,
> <0 0x08904400 0 0x1f0>,
> <0 0x08903a00 0 0x100>,
> <0 0x08903c00 0 0x3ec>,
> --
> 2.35.1
>
On Mon, Sep 19, 2022 at 11:44:53AM +0200, Johan Hovold wrote:
> With the current binding, the PCS register block (0x1400) needs to
> include the PCS_USB registers (0x1700).
>
> Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform")
> Signed-off-by: Johan Hovold <[email protected]>
Reviewed-by: Andrew Halaney <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> index 9667eb1b7c61..c734cac84719 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> @@ -1181,7 +1181,7 @@ usb_0_qmpphy: phy-wrapper@88ec000 {
> usb_0_ssphy: usb3-phy@88eb400 {
> reg = <0 0x088eb400 0 0x100>,
> <0 0x088eb600 0 0x3ec>,
> - <0 0x088ec400 0 0x1f0>,
> + <0 0x088ec400 0 0x364>,
> <0 0x088eba00 0 0x100>,
> <0 0x088ebc00 0 0x3ec>,
> <0 0x088ec200 0 0x18>;
> @@ -1243,7 +1243,7 @@ usb_1_qmpphy: phy-wrapper@8904000 {
> usb_1_ssphy: usb3-phy@8903400 {
> reg = <0 0x08903400 0 0x100>,
> <0 0x08903600 0 0x3ec>,
> - <0 0x08904400 0 0x1f0>,
> + <0 0x08904400 0 0x364>,
> <0 0x08903a00 0 0x100>,
> <0 0x08903c00 0 0x3ec>,
> <0 0x08904200 0 0x18>;
> --
> 2.35.1
>
On Mon, 19 Sep 2022 11:44:50 +0200, Johan Hovold wrote:
> When adding a check for overlapping register regions to the QMP PHY
> drivers I noticed that the USB4/USB3/DP PHY nodes are currently broken
> in multiple ways.
>
> This series fixes the SS PHY nodes and drops the DP PHY nodes which can
> be added back after the binding and driver has been updated.
>
> [...]
Applied, thanks!
[1/4] arm64: dts: qcom: sc8280xp: fix USB0 PHY PCS_MISC registers
commit: 31b3b3059791be536e2ec0c6830767b596af340f
[2/4] arm64: dts: qcom: sc8280xp: fix USB1 PHY RX1 registers
commit: 81cad26c6c3984d01b0612069c70ffd820f62dfa
[3/4] arm64: dts: qcom: sc8280xp: fix USB PHY PCS registers
commit: 8723c3f290c7b798c0cbd89998576e6b365bda3a
[4/4] arm64: dts: qcom: sc8280xp: drop broken DP PHY nodes
commit: 7cdfb7a54ac88f7cb6d830ebb78bdbcbcb44bb4c
Best regards,
--
Bjorn Andersson <[email protected]>