From: Lad Prabhakar <[email protected]>
Move the WDT2 clock and reset entries under CONFIG_ARM64 so that its only
visible for RZ/G2UL (ARM64) SoC as the RZ/Five (RISC-V) SoC doesn't have
the WDT2 channel.
While at it, add the WDT2 clocks to r9a07g043_crit_mod_clks[] list as WDT
CH2 is specifically to check the operation of Cortex-M33 CPU on the RZ/G2UL
SoC and we dont want to turn off the clocks of WDT2 if it isn't enabled by
Cortex-A55.
Fixes: 95d48d270305 ("clk: renesas: r9a07g043: Add support for RZ/Five SoC")
Reported-by: Biju Das <[email protected]>
Signed-off-by: Lad Prabhakar <[email protected]>
---
v1 -> v2
* Moved the entries in existing section of ARM64
* Updated the commit message
---
drivers/clk/renesas/r9a07g043-cpg.c | 12 +++++++-----
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c
index 37475465100d..e4f7f6ade427 100644
--- a/drivers/clk/renesas/r9a07g043-cpg.c
+++ b/drivers/clk/renesas/r9a07g043-cpg.c
@@ -137,6 +137,10 @@ static struct rzg2l_mod_clk r9a07g043_mod_clks[] = {
0x518, 0),
DEF_MOD("ia55_clk", R9A07G043_IA55_CLK, R9A07G043_CLK_P1,
0x518, 1),
+ DEF_MOD("wdt2_pclk", R9A07G043_WDT2_PCLK, R9A07G043_CLK_P0,
+ 0x548, 4),
+ DEF_MOD("wdt2_clk", R9A07G043_WDT2_CLK, R9A07G043_OSCCLK,
+ 0x548, 5),
#endif
#ifdef CONFIG_RISCV
DEF_MOD("iax45_pclk", R9A07G043_IAX45_PCLK, R9A07G043_CLK_P2,
@@ -158,10 +162,6 @@ static struct rzg2l_mod_clk r9a07g043_mod_clks[] = {
0x548, 0),
DEF_MOD("wdt0_clk", R9A07G043_WDT0_CLK, R9A07G043_OSCCLK,
0x548, 1),
- DEF_MOD("wdt2_pclk", R9A07G043_WDT2_PCLK, R9A07G043_CLK_P0,
- 0x548, 4),
- DEF_MOD("wdt2_clk", R9A07G043_WDT2_CLK, R9A07G043_OSCCLK,
- 0x548, 5),
DEF_MOD("spi_clk2", R9A07G043_SPI_CLK2, R9A07G043_CLK_SPI1,
0x550, 0),
DEF_MOD("spi_clk", R9A07G043_SPI_CLK, R9A07G043_CLK_SPI0,
@@ -259,6 +259,7 @@ static struct rzg2l_reset r9a07g043_resets[] = {
DEF_RST(R9A07G043_GIC600_GICRESET_N, 0x814, 0),
DEF_RST(R9A07G043_GIC600_DBG_GICRESET_N, 0x814, 1),
DEF_RST(R9A07G043_IA55_RESETN, 0x818, 0),
+ DEF_RST(R9A07G043_WDT2_PRESETN, 0x848, 2),
#endif
#ifdef CONFIG_RISCV
DEF_RST(R9A07G043_IAX45_RESETN, 0x818, 0),
@@ -269,7 +270,6 @@ static struct rzg2l_reset r9a07g043_resets[] = {
DEF_RST(R9A07G043_OSTM1_PRESETZ, 0x834, 1),
DEF_RST(R9A07G043_OSTM2_PRESETZ, 0x834, 2),
DEF_RST(R9A07G043_WDT0_PRESETN, 0x848, 0),
- DEF_RST(R9A07G043_WDT2_PRESETN, 0x848, 2),
DEF_RST(R9A07G043_SPI_RST, 0x850, 0),
DEF_RST(R9A07G043_SDHI0_IXRST, 0x854, 0),
DEF_RST(R9A07G043_SDHI1_IXRST, 0x854, 1),
@@ -311,6 +311,8 @@ static const unsigned int r9a07g043_crit_mod_clks[] __initconst = {
#ifdef CONFIG_ARM64
MOD_CLK_BASE + R9A07G043_GIC600_GICCLK,
MOD_CLK_BASE + R9A07G043_IA55_CLK,
+ MOD_CLK_BASE + R9A07G043_WDT2_PCLK,
+ MOD_CLK_BASE + R9A07G043_WDT2_CLK,
#endif
#ifdef CONFIG_RISCV
MOD_CLK_BASE + R9A07G043_IAX45_CLK,
--
2.25.1