Create new SoC data structure for Tegra234 platforms.
Additional features, tap value configurations are added/
updated for Tegra234 platform hence separate Tegra194 and
Tegra234 SoC data.
Signed-off-by: Aniruddha Tvs Rao <[email protected]>
Signed-off-by: Prathamesh Shete <[email protected]>
---
drivers/mmc/host/sdhci-tegra.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
index 2d2d8260c681..a6c5bbae77b4 100644
--- a/drivers/mmc/host/sdhci-tegra.c
+++ b/drivers/mmc/host/sdhci-tegra.c
@@ -1556,7 +1556,21 @@ static const struct sdhci_tegra_soc_data soc_data_tegra194 = {
.max_tap_delay = 139,
};
+static const struct sdhci_tegra_soc_data soc_data_tegra234 = {
+ .pdata = &sdhci_tegra186_pdata,
+ .dma_mask = DMA_BIT_MASK(39),
+ .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL |
+ NVQUIRK_HAS_PADCALIB |
+ NVQUIRK_DIS_CARD_CLK_CONFIG_TAP |
+ NVQUIRK_ENABLE_SDR50 |
+ NVQUIRK_ENABLE_SDR104 |
+ NVQUIRK_HAS_TMCLK,
+ .min_tap_delay = 95,
+ .max_tap_delay = 111,
+};
+
static const struct of_device_id sdhci_tegra_dt_match[] = {
+ { .compatible = "nvidia,tegra234-sdhci", .data = &soc_data_tegra234 },
{ .compatible = "nvidia,tegra194-sdhci", .data = &soc_data_tegra194 },
{ .compatible = "nvidia,tegra186-sdhci", .data = &soc_data_tegra186 },
{ .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 },
--
2.17.1
Ensure tegra_host member "curr_clk_rate" holds the actual clock rate
instead of requested clock rate for proper use during tuning correction
algorithm. Actual clk rate may not be the same as the requested clk
frequency depending on the parent clock source set. Tuning correction
algorithm depends on certain parameters which are sensitive to current
clk rate. If the host clk is selected instead of the actual clock rate,
tuning correction algorithm may end up applying invalid correction,
which could result in errors
Fixes: ea8fc5953e8b ("mmc: tegra: update hw tuning process")
Signed-off-by: Aniruddha TVS Rao <[email protected]>
Signed-off-by: Prathamesh Shete <[email protected]>
---
drivers/mmc/host/sdhci-tegra.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
index 58449e010a9b..10f6df070456 100644
--- a/drivers/mmc/host/sdhci-tegra.c
+++ b/drivers/mmc/host/sdhci-tegra.c
@@ -780,7 +780,7 @@ static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
dev_err(dev, "failed to set clk rate to %luHz: %d\n",
host_clk, err);
- tegra_host->curr_clk_rate = host_clk;
+ tegra_host->curr_clk_rate = clk_get_rate(pltfm_host->clk);
if (tegra_host->ddr_signaling)
host->max_clk = host_clk;
else
--
2.17.1
SMMU clients are supposed to program stream ID from
their respective address spaces instead of MC override.
Define NVQUIRK_PROGRAM_STREAMID and use it to program
SMMU stream ID from the SDMMC client address space.
Signed-off-by: Aniruddha TVS Rao <[email protected]>
Signed-off-by: Prathamesh Shete <[email protected]>
---
drivers/mmc/host/sdhci-tegra.c | 35 ++++++++++++++++++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
index a6c5bbae77b4..4d32b5bfc424 100644
--- a/drivers/mmc/host/sdhci-tegra.c
+++ b/drivers/mmc/host/sdhci-tegra.c
@@ -25,6 +25,7 @@
#include <linux/mmc/slot-gpio.h>
#include <linux/gpio/consumer.h>
#include <linux/ktime.h>
+#include <linux/iommu.h>
#include <soc/tegra/common.h>
@@ -94,6 +95,8 @@
#define SDHCI_TEGRA_AUTO_CAL_STATUS 0x1ec
#define SDHCI_TEGRA_AUTO_CAL_ACTIVE BIT(31)
+#define SDHCI_TEGRA_CIF2AXI_CTRL_0 0x1fc
+
#define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0)
#define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1)
#define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2)
@@ -121,6 +124,7 @@
#define NVQUIRK_HAS_TMCLK BIT(10)
#define NVQUIRK_HAS_ANDROID_GPT_SECTOR BIT(11)
+#define NVQUIRK_PROGRAM_STREAMID BIT(12)
/* SDMMC CQE Base Address for Tegra Host Ver 4.1 and Higher */
#define SDHCI_TEGRA_CQE_BASE_ADDR 0xF000
@@ -128,6 +132,8 @@
#define SDHCI_TEGRA_CQE_TRNS_MODE (SDHCI_TRNS_MULTI | \
SDHCI_TRNS_BLK_CNT_EN | \
SDHCI_TRNS_DMA)
+#define SDHCI_TEGRA_STREAMID_MASK 0xff
+#define SDHCI_TEGRA_WRITE_STREAMID_SHIFT 0x8
struct sdhci_tegra_soc_data {
const struct sdhci_pltfm_data *pdata;
@@ -177,6 +183,7 @@ struct sdhci_tegra {
bool enable_hwcq;
unsigned long curr_clk_rate;
u8 tuned_tap_delay;
+ u32 streamid;
};
static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg)
@@ -1564,6 +1571,7 @@ static const struct sdhci_tegra_soc_data soc_data_tegra234 = {
NVQUIRK_DIS_CARD_CLK_CONFIG_TAP |
NVQUIRK_ENABLE_SDR50 |
NVQUIRK_ENABLE_SDR104 |
+ NVQUIRK_PROGRAM_STREAMID |
NVQUIRK_HAS_TMCLK,
.min_tap_delay = 95,
.max_tap_delay = 111,
@@ -1636,6 +1644,7 @@ static int sdhci_tegra_probe(struct platform_device *pdev)
struct sdhci_host *host;
struct sdhci_pltfm_host *pltfm_host;
struct sdhci_tegra *tegra_host;
+ struct iommu_fwspec *fwspec;
struct clk *clk;
int rc;
@@ -1775,6 +1784,23 @@ static int sdhci_tegra_probe(struct platform_device *pdev)
if (rc)
goto err_add_host;
+ /* Program MC streamID for DMA transfers */
+ if (soc_data->nvquirks & NVQUIRK_PROGRAM_STREAMID) {
+ fwspec = dev_iommu_fwspec_get(&pdev->dev);
+ if (fwspec == NULL) {
+ dev_warn(mmc_dev(host->mmc),
+ "iommu fwspec is NULL, continue without stream ID\n");
+ } else {
+ tegra_host->streamid = fwspec->ids[0] & 0xffff;
+ tegra_sdhci_writel(host, (tegra_host->streamid &
+ SDHCI_TEGRA_STREAMID_MASK) |
+ ((tegra_host->streamid <<
+ SDHCI_TEGRA_WRITE_STREAMID_SHIFT)
+ & SDHCI_TEGRA_STREAMID_MASK),
+ SDHCI_TEGRA_CIF2AXI_CTRL_0);
+ }
+ }
+
return 0;
err_add_host:
@@ -1861,6 +1887,8 @@ static int sdhci_tegra_suspend(struct device *dev)
static int sdhci_tegra_resume(struct device *dev)
{
struct sdhci_host *host = dev_get_drvdata(dev);
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
int ret;
ret = mmc_gpio_set_cd_wake(host->mmc, false);
@@ -1871,6 +1899,13 @@ static int sdhci_tegra_resume(struct device *dev)
if (ret)
return ret;
+ /* Re-program MC streamID for DMA transfers */
+ if (tegra_host->soc_data->nvquirks & NVQUIRK_PROGRAM_STREAMID) {
+ tegra_sdhci_writel(host, tegra_host->streamid |
+ (tegra_host->streamid << 8),
+ SDHCI_TEGRA_CIF2AXI_CTRL_0);
+ }
+
ret = sdhci_resume_host(host);
if (ret)
goto disable_clk;
--
2.17.1
In case of error condition to avoid system crash
Tegra SDMMC controller requires CMD and DAT resets
issued together. SDHCI controller FSM goes into
bad state due to rapid SD card hot-plug event.
Issuing reset on the CMD FSM before DATA FSM results
in kernel panic, hence add support to issue CMD and
DAT resets together.
This is applicable to Tegra186 and later chips.
Signed-off-by: Aniruddha TVS Rao <[email protected]>
Signed-off-by: Prathamesh Shete <[email protected]>
---
drivers/mmc/host/sdhci-tegra.c | 3 ++-
drivers/mmc/host/sdhci.c | 20 +++++++++++++++-----
drivers/mmc/host/sdhci.h | 2 ++
3 files changed, 19 insertions(+), 6 deletions(-)
diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
index 4d32b5bfc424..58449e010a9b 100644
--- a/drivers/mmc/host/sdhci-tegra.c
+++ b/drivers/mmc/host/sdhci-tegra.c
@@ -1532,7 +1532,8 @@ static const struct sdhci_pltfm_data sdhci_tegra186_pdata = {
SDHCI_QUIRK_NO_HISPD_BIT |
SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
- .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
+ .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
+ SDHCI_QUIRK2_ISSUE_CMD_DAT_RESET_TOGETHER,
.ops = &tegra186_sdhci_ops,
};
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 7689ffec5ad1..2f4a0e84fee8 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -3060,12 +3060,22 @@ static bool sdhci_request_done(struct sdhci_host *host)
host->ops->set_clock(host, host->clock);
/*
- * Spec says we should do both at the same time, but Ricoh
- * controllers do not like that.
+ * While the specification says we should do both at the
+ * same time, Ricoh controllers (and potentially others) do not
+ * like that. On the other hand, some controllers (such as those
+ * found on Tegra186 and later) rely on both being reset at the
+ * same time. Use a quirk for the latter category since most
+ * controllers seem to work fine with DAT and CMD getting reset
+ * at the same time.
*/
- sdhci_do_reset(host, SDHCI_RESET_CMD);
- sdhci_do_reset(host, SDHCI_RESET_DATA);
-
+ if (host->quirks2 &
+ SDHCI_QUIRK2_ISSUE_CMD_DAT_RESET_TOGETHER) {
+ sdhci_do_reset(host, SDHCI_RESET_CMD |
+ SDHCI_RESET_DATA);
+ } else {
+ sdhci_do_reset(host, SDHCI_RESET_CMD);
+ sdhci_do_reset(host, SDHCI_RESET_DATA);
+ }
host->pending_reset = false;
}
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index 95a08f09df30..8045308f7859 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -480,6 +480,8 @@ struct sdhci_host {
* block count.
*/
#define SDHCI_QUIRK2_USE_32BIT_BLK_CNT (1<<18)
+/* Issue CMD and DATA reset together */
+#define SDHCI_QUIRK2_ISSUE_CMD_DAT_RESET_TOGETHER (1<<19)
int irq; /* Device IRQ */
void __iomem *ioaddr; /* Mapped address */
--
2.17.1
Hi Prathamesh,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on tegra/for-next]
[also build test ERROR on linus/master v6.0-rc6 next-20220921]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Prathamesh-Shete/mmc-sdhci-tegra-Separate-Tegra194-and-Tegra234-SoC-data/20220920-203924
base: https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git for-next
config: arc-randconfig-r002-20220921 (https://download.01.org/0day-ci/archive/20220922/[email protected]/config)
compiler: arc-elf-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/intel-lab-lkp/linux/commit/8087ec8183ffb01cc85647de0977c2dd369b324d
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Prathamesh-Shete/mmc-sdhci-tegra-Separate-Tegra194-and-Tegra234-SoC-data/20220920-203924
git checkout 8087ec8183ffb01cc85647de0977c2dd369b324d
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=arc SHELL=/bin/bash drivers/mmc/host/
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <[email protected]>
All errors (new ones prefixed by >>):
drivers/mmc/host/sdhci-tegra.c: In function 'sdhci_tegra_probe':
>> drivers/mmc/host/sdhci-tegra.c:1794:54: error: 'struct iommu_fwspec' has no member named 'ids'
1794 | tegra_host->streamid = fwspec->ids[0] & 0xffff;
| ^~
vim +1794 drivers/mmc/host/sdhci-tegra.c
1640
1641 static int sdhci_tegra_probe(struct platform_device *pdev)
1642 {
1643 const struct sdhci_tegra_soc_data *soc_data;
1644 struct sdhci_host *host;
1645 struct sdhci_pltfm_host *pltfm_host;
1646 struct sdhci_tegra *tegra_host;
1647 struct iommu_fwspec *fwspec;
1648 struct clk *clk;
1649 int rc;
1650
1651 soc_data = of_device_get_match_data(&pdev->dev);
1652 if (!soc_data)
1653 return -EINVAL;
1654
1655 host = sdhci_pltfm_init(pdev, soc_data->pdata, sizeof(*tegra_host));
1656 if (IS_ERR(host))
1657 return PTR_ERR(host);
1658 pltfm_host = sdhci_priv(host);
1659
1660 tegra_host = sdhci_pltfm_priv(pltfm_host);
1661 tegra_host->ddr_signaling = false;
1662 tegra_host->pad_calib_required = false;
1663 tegra_host->pad_control_available = false;
1664 tegra_host->soc_data = soc_data;
1665
1666 if (soc_data->nvquirks & NVQUIRK_HAS_ANDROID_GPT_SECTOR)
1667 host->mmc->caps2 |= MMC_CAP2_ALT_GPT_TEGRA;
1668
1669 if (soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL) {
1670 rc = tegra_sdhci_init_pinctrl_info(&pdev->dev, tegra_host);
1671 if (rc == 0)
1672 host->mmc_host_ops.start_signal_voltage_switch =
1673 sdhci_tegra_start_signal_voltage_switch;
1674 }
1675
1676 /* Hook to periodically rerun pad calibration */
1677 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB)
1678 host->mmc_host_ops.request = tegra_sdhci_request;
1679
1680 host->mmc_host_ops.hs400_enhanced_strobe =
1681 tegra_sdhci_hs400_enhanced_strobe;
1682
1683 if (!host->ops->platform_execute_tuning)
1684 host->mmc_host_ops.execute_tuning =
1685 tegra_sdhci_execute_hw_tuning;
1686
1687 rc = mmc_of_parse(host->mmc);
1688 if (rc)
1689 goto err_parse_dt;
1690
1691 if (tegra_host->soc_data->nvquirks & NVQUIRK_ENABLE_DDR50)
1692 host->mmc->caps |= MMC_CAP_1_8V_DDR;
1693
1694 /* HW busy detection is supported, but R1B responses are required. */
1695 host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_NEED_RSP_BUSY;
1696
1697 /* GPIO CD can be set as a wakeup source */
1698 host->mmc->caps |= MMC_CAP_CD_WAKE;
1699
1700 tegra_sdhci_parse_dt(host);
1701
1702 tegra_host->power_gpio = devm_gpiod_get_optional(&pdev->dev, "power",
1703 GPIOD_OUT_HIGH);
1704 if (IS_ERR(tegra_host->power_gpio)) {
1705 rc = PTR_ERR(tegra_host->power_gpio);
1706 goto err_power_req;
1707 }
1708
1709 /*
1710 * Tegra210 has a separate SDMMC_LEGACY_TM clock used for host
1711 * timeout clock and SW can choose TMCLK or SDCLK for hardware
1712 * data timeout through the bit USE_TMCLK_FOR_DATA_TIMEOUT of
1713 * the register SDHCI_TEGRA_VENDOR_SYS_SW_CTRL.
1714 *
1715 * USE_TMCLK_FOR_DATA_TIMEOUT bit default is set to 1 and SDMMC uses
1716 * 12Mhz TMCLK which is advertised in host capability register.
1717 * With TMCLK of 12Mhz provides maximum data timeout period that can
1718 * be achieved is 11s better than using SDCLK for data timeout.
1719 *
1720 * So, TMCLK is set to 12Mhz and kept enabled all the time on SoC's
1721 * supporting separate TMCLK.
1722 */
1723
1724 if (soc_data->nvquirks & NVQUIRK_HAS_TMCLK) {
1725 clk = devm_clk_get(&pdev->dev, "tmclk");
1726 if (IS_ERR(clk)) {
1727 rc = PTR_ERR(clk);
1728 if (rc == -EPROBE_DEFER)
1729 goto err_power_req;
1730
1731 dev_warn(&pdev->dev, "failed to get tmclk: %d\n", rc);
1732 clk = NULL;
1733 }
1734
1735 clk_set_rate(clk, 12000000);
1736 rc = clk_prepare_enable(clk);
1737 if (rc) {
1738 dev_err(&pdev->dev,
1739 "failed to enable tmclk: %d\n", rc);
1740 goto err_power_req;
1741 }
1742
1743 tegra_host->tmclk = clk;
1744 }
1745
1746 clk = devm_clk_get(mmc_dev(host->mmc), NULL);
1747 if (IS_ERR(clk)) {
1748 rc = dev_err_probe(&pdev->dev, PTR_ERR(clk),
1749 "failed to get clock\n");
1750 goto err_clk_get;
1751 }
1752 pltfm_host->clk = clk;
1753
1754 tegra_host->rst = devm_reset_control_get_exclusive(&pdev->dev,
1755 "sdhci");
1756 if (IS_ERR(tegra_host->rst)) {
1757 rc = PTR_ERR(tegra_host->rst);
1758 dev_err(&pdev->dev, "failed to get reset control: %d\n", rc);
1759 goto err_rst_get;
1760 }
1761
1762 rc = devm_tegra_core_dev_init_opp_table_common(&pdev->dev);
1763 if (rc)
1764 goto err_rst_get;
1765
1766 pm_runtime_enable(&pdev->dev);
1767 rc = pm_runtime_resume_and_get(&pdev->dev);
1768 if (rc)
1769 goto err_pm_get;
1770
1771 rc = reset_control_assert(tegra_host->rst);
1772 if (rc)
1773 goto err_rst_assert;
1774
1775 usleep_range(2000, 4000);
1776
1777 rc = reset_control_deassert(tegra_host->rst);
1778 if (rc)
1779 goto err_rst_assert;
1780
1781 usleep_range(2000, 4000);
1782
1783 rc = sdhci_tegra_add_host(host);
1784 if (rc)
1785 goto err_add_host;
1786
1787 /* Program MC streamID for DMA transfers */
1788 if (soc_data->nvquirks & NVQUIRK_PROGRAM_STREAMID) {
1789 fwspec = dev_iommu_fwspec_get(&pdev->dev);
1790 if (fwspec == NULL) {
1791 dev_warn(mmc_dev(host->mmc),
1792 "iommu fwspec is NULL, continue without stream ID\n");
1793 } else {
> 1794 tegra_host->streamid = fwspec->ids[0] & 0xffff;
1795 tegra_sdhci_writel(host, (tegra_host->streamid &
1796 SDHCI_TEGRA_STREAMID_MASK) |
1797 ((tegra_host->streamid <<
1798 SDHCI_TEGRA_WRITE_STREAMID_SHIFT)
1799 & SDHCI_TEGRA_STREAMID_MASK),
1800 SDHCI_TEGRA_CIF2AXI_CTRL_0);
1801 }
1802 }
1803
1804 return 0;
1805
1806 err_add_host:
1807 reset_control_assert(tegra_host->rst);
1808 err_rst_assert:
1809 pm_runtime_put_sync_suspend(&pdev->dev);
1810 err_pm_get:
1811 pm_runtime_disable(&pdev->dev);
1812 err_rst_get:
1813 err_clk_get:
1814 clk_disable_unprepare(tegra_host->tmclk);
1815 err_power_req:
1816 err_parse_dt:
1817 sdhci_pltfm_free(pdev);
1818 return rc;
1819 }
1820
--
0-DAY CI Kernel Test Service
https://01.org/lkp
On 20/09/22 15:37, Prathamesh Shete wrote:
> Ensure tegra_host member "curr_clk_rate" holds the actual clock rate
> instead of requested clock rate for proper use during tuning correction
> algorithm. Actual clk rate may not be the same as the requested clk
> frequency depending on the parent clock source set. Tuning correction
> algorithm depends on certain parameters which are sensitive to current
> clk rate. If the host clk is selected instead of the actual clock rate,
> tuning correction algorithm may end up applying invalid correction,
> which could result in errors
>
> Fixes: ea8fc5953e8b ("mmc: tegra: update hw tuning process")
>
> Signed-off-by: Aniruddha TVS Rao <[email protected]>
> Signed-off-by: Prathamesh Shete <[email protected]>
Acked-by: Adrian Hunter <[email protected]>
> ---
> drivers/mmc/host/sdhci-tegra.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
> index 58449e010a9b..10f6df070456 100644
> --- a/drivers/mmc/host/sdhci-tegra.c
> +++ b/drivers/mmc/host/sdhci-tegra.c
> @@ -780,7 +780,7 @@ static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
> dev_err(dev, "failed to set clk rate to %luHz: %d\n",
> host_clk, err);
>
> - tegra_host->curr_clk_rate = host_clk;
> + tegra_host->curr_clk_rate = clk_get_rate(pltfm_host->clk);
> if (tegra_host->ddr_signaling)
> host->max_clk = host_clk;
> else
On 20/09/22 15:37, Prathamesh Shete wrote:
> SMMU clients are supposed to program stream ID from
> their respective address spaces instead of MC override.
> Define NVQUIRK_PROGRAM_STREAMID and use it to program
> SMMU stream ID from the SDMMC client address space.
>
> Signed-off-by: Aniruddha TVS Rao <[email protected]>
> Signed-off-by: Prathamesh Shete <[email protected]>
> ---
> drivers/mmc/host/sdhci-tegra.c | 35 ++++++++++++++++++++++++++++++++++
> 1 file changed, 35 insertions(+)
>
> diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
> index a6c5bbae77b4..4d32b5bfc424 100644
> --- a/drivers/mmc/host/sdhci-tegra.c
> +++ b/drivers/mmc/host/sdhci-tegra.c
> @@ -25,6 +25,7 @@
> #include <linux/mmc/slot-gpio.h>
> #include <linux/gpio/consumer.h>
> #include <linux/ktime.h>
> +#include <linux/iommu.h>
>
> #include <soc/tegra/common.h>
>
> @@ -94,6 +95,8 @@
> #define SDHCI_TEGRA_AUTO_CAL_STATUS 0x1ec
> #define SDHCI_TEGRA_AUTO_CAL_ACTIVE BIT(31)
>
> +#define SDHCI_TEGRA_CIF2AXI_CTRL_0 0x1fc
> +
> #define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0)
> #define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1)
> #define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2)
> @@ -121,6 +124,7 @@
> #define NVQUIRK_HAS_TMCLK BIT(10)
>
> #define NVQUIRK_HAS_ANDROID_GPT_SECTOR BIT(11)
> +#define NVQUIRK_PROGRAM_STREAMID BIT(12)
>
> /* SDMMC CQE Base Address for Tegra Host Ver 4.1 and Higher */
> #define SDHCI_TEGRA_CQE_BASE_ADDR 0xF000
> @@ -128,6 +132,8 @@
> #define SDHCI_TEGRA_CQE_TRNS_MODE (SDHCI_TRNS_MULTI | \
> SDHCI_TRNS_BLK_CNT_EN | \
> SDHCI_TRNS_DMA)
> +#define SDHCI_TEGRA_STREAMID_MASK 0xff
> +#define SDHCI_TEGRA_WRITE_STREAMID_SHIFT 0x8
>
> struct sdhci_tegra_soc_data {
> const struct sdhci_pltfm_data *pdata;
> @@ -177,6 +183,7 @@ struct sdhci_tegra {
> bool enable_hwcq;
> unsigned long curr_clk_rate;
> u8 tuned_tap_delay;
> + u32 streamid;
> };
>
> static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg)
> @@ -1564,6 +1571,7 @@ static const struct sdhci_tegra_soc_data soc_data_tegra234 = {
> NVQUIRK_DIS_CARD_CLK_CONFIG_TAP |
> NVQUIRK_ENABLE_SDR50 |
> NVQUIRK_ENABLE_SDR104 |
> + NVQUIRK_PROGRAM_STREAMID |
> NVQUIRK_HAS_TMCLK,
> .min_tap_delay = 95,
> .max_tap_delay = 111,
> @@ -1636,6 +1644,7 @@ static int sdhci_tegra_probe(struct platform_device *pdev)
> struct sdhci_host *host;
> struct sdhci_pltfm_host *pltfm_host;
> struct sdhci_tegra *tegra_host;
> + struct iommu_fwspec *fwspec;
> struct clk *clk;
> int rc;
>
> @@ -1775,6 +1784,23 @@ static int sdhci_tegra_probe(struct platform_device *pdev)
> if (rc)
> goto err_add_host;
>
> + /* Program MC streamID for DMA transfers */
> + if (soc_data->nvquirks & NVQUIRK_PROGRAM_STREAMID) {
> + fwspec = dev_iommu_fwspec_get(&pdev->dev);
> + if (fwspec == NULL) {
> + dev_warn(mmc_dev(host->mmc),
> + "iommu fwspec is NULL, continue without stream ID\n");
> + } else {
> + tegra_host->streamid = fwspec->ids[0] & 0xffff;
As the robot pointed out 'ids' does not necessarily exist. Looking at
include/linux/iommu.h, it seems to depend on CONFIG_IOMMU_API
> + tegra_sdhci_writel(host, (tegra_host->streamid &
> + SDHCI_TEGRA_STREAMID_MASK) |
> + ((tegra_host->streamid <<
> + SDHCI_TEGRA_WRITE_STREAMID_SHIFT)
> + & SDHCI_TEGRA_STREAMID_MASK),
> + SDHCI_TEGRA_CIF2AXI_CTRL_0);
> + }
> + }
> +
> return 0;
>
> err_add_host:
> @@ -1861,6 +1887,8 @@ static int sdhci_tegra_suspend(struct device *dev)
> static int sdhci_tegra_resume(struct device *dev)
> {
> struct sdhci_host *host = dev_get_drvdata(dev);
> + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> + struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
> int ret;
>
> ret = mmc_gpio_set_cd_wake(host->mmc, false);
> @@ -1871,6 +1899,13 @@ static int sdhci_tegra_resume(struct device *dev)
> if (ret)
> return ret;
>
> + /* Re-program MC streamID for DMA transfers */
> + if (tegra_host->soc_data->nvquirks & NVQUIRK_PROGRAM_STREAMID) {
> + tegra_sdhci_writel(host, tegra_host->streamid |
> + (tegra_host->streamid << 8),
> + SDHCI_TEGRA_CIF2AXI_CTRL_0);
> + }
> +
> ret = sdhci_resume_host(host);
> if (ret)
> goto disable_clk;
On 20/09/22 15:37, Prathamesh Shete wrote:
> Create new SoC data structure for Tegra234 platforms.
> Additional features, tap value configurations are added/
> updated for Tegra234 platform hence separate Tegra194 and
> Tegra234 SoC data.
>
> Signed-off-by: Aniruddha Tvs Rao <[email protected]>
> Signed-off-by: Prathamesh Shete <[email protected]>
Acked-by: Adrian Hunter <[email protected]>
> ---
> drivers/mmc/host/sdhci-tegra.c | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
> index 2d2d8260c681..a6c5bbae77b4 100644
> --- a/drivers/mmc/host/sdhci-tegra.c
> +++ b/drivers/mmc/host/sdhci-tegra.c
> @@ -1556,7 +1556,21 @@ static const struct sdhci_tegra_soc_data soc_data_tegra194 = {
> .max_tap_delay = 139,
> };
>
> +static const struct sdhci_tegra_soc_data soc_data_tegra234 = {
> + .pdata = &sdhci_tegra186_pdata,
> + .dma_mask = DMA_BIT_MASK(39),
> + .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL |
> + NVQUIRK_HAS_PADCALIB |
> + NVQUIRK_DIS_CARD_CLK_CONFIG_TAP |
> + NVQUIRK_ENABLE_SDR50 |
> + NVQUIRK_ENABLE_SDR104 |
> + NVQUIRK_HAS_TMCLK,
> + .min_tap_delay = 95,
> + .max_tap_delay = 111,
> +};
> +
> static const struct of_device_id sdhci_tegra_dt_match[] = {
> + { .compatible = "nvidia,tegra234-sdhci", .data = &soc_data_tegra234 },
> { .compatible = "nvidia,tegra194-sdhci", .data = &soc_data_tegra194 },
> { .compatible = "nvidia,tegra186-sdhci", .data = &soc_data_tegra186 },
> { .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 },