From: Sajid Dalvi <[email protected]>
The PCIe r6.0, sec 5.9 spec requires a 10ms D3hot delay (defined by
PCI_PM_D3HOT_WAIT) for transitions to or from D3hot. So let's switch to
usleep_range() for the delay time to improve the delay accuracy.
This patch is based off of a commit from Sajid Dalvi <[email protected]>
in the Pixel 6 kernel tree [1]. Testing on a Pixel 6, found that the
10ms delay for the Exynos PCIe device was on average delaying for 19ms
when the spec requires 10ms. Switching from msleep() to usleep_range()
therefore decreases the resume time on a Pixel 6 on average by 9ms.
Note: some ancient Intel chips do have a quirk that sets the delay to
120ms. Using usleep_delay() may add a few extra milliseconds for those
chips.
[1] https://android.googlesource.com/kernel/gs/+/18a8cad68d8e6d50f339a716a18295e6d987cee3
Signed-off-by: Sajid Dalvi <[email protected]>
Signed-off-by: Will McVicker <[email protected]>
Reviewed-by: Matthias Kaehlcke <[email protected]>
---
drivers/pci/pci.c | 16 +++++++++-------
1 file changed, 9 insertions(+), 7 deletions(-)
v4:
* Drop use of msleep() in favor of always using usleep_range().
* Update the commit message.
v3:
* Use DIV_ROUND_CLOSEST instead of bit manipulation.
* Minor refactor to use max() where relavant.
v2:
* Update to use 20-25% upper bound
* Update to use usleep_range() for <=20ms, else use msleep()
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 516bf0c2ca02..2127aba3550b 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -66,13 +66,15 @@ struct pci_pme_device {
static void pci_dev_d3_sleep(struct pci_dev *dev)
{
- unsigned int delay = dev->d3hot_delay;
-
- if (delay < pci_pm_d3hot_delay)
- delay = pci_pm_d3hot_delay;
-
- if (delay)
- msleep(delay);
+ unsigned int delay_ms = max(dev->d3hot_delay, pci_pm_d3hot_delay);
+ unsigned int upper;
+
+ if (delay_ms) {
+ /* Use a 20% upper bound, 1ms minimum */
+ upper = max(DIV_ROUND_CLOSEST(delay_ms, 5), 1U);
+ usleep_range(delay_ms * USEC_PER_MSEC,
+ (delay_ms + upper) * USEC_PER_MSEC);
+ }
}
bool pci_reset_supported(struct pci_dev *dev)
base-commit: fcf773ae8016c6bffe5d408d3eda50d981b946e6
--
2.37.3.968.ga6b4b080e4-goog
On Wed, Sep 21, 2022 at 09:27:35PM +0000, Will McVicker wrote:
> From: Sajid Dalvi <[email protected]>
>
> The PCIe r6.0, sec 5.9 spec requires a 10ms D3hot delay (defined by
> PCI_PM_D3HOT_WAIT) for transitions to or from D3hot. So let's switch to
> usleep_range() for the delay time to improve the delay accuracy.
>
> This patch is based off of a commit from Sajid Dalvi <[email protected]>
> in the Pixel 6 kernel tree [1]. Testing on a Pixel 6, found that the
> 10ms delay for the Exynos PCIe device was on average delaying for 19ms
> when the spec requires 10ms. Switching from msleep() to usleep_range()
> therefore decreases the resume time on a Pixel 6 on average by 9ms.
>
> Note: some ancient Intel chips do have a quirk that sets the delay to
> 120ms. Using usleep_delay() may add a few extra milliseconds for those
> chips.
>
> [1] https://android.googlesource.com/kernel/gs/+/18a8cad68d8e6d50f339a716a18295e6d987cee3
>
> Signed-off-by: Sajid Dalvi <[email protected]>
> Signed-off-by: Will McVicker <[email protected]>
> Reviewed-by: Matthias Kaehlcke <[email protected]>
Applied to pci/pm for v6.1, thanks, Will!
> ---
> drivers/pci/pci.c | 16 +++++++++-------
> 1 file changed, 9 insertions(+), 7 deletions(-)
>
> v4:
> * Drop use of msleep() in favor of always using usleep_range().
> * Update the commit message.
>
> v3:
> * Use DIV_ROUND_CLOSEST instead of bit manipulation.
> * Minor refactor to use max() where relavant.
>
> v2:
> * Update to use 20-25% upper bound
> * Update to use usleep_range() for <=20ms, else use msleep()
>
> diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
> index 516bf0c2ca02..2127aba3550b 100644
> --- a/drivers/pci/pci.c
> +++ b/drivers/pci/pci.c
> @@ -66,13 +66,15 @@ struct pci_pme_device {
>
> static void pci_dev_d3_sleep(struct pci_dev *dev)
> {
> - unsigned int delay = dev->d3hot_delay;
> -
> - if (delay < pci_pm_d3hot_delay)
> - delay = pci_pm_d3hot_delay;
> -
> - if (delay)
> - msleep(delay);
> + unsigned int delay_ms = max(dev->d3hot_delay, pci_pm_d3hot_delay);
> + unsigned int upper;
> +
> + if (delay_ms) {
> + /* Use a 20% upper bound, 1ms minimum */
> + upper = max(DIV_ROUND_CLOSEST(delay_ms, 5), 1U);
> + usleep_range(delay_ms * USEC_PER_MSEC,
> + (delay_ms + upper) * USEC_PER_MSEC);
> + }
> }
>
> bool pci_reset_supported(struct pci_dev *dev)
>
> base-commit: fcf773ae8016c6bffe5d408d3eda50d981b946e6
> --
> 2.37.3.968.ga6b4b080e4-goog
>