Calibrate P2U for endpoint to request UPHY PLL rate change to Gen1 during
initialization.
Signed-off-by: Vidya Sagar <[email protected]>
---
V2:
* None
drivers/pci/controller/dwc/pcie-tegra194.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index 3e4868ab8416..cfe32a98b2f3 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -1078,6 +1078,9 @@ static int tegra_pcie_enable_phy(struct tegra_pcie_dw *pcie)
ret = phy_power_on(pcie->phys[i]);
if (ret < 0)
goto phy_exit;
+
+ if (pcie->of_data->mode == DW_PCIE_EP_TYPE)
+ phy_calibrate(pcie->phys[i]);
}
return 0;
--
2.17.1