This series adds a clock notifier for MediaTek clock muxes, required
in order to achieve stability for GPU DVFS.
The GPU frequency scaling mechanism requires us to switch the GPU
mux clock to a safe parent which frequency is always less or equal
to the "current" GPU frequency before reprogramming its dedicated
"MFG" PLL.
This is needed because the PLL needs time to reconfigure for its
output to stabilize (so, for the PLL to lock again): failing to do
so will lead to instabilities such as glitches, GPU lockups and/or
full system lockups.
While at it, reparenting of some GPU clocks was also performed, as
the clock tree was slightly incorrect.
This series was tested, along with mtk-regulator-coupler [1], on
Chromebooks with different SoCs (MT8183, MT8192, MT8195*), resulting
in fully working GPU DVFS with the Panfrost driver.
[1]: https://patchwork.kernel.org/project/linux-mediatek/patch/[email protected]/
* MT8195 does not require mtk-regulator-coupler. This series, along
with [1], are required to perform GPU DVFS also on non-Chromebook SoCs.
Changes in v3:
- Clarified commit description in patch [05/10]
Changes in v2:
- Added comment in clk-mt8195-topckgen to keep the mfg parents
documented after removal, as suggested by Chen-Yu
AngeloGioacchino Del Regno (6):
clk: mediatek: clk-mt8195-mfg: Reparent mfg_bg3d and propagate rate
changes
clk: mediatek: clk-mt8195-topckgen: Register mfg_ck_fast_ref as
generic mux
clk: mediatek: clk-mt8195-topckgen: Add GPU clock mux notifier
clk: mediatek: clk-mt8195-topckgen: Drop univplls from mfg mux parents
clk: mediatek: clk-mt8192-mfg: Propagate rate changes to parent
clk: mediatek: clk-mt8192: Add clock mux notifier for mfg_pll_sel
Chen-Yu Tsai (4):
arm64: dts: mt8183: Fix Mali GPU clock
clk: mediatek: mt8183: mfgcfg: Propagate rate changes to parent
clk: mediatek: mux: add clk notifier functions
clk: mediatek: mt8183: Add clk mux notifier for MFG mux
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 2 +-
drivers/clk/mediatek/clk-mt8183-mfgcfg.c | 6 +--
drivers/clk/mediatek/clk-mt8183.c | 28 +++++++++++++
drivers/clk/mediatek/clk-mt8192-mfg.c | 6 ++-
drivers/clk/mediatek/clk-mt8192.c | 28 +++++++++++++
drivers/clk/mediatek/clk-mt8195-mfg.c | 6 ++-
drivers/clk/mediatek/clk-mt8195-topckgen.c | 46 +++++++++++++++-------
drivers/clk/mediatek/clk-mux.c | 38 ++++++++++++++++++
drivers/clk/mediatek/clk-mux.h | 15 +++++++
9 files changed, 153 insertions(+), 22 deletions(-)
--
2.37.2
The MFG_BG3D is a gate to enable/disable clock output to the GPU,
but the actual output is decided by multiple muxes; in particular:
mfg_ck_fast_ref muxes between "slow" (top_mfg_core_tmp) and
"fast" (MFGPLL) clock, while top_mfg_core_tmp muxes between the
26MHz clock and various system PLLs.
The clock gate comes after all the muxes, so its parent is
mfg_ck_fast_reg, not top_mfg_core_tmp.
Reparent MFG_BG3D to the latter to match the hardware and add the
CLK_SET_RATE_PARENT flag to it: this way we ensure propagating
rate changes that are requested on MFG_BG3D along its entire clock
tree.
Fixes: 35016f10c0e5 ("clk: mediatek: Add MT8195 mfgcfg clock support")
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
---
drivers/clk/mediatek/clk-mt8195-mfg.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt8195-mfg.c b/drivers/clk/mediatek/clk-mt8195-mfg.c
index 9411c556a5a9..c94cb71bd9b9 100644
--- a/drivers/clk/mediatek/clk-mt8195-mfg.c
+++ b/drivers/clk/mediatek/clk-mt8195-mfg.c
@@ -17,10 +17,12 @@ static const struct mtk_gate_regs mfg_cg_regs = {
};
#define GATE_MFG(_id, _name, _parent, _shift) \
- GATE_MTK(_id, _name, _parent, &mfg_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+ GATE_MTK_FLAGS(_id, _name, _parent, &mfg_cg_regs, \
+ _shift, &mtk_clk_gate_ops_setclr, \
+ CLK_SET_RATE_PARENT)
static const struct mtk_gate mfg_clks[] = {
- GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "top_mfg_core_tmp", 0),
+ GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "mfg_ck_fast_ref", 0),
};
static const struct mtk_clk_desc mfg_desc = {
--
2.37.2
Following what was done on MT8183 and MT8195, also propagate the rate
changes to MFG_BG3D's parent on MT8192 to allow for proper GPU DVFS.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
---
drivers/clk/mediatek/clk-mt8192-mfg.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt8192-mfg.c b/drivers/clk/mediatek/clk-mt8192-mfg.c
index 3bbc7469f0e4..8ea5acdf832c 100644
--- a/drivers/clk/mediatek/clk-mt8192-mfg.c
+++ b/drivers/clk/mediatek/clk-mt8192-mfg.c
@@ -18,8 +18,10 @@ static const struct mtk_gate_regs mfg_cg_regs = {
.sta_ofs = 0x0,
};
-#define GATE_MFG(_id, _name, _parent, _shift) \
- GATE_MTK(_id, _name, _parent, &mfg_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+#define GATE_MFG(_id, _name, _parent, _shift) \
+ GATE_MTK_FLAGS(_id, _name, _parent, &mfg_cg_regs, \
+ _shift, &mtk_clk_gate_ops_setclr, \
+ CLK_SET_RATE_PARENT)
static const struct mtk_gate mfg_clks[] = {
GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "mfg_pll_sel", 0),
--
2.37.2
From: Chen-Yu Tsai <[email protected]>
When the MFG PLL clock, which is upstream of the MFG clock, is changed,
the downstream clock and consumers need to be switched away from the PLL
over to a stable clock to avoid glitches.
This is done through the use of the newly added clk mux notifier. The
notifier is set on the mux itself instead of the upstream PLL, but in
practice this works, as the rate change notifitcations are propogated
throughout the sub-tree hanging off the PLL. Just before rate changes,
the MFG mux is temporarily and transparently switched to the 26 MHz
main crystal. After the rate change, the mux is switched back.
Signed-off-by: Chen-Yu Tsai <[email protected]>
[Angelo: Rebased to assign clk_ops in mtk_mux_nb]
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Reviewed-by: Miles Chen <[email protected]>
---
drivers/clk/mediatek/clk-mt8183.c | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c
index 8512101e1189..1860a35a723a 100644
--- a/drivers/clk/mediatek/clk-mt8183.c
+++ b/drivers/clk/mediatek/clk-mt8183.c
@@ -1198,10 +1198,33 @@ static void clk_mt8183_top_init_early(struct device_node *node)
CLK_OF_DECLARE_DRIVER(mt8183_topckgen, "mediatek,mt8183-topckgen",
clk_mt8183_top_init_early);
+/* Register mux notifier for MFG mux */
+static int clk_mt8183_reg_mfg_mux_notifier(struct device *dev, struct clk *clk)
+{
+ struct mtk_mux_nb *mfg_mux_nb;
+ int i;
+
+ mfg_mux_nb = devm_kzalloc(dev, sizeof(*mfg_mux_nb), GFP_KERNEL);
+ if (!mfg_mux_nb)
+ return -ENOMEM;
+
+ for (i = 0; i < ARRAY_SIZE(top_muxes); i++)
+ if (top_muxes[i].id == CLK_TOP_MUX_MFG)
+ break;
+ if (i == ARRAY_SIZE(top_muxes))
+ return -EINVAL;
+
+ mfg_mux_nb->ops = top_muxes[i].ops;
+ mfg_mux_nb->bypass_index = 0; /* Bypass to 26M crystal */
+
+ return devm_mtk_clk_mux_notifier_register(dev, clk, mfg_mux_nb);
+}
+
static int clk_mt8183_top_probe(struct platform_device *pdev)
{
void __iomem *base;
struct device_node *node = pdev->dev.of_node;
+ int ret;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
@@ -1227,6 +1250,11 @@ static int clk_mt8183_top_probe(struct platform_device *pdev)
mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
top_clk_data);
+ ret = clk_mt8183_reg_mfg_mux_notifier(&pdev->dev,
+ top_clk_data->hws[CLK_TOP_MUX_MFG]->clk);
+ if (ret)
+ return ret;
+
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
top_clk_data);
}
--
2.37.2
On Tue, Sep 27, 2022 at 6:11 PM AngeloGioacchino Del Regno
<[email protected]> wrote:
>
> This series adds a clock notifier for MediaTek clock muxes, required
> in order to achieve stability for GPU DVFS.
>
> The GPU frequency scaling mechanism requires us to switch the GPU
> mux clock to a safe parent which frequency is always less or equal
> to the "current" GPU frequency before reprogramming its dedicated
> "MFG" PLL.
> This is needed because the PLL needs time to reconfigure for its
> output to stabilize (so, for the PLL to lock again): failing to do
> so will lead to instabilities such as glitches, GPU lockups and/or
> full system lockups.
>
> While at it, reparenting of some GPU clocks was also performed, as
> the clock tree was slightly incorrect.
>
> This series was tested, along with mtk-regulator-coupler [1], on
> Chromebooks with different SoCs (MT8183, MT8192, MT8195*), resulting
> in fully working GPU DVFS with the Panfrost driver.
>
> [1]: https://patchwork.kernel.org/project/linux-mediatek/patch/[email protected]/
>
> * MT8195 does not require mtk-regulator-coupler. This series, along
> with [1], are required to perform GPU DVFS also on non-Chromebook SoCs.
>
> Changes in v3:
> - Clarified commit description in patch [05/10]
>
> Changes in v2:
> - Added comment in clk-mt8195-topckgen to keep the mfg parents
> documented after removal, as suggested by Chen-Yu
>
> AngeloGioacchino Del Regno (6):
> clk: mediatek: clk-mt8195-mfg: Reparent mfg_bg3d and propagate rate
> changes
> clk: mediatek: clk-mt8195-topckgen: Register mfg_ck_fast_ref as
> generic mux
> clk: mediatek: clk-mt8195-topckgen: Add GPU clock mux notifier
> clk: mediatek: clk-mt8195-topckgen: Drop univplls from mfg mux parents
> clk: mediatek: clk-mt8192-mfg: Propagate rate changes to parent
> clk: mediatek: clk-mt8192: Add clock mux notifier for mfg_pll_sel
>
> Chen-Yu Tsai (4):
> arm64: dts: mt8183: Fix Mali GPU clock
> clk: mediatek: mt8183: mfgcfg: Propagate rate changes to parent
> clk: mediatek: mux: add clk notifier functions
> clk: mediatek: mt8183: Add clk mux notifier for MFG mux
I've queued all the clk patches up here [1] and will send a pull request
to the clock maintainer later this week.
The dts patch needs to go through the soc tree.
ChenYu
[1] https://git.kernel.org/pub/scm/linux/kernel/git/wens/linux.git/log/?h=clk-mtk-for-6.1