Add the nodes to enable the NVM Express PCIe controller on the
Radxa ROCK3 Model A board.
Cc: Chukun Pan <[email protected]>
Cc: Michael Riesch <[email protected]>
Signed-off-by: Anand Moon <[email protected]>
---
alarm@rock-3a:~$ lspci
0000:00:00.0 PCI bridge: Rockchip Electronics Co., Ltd RK3568 Remote Signal Processor (rev 01)
0002:00:00.0 PCI bridge: Rockchip Electronics Co., Ltd RK3568 Remote Signal Processor (rev 01)
0002:01:00.0 Non-Volatile memory controller: Micron/Crucial Technology P2 NVMe PCIe SSD (rev 01)
---
.../boot/dts/rockchip/rk3568-rock-3a.dts | 36 +++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
index fb87a168fe96..44d85ee1631e 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
@@ -79,6 +79,26 @@ vcc3v3_pcie: vcc3v3-pcie-regulator {
vin-supply = <&vcc5v0_sys>;
};
+ /* pi6c pcie clock generator feeds both ports */
+ vcc3v3_pi6c_03: vcc3v3-pi6c-03-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_pi6c_03";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <200000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ pcie30_3v3: gpio-regulator {
+ compatible = "regulator-gpio";
+ regulator-name = "pcie30_3v3";
+ regulator-min-microvolt = <100000>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
+ gpios-states = <0x1>;
+ states = <100000 0x0>, <3300000 0x1>;
+ };
+
vcc3v3_sys: vcc3v3-sys {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_sys";
@@ -546,6 +566,22 @@ &pcie2x1 {
status = "okay";
};
+&pcie30phy {
+ data-lanes = <0 1 2 3>;
+ phy-supply = <&vcc3v3_pi6c_03>;
+ status = "okay";
+};
+
+&pcie3x2 {
+ /* mPCIe slot */
+ num-lanes = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie30x2m1_pins>;
+ reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&pcie30_3v3>;
+ status = "okay";
+};
+
&pinctrl {
cam {
vcc_cam_en: vcc_cam_en {
--
2.37.3
Hi,
On 26-09-22, 06:14, Anand Moon wrote:
> + pcie30_3v3: gpio-regulator {
> + compatible = "regulator-gpio";
> + regulator-name = "pcie30_3v3";
> + regulator-min-microvolt = <100000>;
> + regulator-max-microvolt = <3300000>;
> + gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
> + gpios-states = <0x1>;
> + states = <100000 0x0>, <3300000 0x1>;
> + };
This is actually no different from vcc3v3-pcie regulator?
> +&pcie30phy {
> + data-lanes = <0 1 2 3>;
> + phy-supply = <&vcc3v3_pi6c_03>;
> + status = "okay";
> +};
It seems that there is no need to define additional data-lanes when
the pcie3x1 node is not enabled, and phy-supply seems unnecessary on
this board.
Excuse me, can you try the patches I posted? Lspci can recognize
pcie3x2 normally, but I don't have a spare nvme hard drive right
now to test if it works.
Thanks, Chukun
---
Chukun Pan (3):
arm64: dts: rockchip: Add regulator suffix to ROCK3 Model A
arm64: dts: rockchip: Rename pinctrl label of pcie2x1 on rock-3a
arm64: dts: rockchip: Add PCIe v3 nodes to rock-3a
.../boot/dts/rockchip/rk3568-rock-3a.dts | 36 ++++++++++++++-----
1 file changed, 27 insertions(+), 9 deletions(-)
--
2.25.1
Hi Chukun,
On Mon, 26 Sept 2022 at 23:31, Chukun Pan <[email protected]> wrote:
>
> Hi,
>
> On 26-09-22, 06:14, Anand Moon wrote:
>
> > + pcie30_3v3: gpio-regulator {
> > + compatible = "regulator-gpio";
> > + regulator-name = "pcie30_3v3";
> > + regulator-min-microvolt = <100000>;
> > + regulator-max-microvolt = <3300000>;
> > + gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
> > + gpios-states = <0x1>;
> > + states = <100000 0x0>, <3300000 0x1>;
> > + };
>
> This is actually no different from vcc3v3-pcie regulator?
>
> > +&pcie30phy {
> > + data-lanes = <0 1 2 3>;
> > + phy-supply = <&vcc3v3_pi6c_03>;
> > + status = "okay";
> > +};
>
> It seems that there is no need to define additional data-lanes when
> the pcie3x1 node is not enabled, and phy-supply seems unnecessary on
> this board.
>
As per the schematic below pice support with 2 regulators
VCC3V3_PCIE (SCT2250FPA)
VCC3V3_PI6C_03 (PI6C557-03 is a spread spectrum clock generator
supporting PCI Express and Ethernet requirements)
[0] https://dl.radxa.com/rock3/docs/hw/3a/rock3a_v1.3_sch.pdf
> Excuse me, can you try the patches I posted? Lspci can recognize
> pcie3x2 normally, but I don't have a spare nvme hard drive right
> now to test if it works.
>
No, it did not work on my board, see bool logs.
[0] https://pastebin.com/Lk93VFxg
[ 0.725985] phy phy-fe8c0000.phy.4: lane number 0, val 1
[ 0.726975] phy phy-fe8c0000.phy.4: rockchip_p3phy_rk3568_init: lock
failed 0x6890000, check input refclk and power supply
[ 0.728172] phy phy-fe8c0000.phy.4: phy init failed --> -110
[ 0.728704] rockchip-dw-pcie: probe of 3c0800000.pcie failed with error -110
[ 0.745193] ALSA device list:
Thanks
-Anand
> Thanks, Chukun
>
> ---
> Chukun Pan (3):
> arm64: dts: rockchip: Add regulator suffix to ROCK3 Model A
> arm64: dts: rockchip: Rename pinctrl label of pcie2x1 on rock-3a
> arm64: dts: rockchip: Add PCIe v3 nodes to rock-3a
>
> .../boot/dts/rockchip/rk3568-rock-3a.dts | 36 ++++++++++++++-----
> 1 file changed, 27 insertions(+), 9 deletions(-)
>
> --
> 2.25.1
>
On 2022-09-27 14:46, Anand Moon wrote:
> Hi Chukun,
>
> On Mon, 26 Sept 2022 at 23:31, Chukun Pan <[email protected]> wrote:
>>
>> Hi,
>>
>> On 26-09-22, 06:14, Anand Moon wrote:
>>
>>> + pcie30_3v3: gpio-regulator {
>>> + compatible = "regulator-gpio";
>>> + regulator-name = "pcie30_3v3";
>>> + regulator-min-microvolt = <100000>;
>>> + regulator-max-microvolt = <3300000>;
>>> + gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
>>> + gpios-states = <0x1>;
>>> + states = <100000 0x0>, <3300000 0x1>;
>>> + };
>>
>> This is actually no different from vcc3v3-pcie regulator?
>>
>>> +&pcie30phy {
>>> + data-lanes = <0 1 2 3>;
>>> + phy-supply = <&vcc3v3_pi6c_03>;
>>> + status = "okay";
>>> +};
>>
>> It seems that there is no need to define additional data-lanes when
>> the pcie3x1 node is not enabled, and phy-supply seems unnecessary on
>> this board.
>>
> As per the schematic below pice support with 2 regulators
>
> VCC3V3_PCIE (SCT2250FPA)
> VCC3V3_PI6C_03 (PI6C557-03 is a spread spectrum clock generator
> supporting PCI Express and Ethernet requirements)
Neither of which have anything to do with the phy, which is in the SoC
and runs off VDDA_0V9 and VCCA_1V8, see page 12. VCC3V3_PCIE is the
general power supply for the M.2 socket, which I doubt is supposed to
deliver 100mV when disabled.
(as a side note, is pcie2x1's vpcie3v3-supply as queued in -next
actually correct? AFAICS the other socket is effectively powered
straight from VCC3V3_SYS so shouldn't have needed VCC3V3_PCIE, but at
least it's there now ready for this one)
Robin.
>
> [0] https://dl.radxa.com/rock3/docs/hw/3a/rock3a_v1.3_sch.pdf
>
>> Excuse me, can you try the patches I posted? Lspci can recognize
>> pcie3x2 normally, but I don't have a spare nvme hard drive right
>> now to test if it works.
>>
>
> No, it did not work on my board, see bool logs.
> [0] https://pastebin.com/Lk93VFxg
>
> [ 0.725985] phy phy-fe8c0000.phy.4: lane number 0, val 1
> [ 0.726975] phy phy-fe8c0000.phy.4: rockchip_p3phy_rk3568_init: lock
> failed 0x6890000, check input refclk and power supply
> [ 0.728172] phy phy-fe8c0000.phy.4: phy init failed --> -110
> [ 0.728704] rockchip-dw-pcie: probe of 3c0800000.pcie failed with error -110
> [ 0.745193] ALSA device list:
>
> Thanks
> -Anand
>
>> Thanks, Chukun
>>
>> ---
>> Chukun Pan (3):
>> arm64: dts: rockchip: Add regulator suffix to ROCK3 Model A
>> arm64: dts: rockchip: Rename pinctrl label of pcie2x1 on rock-3a
>> arm64: dts: rockchip: Add PCIe v3 nodes to rock-3a
>>
>> .../boot/dts/rockchip/rk3568-rock-3a.dts | 36 ++++++++++++++-----
>> 1 file changed, 27 insertions(+), 9 deletions(-)
>>
>> --
>> 2.25.1
>>
>
> _______________________________________________
> Linux-rockchip mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-rockchip
Hi Anand,
On 27-09-22, 19:16, Anand Moon wrote:
> As per the schematic below pice support with 2 regulators
>
> VCC3V3_PCIE (SCT2250FPA)
> VCC3V3_PI6C_03 (PI6C557-03 is a spread spectrum clock generator
> supporting PCI Express and Ethernet requirements)
> [0] https://dl.radxa.com/rock3/docs/hw/3a/rock3a_v1.3_sch.pdf
Thanks for sharing, I rewrote this patch, can you try again?
> No, it did not work on my board, see bool logs.
> [0] https://pastebin.com/Lk93VFxg
From the boot log, looks like ethernet is broken:
mdio_bus stmmac-0: MDIO device at address 0 is missing.
rk_gmac-dwmac fe010000.ethernet eth0: no phy at addr -1
Actually I had this problem too, and reusing the "snps, reset"
property solved it. What confuses me is am I doing something
wrong or there is something wrong with the device tree now?
Thanks,
Chukun
---
Chukun Pan (1):
arm64: dts: rockchip: Add PCIe v3 nodes to rock-3a
.../boot/dts/rockchip/rk3568-rock-3a.dts | 52 ++++++++++++++++++-
1 file changed, 51 insertions(+), 1 deletion(-)
--
2.25.1
Hi,
On 27-09-22, 18:47, Robin Murphy wrote:
> (as a side note, is pcie2x1's vpcie3v3-supply as queued in -next
> actually correct? AFAICS the other socket is effectively powered
> straight from VCC3V3_SYS so shouldn't have needed VCC3V3_PCIE,
> but at least it's there now ready for this one)
Thanks for the correction, I didn't notice this before. You are right,
the supply of pcie2x1 comes from VCC3V3_SYS. But if we change supply
of pcie2x1 to VCC3V3_SYS, it will cause pcie30phy to fail to initialize
normally. The error is the same as the following:
> phy phy-fe8c0000.phy.4: rockchip_p3phy_rk3568_init: lock
> failed 0x6890000, check input refclk and power supply
> phy phy-fe8c0000.phy.4: phy init failed --> -110
> rockchip-dw-pcie: probe of 3c0800000.pcie failed with error -110
If both vpcie3v3-supply of pcie2x1 and pcie3x2 use VCC3V3_PCIE like
the vendor kernel, they can initialized normally.
Thanks,
Chukun
--
2.25.1
On 2022-09-28 11:05, Chukun Pan wrote:
> Hi,
>
> On 27-09-22, 18:47, Robin Murphy wrote:
>
>> (as a side note, is pcie2x1's vpcie3v3-supply as queued in -next
>> actually correct? AFAICS the other socket is effectively powered
>> straight from VCC3V3_SYS so shouldn't have needed VCC3V3_PCIE,
>> but at least it's there now ready for this one)
>
> Thanks for the correction, I didn't notice this before. You are right,
> the supply of pcie2x1 comes from VCC3V3_SYS. But if we change supply
> of pcie2x1 to VCC3V3_SYS, it will cause pcie30phy to fail to initialize
> normally. The error is the same as the following:
>
>> phy phy-fe8c0000.phy.4: rockchip_p3phy_rk3568_init: lock
>> failed 0x6890000, check input refclk and power supply
>> phy phy-fe8c0000.phy.4: phy init failed --> -110
>> rockchip-dw-pcie: probe of 3c0800000.pcie failed with error -110
>
> If both vpcie3v3-supply of pcie2x1 and pcie3x2 use VCC3V3_PCIE like
> the vendor kernel, they can initialized normally.
Presumably that only works because you happen to be probing pcie2x1
first, so it's not robust if that is disabled or probes later.
Looking again, it seems the answer was right there in the error message
all along - the PCIe 3.0 phy wants its external reference clock
describing correctly, and it's *that* clock which depends on
VCC3V3_PI6C_03, which happens to be turned on in parallel with VCC3V3_PCIE.
Cheers,
Robin.
Hi Chukun,
On Tue, 27 Sept 2022 at 23:45, Chukun Pan <[email protected]> wrote:
>
> Hi Anand,
>
> On 27-09-22, 19:16, Anand Moon wrote:
>
> > As per the schematic below pice support with 2 regulators
> >
> > VCC3V3_PCIE (SCT2250FPA)
> > VCC3V3_PI6C_03 (PI6C557-03 is a spread spectrum clock generator
> > supporting PCI Express and Ethernet requirements)
>
> > [0] https://dl.radxa.com/rock3/docs/hw/3a/rock3a_v1.3_sch.pdf
>
> Thanks for sharing, I rewrote this patch, can you try again?
>
No, It's not working on my board.
I have to enable CONFIG_REGULATOR_DEBUG, See the logs below.
[ 0.784121] reg-fixed-voltage vcc3v3-pi6c-03-regulator: vcc3v3_pi6c03
supplying 3300000uV
[ 0.784430] vcc3v3_pcie: 3300 mV, disabled
[0] https://pastebin.com/aEKQx1YZ
> > No, it did not work on my board, see bool logs.
> > [0] https://pastebin.com/Lk93VFxg
>
If you check the driver code it requires *data-line* and *num-lanes
from the dts.
[ 0.725985] phy phy-fe8c0000.phy.4: lane number 0, val 1
[ 0.726975] phy phy-fe8c0000.phy.4: rockchip_p3phy_rk3568_init: lock
failed 0x6890000, check input refclk and power supply
[ 0.728172] phy phy-fe8c0000.phy.4: phy init failed --> -110
[ 0.728704] rockchip-dw-pcie: probe of 3c0800000.pcie failed with error -110
> From the boot log, looks like ethernet is broken:
> mdio_bus stmmac-0: MDIO device at address 0 is missing.
> rk_gmac-dwmac fe010000.ethernet eth0: no phy at addr -1
>
> Actually I had this problem too, and reusing the "snps, reset"
> property solved it. What confuses me is am I doing something
> wrong or there is something wrong with the device tree now?
>
Yep, I have the following changes that work to bring the Ethernet up.
alarm@rock-3a:~/linux-next-5.y-devel$ git diff
arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
index 097cee13885d..498b9b2af3ed 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
@@ -242,6 +242,11 @@ &gmac1 {
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
assigned-clock-rates = <0>, <125000000>;
clock_in_out = "output";
+
+ snps,reset-gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
+ snps,reset-delays-us = <0 20000 100000>;
+ snps,reset-active-low;
+
phy-handle = <&rgmii_phy1>;
phy-mode = "rgmii-id";
pinctrl-names = "default";
@@ -250,6 +255,8 @@ &gmac1m1_tx_bus2
&gmac1m1_rx_bus2
&gmac1m1_rgmii_clk
&gmac1m1_rgmii_bus>;
+ tx_delay = <0x30>;
+ rx_delay = <0x10>;
status = "okay";
};
@@ -559,14 +566,11 @@ &i2s1_8ch {
};
&mdio1 {
- rgmii_phy1: ethernet-phy@0 {
+ rgmii_phy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
- reg = <0x0>;
+ reg = <0x1>;
pinctrl-names = "default";
pinctrl-0 = <ð_phy_rst>;
- reset-assert-us = <20000>;
- reset-deassert-us = <100000>;
- reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
};
};
Thanks
-Anand
Hi Anand,
> No, It's not working on my board.
> If you check the driver code it requires *data-line* and *num-lanes
> from the dts.
I have successfully tested NVME hard drives on my board. See
below for the patch, looking forward to your testing.
root@rock3a:~# lspci
0000:00:00.0 PCI bridge: Rockchip Electronics Co., Ltd \
RK3568 Remote Signal Processor (rev 01)
0000:01:00.0 Network controller: MEDIATEK Corp. MT7921 \
802.11ax PCI Express Wireless Network Adapter
0002:00:00.0 PCI bridge: Rockchip Electronics Co., Ltd \
RK3568 Remote Signal Processor (rev 01)
0002:01:00.0 Non-Volatile memory controller: Sandisk Corp \
PC SN520 NVMe SSD (rev 01)
Patch:
--- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
@@ -67,6 +67,37 @@ vcc12v_dcin: vcc12v-dcin-regulator {
regulator-boot-on;
};
+ pcie30_avdd0v9: pcie30-avdd0v9-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "pcie30_avdd0v9";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ vin-supply = <&vcc3v3_sys>;
+ };
+
+ pcie30_avdd1v8: pcie30-avdd1v8-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "pcie30_avdd1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc3v3_sys>;
+ };
+
+ /* pi6c pcie clock generator */
+ vcc3v3_pi6c_03: vcc3v3-pi6c-03-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_pi6c_03";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
vcc3v3_pcie: vcc3v3-pcie-regulator {
compatible = "regulator-fixed";
enable-active-high;
@@ -546,6 +577,19 @@ &pcie2x1 {
status = "okay";
};
+&pcie30phy {
+ phy-supply = <&vcc3v3_pi6c_03>;
+ status = "okay";
+};
+
+&pcie3x2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie30x2m1_pins>;
+ reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_pcie>;
+ status = "okay";
+};
+
&pinctrl {
cam {
vcc_cam_en: vcc_cam_en {
--
2.25.1
Thanks,
Chukun
Hi Chukun,
On Fri, 30 Sept 2022 at 20:55, Chukun Pan <[email protected]> wrote:
>
> Hi Anand,
>
> > No, It's not working on my board.
> > If you check the driver code it requires *data-line* and *num-lanes
> > from the dts.
>
> I have successfully tested NVME hard drives on my board. See
> below for the patch, looking forward to your testing.
>
> root@rock3a:~# lspci
> 0000:00:00.0 PCI bridge: Rockchip Electronics Co., Ltd \
> RK3568 Remote Signal Processor (rev 01)
> 0000:01:00.0 Network controller: MEDIATEK Corp. MT7921 \
> 802.11ax PCI Express Wireless Network Adapter
> 0002:00:00.0 PCI bridge: Rockchip Electronics Co., Ltd \
> RK3568 Remote Signal Processor (rev 01)
> 0002:01:00.0 Non-Volatile memory controller: Sandisk Corp \
> PC SN520 NVMe SSD (rev 01)
>
> Patch:
>
Thanks this patch works for me.
I would prefer the regulators would get enabled/disabled by the core drivers
like it's done in rk3399 PCIe drivers.
$ lspci
0000:00:00.0 PCI bridge: Rockchip Electronics Co., Ltd RK3568 Remote
Signal Processor (rev 01)
0000:01:00.0 Network controller: Intel Corporation Wireless 8265 / 8275 (rev 78)
0002:00:00.0 PCI bridge: Rockchip Electronics Co., Ltd RK3568 Remote
Signal Processor (rev 01)
0002:01:00.0 Non-Volatile memory controller: Micron/Crucial Technology
P2 NVMe PCIe SSD (rev 01)
> --- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
> +++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
> @@ -67,6 +67,37 @@ vcc12v_dcin: vcc12v-dcin-regulator {
> regulator-boot-on;
> };
>
> + pcie30_avdd0v9: pcie30-avdd0v9-regulator {
> + compatible = "regulator-fixed";
> + regulator-name = "pcie30_avdd0v9";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <900000>;
> + vin-supply = <&vcc3v3_sys>;
> + };
> +
> + pcie30_avdd1v8: pcie30-avdd1v8-regulator {
> + compatible = "regulator-fixed";
> + regulator-name = "pcie30_avdd1v8";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + vin-supply = <&vcc3v3_sys>;
> + };
> +
> + /* pi6c pcie clock generator */
> + vcc3v3_pi6c_03: vcc3v3-pi6c-03-regulator {
> + compatible = "regulator-fixed";
> + regulator-name = "vcc3v3_pi6c_03";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + vin-supply = <&vcc5v0_sys>;
> + };
> +
> vcc3v3_pcie: vcc3v3-pcie-regulator {
> compatible = "regulator-fixed";
> enable-active-high;
> @@ -546,6 +577,19 @@ &pcie2x1 {
> status = "okay";
> };
>
> +&pcie30phy {
Please add the following field as per the device tree binding
# Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml
data-lanes = <0 1>;
> + phy-supply = <&vcc3v3_pi6c_03>;
> + status = "okay";
> +};
> +
> +&pcie3x2 {
Please add the following field as per the device tree binding
# Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
num-lanes = <2>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pcie30x2m1_pins>;
> + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
> + vpcie3v3-supply = <&vcc3v3_pcie>;
> + status = "okay";
> +};
> +
> &pinctrl {
> cam {
> vcc_cam_en: vcc_cam_en {
> --
> 2.25.1
>
> Thanks,
> Chukun
Thanks
-Anand