2022-09-27 20:24:47

by Robert Marko

Subject: [PATCH 1/2] arm64: dts: qcom: ipq6018: fix NAND node name

Per schema it should be nand-controller@79b0000 instead of nand@79b0000.
Fix it to match nand-controller.yaml requirements.

Signed-off-by: Robert Marko <[email protected]>
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
index a7c7ca980a71..57978a8ab498 100644
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -348,7 +348,7 @@ qpic_bam: dma-controller@7984000 {
status = "disabled";
};

- qpic_nand: nand@79b0000 {
+ qpic_nand: nand-controller@79b0000 {
compatible = "qcom,ipq6018-nand";
reg = <0x0 0x079b0000 0x0 0x10000>;
#address-cells = <1>;
--
2.37.3

2022-09-27 20:51:51

by Robert Marko

Subject: [PATCH 2/2] arm64: dts: qcom: ipq6018: move ARMv8 timer out of SoC node

The ARM timer is usually considered not part of SoC node, just like
other ARM designed blocks (PMU, PSCI). This fixes dtbs_check warning:

arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dtb: soc: timer: {'compatible': ['arm,armv8-timer'], 'interrupts': [[1, 2, 3848], [1, 3, 3848], [1, 4, 3848], [1, 1, 3848]]} should not be valid under {'type': 'object'}
From schema: dtschema/schemas/simple-bus.yaml

Signed-off-by: Robert Marko <[email protected]>
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
index 57978a8ab498..428e99e127c3 100644
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -511,14 +511,6 @@ a53pll: clock@b116000 {
clock-names = "xo";
};

- timer {
- compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
- };
-
timer@b120000 {
#address-cells = <1>;
#size-cells = <1>;
@@ -770,6 +762,14 @@ dwc_0: usb@8a00000 {
};
};

+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
wcss: wcss-smp2p {
compatible = "qcom,smp2p";
qcom,smem = <435>, <428>;
--
2.37.3

2022-09-28 08:15:04

by Krzysztof Kozlowski

Subject: Re: [PATCH 2/2] arm64: dts: qcom: ipq6018: move ARMv8 timer out of SoC node

On 27/09/2022 22:12, Robert Marko wrote:
> The ARM timer is usually considered not part of SoC node, just like
> other ARM designed blocks (PMU, PSCI). This fixes dtbs_check warning:
>
> arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dtb: soc: timer: {'compatible': ['arm,armv8-timer'], 'interrupts': [[1, 2, 3848], [1, 3, 3848], [1, 4, 3848], [1, 1, 3848]]} should not be valid under {'type': 'object'}
> From schema: dtschema/schemas/simple-bus.yaml
>
> Signed-off-by: Robert Marko <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/ipq6018.dtsi | 16 ++++++++--------


Reviewed-by: Krzysztof Kozlowski <[email protected]>

Best regards,
Krzysztof

2022-09-28 08:16:32

by Neil Armstrong

Subject: Re: [PATCH 1/2] arm64: dts: qcom: ipq6018: fix NAND node name

On 27/09/2022 22:12, Robert Marko wrote:
> Per schema it should be nand-controller@79b0000 instead of nand@79b0000.
> Fix it to match nand-controller.yaml requirements.
>
> Signed-off-by: Robert Marko <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> index a7c7ca980a71..57978a8ab498 100644
> --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> @@ -348,7 +348,7 @@ qpic_bam: dma-controller@7984000 {
> status = "disabled";
> };
>
> - qpic_nand: nand@79b0000 {
> + qpic_nand: nand-controller@79b0000 {
> compatible = "qcom,ipq6018-nand";
> reg = <0x0 0x079b0000 0x0 0x10000>;
> #address-cells = <1>;

Reviewed-by: Neil Armstrong <[email protected]>

2022-09-28 08:20:38

by Krzysztof Kozlowski

Subject: Re: [PATCH 1/2] arm64: dts: qcom: ipq6018: fix NAND node name

On 27/09/2022 22:12, Robert Marko wrote:
> Per schema it should be nand-controller@79b0000 instead of nand@79b0000.
> Fix it to match nand-controller.yaml requirements.
>
> Signed-off-by: Robert Marko <[email protected]>


Reviewed-by: Krzysztof Kozlowski <[email protected]>

Best regards,
Krzysztof

2022-09-28 08:38:15

by Neil Armstrong

Subject: Re: [PATCH 2/2] arm64: dts: qcom: ipq6018: move ARMv8 timer out of SoC node

On 27/09/2022 22:12, Robert Marko wrote:
> The ARM timer is usually considered not part of SoC node, just like
> other ARM designed blocks (PMU, PSCI). This fixes dtbs_check warning:
>
> arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dtb: soc: timer: {'compatible': ['arm,armv8-timer'], 'interrupts': [[1, 2, 3848], [1, 3, 3848], [1, 4, 3848], [1, 1, 3848]]} should not be valid under {'type': 'object'}
> From schema: dtschema/schemas/simple-bus.yaml
>
> Signed-off-by: Robert Marko <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/ipq6018.dtsi | 16 ++++++++--------
> 1 file changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> index 57978a8ab498..428e99e127c3 100644
> --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> @@ -511,14 +511,6 @@ a53pll: clock@b116000 {
> clock-names = "xo";
> };
>
> - timer {
> - compatible = "arm,armv8-timer";
> - interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> - <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> - <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> - <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
> - };
> -
> timer@b120000 {
> #address-cells = <1>;
> #size-cells = <1>;
> @@ -770,6 +762,14 @@ dwc_0: usb@8a00000 {
> };
> };
>
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
> + };
> +
> wcss: wcss-smp2p {
> compatible = "qcom,smp2p";
> qcom,smem = <435>, <428>;

Reviewed-by: Neil Armstrong <[email protected]>

2022-10-18 03:59:12

by Bjorn Andersson

Subject: Re: (subset) [PATCH 1/2] arm64: dts: qcom: ipq6018: fix NAND node name

On Tue, 27 Sep 2022 22:12:17 +0200, Robert Marko wrote:
> Per schema it should be nand-controller@79b0000 instead of nand@79b0000.
> Fix it to match nand-controller.yaml requirements.
>
>

Applied, thanks!

[1/2] arm64: dts: qcom: ipq6018: fix NAND node name
commit: 8857b0ab6a562c473c5bded0efda9390b82a84d4
[2/2] arm64: dts: qcom: ipq6018: move ARMv8 timer out of SoC node
commit: feeef118fda562cf9081edef8ad464d89db070f4

Best regards,
--
Bjorn Andersson <[email protected]>