LinuxLists.cc - [PATCH v2 4/4] riscv: entry: consolidate general regs saving into save

2022-09-28 16:41:08

Subject: [PATCH v2 4/4] riscv: entry: consolidate general regs saving into save_gp

Consolidate the saving/restoring GPs(except ra, sp and tp) into
save_gp/restore_gp macro.

No functional change intended.

Signed-off-by: Jisheng Zhang <[email protected]>
---
arch/riscv/include/asm/asm.h | 65 +++++++++++++++++++++++++
arch/riscv/kernel/entry.S | 87 ++--------------------------------
arch/riscv/kernel/mcount-dyn.S | 58 +----------------------
3 files changed, 70 insertions(+), 140 deletions(-)

diff --git a/arch/riscv/include/asm/asm.h b/arch/riscv/include/asm/asm.h
index 1b471ff73178..2f3b49536e9d 100644
--- a/arch/riscv/include/asm/asm.h
+++ b/arch/riscv/include/asm/asm.h
@@ -68,6 +68,7 @@
#endif

#ifdef __ASSEMBLY__
+#include <asm/asm-offsets.h>

/* Common assembly source macros */

@@ -80,6 +81,70 @@
.endr
.endm

+ /* save all GPs except ra, sp and tp */
+ .macro save_gp
+ REG_S x3, PT_GP(sp)
+ REG_S x5, PT_T0(sp)
+ REG_S x6, PT_T1(sp)
+ REG_S x7, PT_T2(sp)
+ REG_S x8, PT_S0(sp)
+ REG_S x9, PT_S1(sp)
+ REG_S x10, PT_A0(sp)
+ REG_S x11, PT_A1(sp)
+ REG_S x12, PT_A2(sp)
+ REG_S x13, PT_A3(sp)
+ REG_S x14, PT_A4(sp)
+ REG_S x15, PT_A5(sp)
+ REG_S x16, PT_A6(sp)
+ REG_S x17, PT_A7(sp)
+ REG_S x18, PT_S2(sp)
+ REG_S x19, PT_S3(sp)
+ REG_S x20, PT_S4(sp)
+ REG_S x21, PT_S5(sp)
+ REG_S x22, PT_S6(sp)
+ REG_S x23, PT_S7(sp)
+ REG_S x24, PT_S8(sp)
+ REG_S x25, PT_S9(sp)
+ REG_S x26, PT_S10(sp)
+ REG_S x27, PT_S11(sp)
+ REG_S x28, PT_T3(sp)
+ REG_S x29, PT_T4(sp)
+ REG_S x30, PT_T5(sp)
+ REG_S x31, PT_T6(sp)
+ .endm
+
+ /* restore all GPs except ra, sp and tp */
+ .macro restore_gp
+ REG_L x3, PT_GP(sp)
+ REG_L x5, PT_T0(sp)
+ REG_L x6, PT_T1(sp)
+ REG_L x7, PT_T2(sp)
+ REG_L x8, PT_S0(sp)
+ REG_L x9, PT_S1(sp)
+ REG_L x10, PT_A0(sp)
+ REG_L x11, PT_A1(sp)
+ REG_L x12, PT_A2(sp)
+ REG_L x13, PT_A3(sp)
+ REG_L x14, PT_A4(sp)
+ REG_L x15, PT_A5(sp)
+ REG_L x16, PT_A6(sp)
+ REG_L x17, PT_A7(sp)
+ REG_L x18, PT_S2(sp)
+ REG_L x19, PT_S3(sp)
+ REG_L x20, PT_S4(sp)
+ REG_L x21, PT_S5(sp)
+ REG_L x22, PT_S6(sp)
+ REG_L x23, PT_S7(sp)
+ REG_L x24, PT_S8(sp)
+ REG_L x25, PT_S9(sp)
+ REG_L x26, PT_S10(sp)
+ REG_L x27, PT_S11(sp)
+ REG_L x28, PT_T3(sp)
+ REG_L x29, PT_T4(sp)
+ REG_L x30, PT_T5(sp)
+ REG_L x31, PT_T6(sp)
+ .endm
+
#endif /* __ASSEMBLY__ */

#endif /* _ASM_RISCV_ASM_H */
diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
index 5a6171a90d81..a90f17ed2822 100644
--- a/arch/riscv/kernel/entry.S
+++ b/arch/riscv/kernel/entry.S
@@ -40,34 +40,7 @@ _save_context:
REG_L sp, TASK_TI_KERNEL_SP(tp)
addi sp, sp, -(PT_SIZE_ON_STACK)
REG_S x1, PT_RA(sp)
- REG_S x3, PT_GP(sp)
- REG_S x5, PT_T0(sp)
- REG_S x6, PT_T1(sp)
- REG_S x7, PT_T2(sp)
- REG_S x8, PT_S0(sp)
- REG_S x9, PT_S1(sp)
- REG_S x10, PT_A0(sp)
- REG_S x11, PT_A1(sp)
- REG_S x12, PT_A2(sp)
- REG_S x13, PT_A3(sp)
- REG_S x14, PT_A4(sp)
- REG_S x15, PT_A5(sp)
- REG_S x16, PT_A6(sp)
- REG_S x17, PT_A7(sp)
- REG_S x18, PT_S2(sp)
- REG_S x19, PT_S3(sp)
- REG_S x20, PT_S4(sp)
- REG_S x21, PT_S5(sp)
- REG_S x22, PT_S6(sp)
- REG_S x23, PT_S7(sp)
- REG_S x24, PT_S8(sp)
- REG_S x25, PT_S9(sp)
- REG_S x26, PT_S10(sp)
- REG_S x27, PT_S11(sp)
- REG_S x28, PT_T3(sp)
- REG_S x29, PT_T4(sp)
- REG_S x30, PT_T5(sp)
- REG_S x31, PT_T6(sp)
+ save_gp

/*
* Disable user-mode memory access as it should only be set in the
@@ -182,35 +155,8 @@ ENTRY(ret_from_exception)
csrw CSR_STATUS, a0

REG_L x1, PT_RA(sp)
- REG_L x3, PT_GP(sp)
REG_L x4, PT_TP(sp)
- REG_L x5, PT_T0(sp)
- REG_L x6, PT_T1(sp)
- REG_L x7, PT_T2(sp)
- REG_L x8, PT_S0(sp)
- REG_L x9, PT_S1(sp)
- REG_L x10, PT_A0(sp)
- REG_L x11, PT_A1(sp)
- REG_L x12, PT_A2(sp)
- REG_L x13, PT_A3(sp)
- REG_L x14, PT_A4(sp)
- REG_L x15, PT_A5(sp)
- REG_L x16, PT_A6(sp)
- REG_L x17, PT_A7(sp)
- REG_L x18, PT_S2(sp)
- REG_L x19, PT_S3(sp)
- REG_L x20, PT_S4(sp)
- REG_L x21, PT_S5(sp)
- REG_L x22, PT_S6(sp)
- REG_L x23, PT_S7(sp)
- REG_L x24, PT_S8(sp)
- REG_L x25, PT_S9(sp)
- REG_L x26, PT_S10(sp)
- REG_L x27, PT_S11(sp)
- REG_L x28, PT_T3(sp)
- REG_L x29, PT_T4(sp)
- REG_L x30, PT_T5(sp)
- REG_L x31, PT_T6(sp)
+ restore_gp

REG_L x2, PT_SP(sp)

@@ -237,34 +183,7 @@ ENTRY(handle_kernel_stack_overflow)

//save context to overflow stack
REG_S x1, PT_RA(sp)
- REG_S x3, PT_GP(sp)
- REG_S x5, PT_T0(sp)
- REG_S x6, PT_T1(sp)
- REG_S x7, PT_T2(sp)
- REG_S x8, PT_S0(sp)
- REG_S x9, PT_S1(sp)
- REG_S x10, PT_A0(sp)
- REG_S x11, PT_A1(sp)
- REG_S x12, PT_A2(sp)
- REG_S x13, PT_A3(sp)
- REG_S x14, PT_A4(sp)
- REG_S x15, PT_A5(sp)
- REG_S x16, PT_A6(sp)
- REG_S x17, PT_A7(sp)
- REG_S x18, PT_S2(sp)
- REG_S x19, PT_S3(sp)
- REG_S x20, PT_S4(sp)
- REG_S x21, PT_S5(sp)
- REG_S x22, PT_S6(sp)
- REG_S x23, PT_S7(sp)
- REG_S x24, PT_S8(sp)
- REG_S x25, PT_S9(sp)
- REG_S x26, PT_S10(sp)
- REG_S x27, PT_S11(sp)
- REG_S x28, PT_T3(sp)
- REG_S x29, PT_T4(sp)
- REG_S x30, PT_T5(sp)
- REG_S x31, PT_T6(sp)
+ save_gp

REG_L s0, TASK_TI_KERNEL_SP(tp)
csrr s1, CSR_STATUS
diff --git a/arch/riscv/kernel/mcount-dyn.S b/arch/riscv/kernel/mcount-dyn.S
index d171eca623b6..1b4b0aecf4f5 100644
--- a/arch/riscv/kernel/mcount-dyn.S
+++ b/arch/riscv/kernel/mcount-dyn.S
@@ -68,35 +68,8 @@
REG_L x1, PT_EPC(sp)

REG_S x2, PT_SP(sp)
- REG_S x3, PT_GP(sp)
REG_S x4, PT_TP(sp)
- REG_S x5, PT_T0(sp)
- REG_S x6, PT_T1(sp)
- REG_S x7, PT_T2(sp)
- REG_S x8, PT_S0(sp)
- REG_S x9, PT_S1(sp)
- REG_S x10, PT_A0(sp)
- REG_S x11, PT_A1(sp)
- REG_S x12, PT_A2(sp)
- REG_S x13, PT_A3(sp)
- REG_S x14, PT_A4(sp)
- REG_S x15, PT_A5(sp)
- REG_S x16, PT_A6(sp)
- REG_S x17, PT_A7(sp)
- REG_S x18, PT_S2(sp)
- REG_S x19, PT_S3(sp)
- REG_S x20, PT_S4(sp)
- REG_S x21, PT_S5(sp)
- REG_S x22, PT_S6(sp)
- REG_S x23, PT_S7(sp)
- REG_S x24, PT_S8(sp)
- REG_S x25, PT_S9(sp)
- REG_S x26, PT_S10(sp)
- REG_S x27, PT_S11(sp)
- REG_S x28, PT_T3(sp)
- REG_S x29, PT_T4(sp)
- REG_S x30, PT_T5(sp)
- REG_S x31, PT_T6(sp)
+ save_gp
.endm

.macro RESTORE_ALL
@@ -106,35 +79,8 @@
addi sp, sp, -PT_SIZE_ON_STACK
REG_L x1, PT_EPC(sp)
REG_L x2, PT_SP(sp)
- REG_L x3, PT_GP(sp)
REG_L x4, PT_TP(sp)
- REG_L x5, PT_T0(sp)
- REG_L x6, PT_T1(sp)
- REG_L x7, PT_T2(sp)
- REG_L x8, PT_S0(sp)
- REG_L x9, PT_S1(sp)
- REG_L x10, PT_A0(sp)
- REG_L x11, PT_A1(sp)
- REG_L x12, PT_A2(sp)
- REG_L x13, PT_A3(sp)
- REG_L x14, PT_A4(sp)
- REG_L x15, PT_A5(sp)
- REG_L x16, PT_A6(sp)
- REG_L x17, PT_A7(sp)
- REG_L x18, PT_S2(sp)
- REG_L x19, PT_S3(sp)
- REG_L x20, PT_S4(sp)
- REG_L x21, PT_S5(sp)
- REG_L x22, PT_S6(sp)
- REG_L x23, PT_S7(sp)
- REG_L x24, PT_S8(sp)
- REG_L x25, PT_S9(sp)
- REG_L x26, PT_S10(sp)
- REG_L x27, PT_S11(sp)
- REG_L x28, PT_T3(sp)
- REG_L x29, PT_T4(sp)
- REG_L x30, PT_T5(sp)
- REG_L x31, PT_T6(sp)
+ restore_gp

addi sp, sp, PT_SIZE_ON_STACK
addi sp, sp, SZREG
--
2.34.1

2022-09-29 04:59:58

by Guo Ren

[permalink] [raw]

Subject: Re: [PATCH v2 4/4] riscv: entry: consolidate general regs saving into save_gp

On Thu, Sep 29, 2022 at 12:29 AM Jisheng Zhang <[email protected]> wrote:
>
> Consolidate the saving/restoring GPs(except ra, sp and tp) into
> save_gp/restore_gp macro.
>
> No functional change intended.
>
> Signed-off-by: Jisheng Zhang <[email protected]>
> ---
> arch/riscv/include/asm/asm.h | 65 +++++++++++++++++++++++++
> arch/riscv/kernel/entry.S | 87 ++--------------------------------
> arch/riscv/kernel/mcount-dyn.S | 58 +----------------------
> 3 files changed, 70 insertions(+), 140 deletions(-)
>
> diff --git a/arch/riscv/include/asm/asm.h b/arch/riscv/include/asm/asm.h
> index 1b471ff73178..2f3b49536e9d 100644
> --- a/arch/riscv/include/asm/asm.h
> +++ b/arch/riscv/include/asm/asm.h
> @@ -68,6 +68,7 @@
> #endif
>
> #ifdef __ASSEMBLY__
> +#include <asm/asm-offsets.h>
>
> /* Common assembly source macros */
>
> @@ -80,6 +81,70 @@
> .endr
> .endm
>
> + /* save all GPs except ra, sp and tp */
> + .macro save_gp
How about leave x3(gp) out of the macro, and define:
.marco save_from_x5_to_x31
.marco restore_from_x5_to_x31

> + REG_S x3, PT_GP(sp)
> + REG_S x5, PT_T0(sp)
> + REG_S x6, PT_T1(sp)
> + REG_S x7, PT_T2(sp)
> + REG_S x8, PT_S0(sp)
> + REG_S x9, PT_S1(sp)
> + REG_S x10, PT_A0(sp)
> + REG_S x11, PT_A1(sp)
> + REG_S x12, PT_A2(sp)
> + REG_S x13, PT_A3(sp)
> + REG_S x14, PT_A4(sp)
> + REG_S x15, PT_A5(sp)
> + REG_S x16, PT_A6(sp)
> + REG_S x17, PT_A7(sp)
> + REG_S x18, PT_S2(sp)
> + REG_S x19, PT_S3(sp)
> + REG_S x20, PT_S4(sp)
> + REG_S x21, PT_S5(sp)
> + REG_S x22, PT_S6(sp)
> + REG_S x23, PT_S7(sp)
> + REG_S x24, PT_S8(sp)
> + REG_S x25, PT_S9(sp)
> + REG_S x26, PT_S10(sp)
> + REG_S x27, PT_S11(sp)
> + REG_S x28, PT_T3(sp)
> + REG_S x29, PT_T4(sp)
> + REG_S x30, PT_T5(sp)
> + REG_S x31, PT_T6(sp)
> + .endm
> +
> + /* restore all GPs except ra, sp and tp */
> + .macro restore_gp
> + REG_L x3, PT_GP(sp)
> + REG_L x5, PT_T0(sp)
> + REG_L x6, PT_T1(sp)
> + REG_L x7, PT_T2(sp)
> + REG_L x8, PT_S0(sp)
> + REG_L x9, PT_S1(sp)
> + REG_L x10, PT_A0(sp)
> + REG_L x11, PT_A1(sp)
> + REG_L x12, PT_A2(sp)
> + REG_L x13, PT_A3(sp)
> + REG_L x14, PT_A4(sp)
> + REG_L x15, PT_A5(sp)
> + REG_L x16, PT_A6(sp)
> + REG_L x17, PT_A7(sp)
> + REG_L x18, PT_S2(sp)
> + REG_L x19, PT_S3(sp)
> + REG_L x20, PT_S4(sp)
> + REG_L x21, PT_S5(sp)
> + REG_L x22, PT_S6(sp)
> + REG_L x23, PT_S7(sp)
> + REG_L x24, PT_S8(sp)
> + REG_L x25, PT_S9(sp)
> + REG_L x26, PT_S10(sp)
> + REG_L x27, PT_S11(sp)
> + REG_L x28, PT_T3(sp)
> + REG_L x29, PT_T4(sp)
> + REG_L x30, PT_T5(sp)
> + REG_L x31, PT_T6(sp)
> + .endm
> +
> #endif /* __ASSEMBLY__ */
>
> #endif /* _ASM_RISCV_ASM_H */
> diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
> index 5a6171a90d81..a90f17ed2822 100644
> --- a/arch/riscv/kernel/entry.S
> +++ b/arch/riscv/kernel/entry.S
> @@ -40,34 +40,7 @@ _save_context:
> REG_L sp, TASK_TI_KERNEL_SP(tp)
> addi sp, sp, -(PT_SIZE_ON_STACK)
> REG_S x1, PT_RA(sp)
> - REG_S x3, PT_GP(sp)
> - REG_S x5, PT_T0(sp)
> - REG_S x6, PT_T1(sp)
> - REG_S x7, PT_T2(sp)
> - REG_S x8, PT_S0(sp)
> - REG_S x9, PT_S1(sp)
> - REG_S x10, PT_A0(sp)
> - REG_S x11, PT_A1(sp)
> - REG_S x12, PT_A2(sp)
> - REG_S x13, PT_A3(sp)
> - REG_S x14, PT_A4(sp)
> - REG_S x15, PT_A5(sp)
> - REG_S x16, PT_A6(sp)
> - REG_S x17, PT_A7(sp)
> - REG_S x18, PT_S2(sp)
> - REG_S x19, PT_S3(sp)
> - REG_S x20, PT_S4(sp)
> - REG_S x21, PT_S5(sp)
> - REG_S x22, PT_S6(sp)
> - REG_S x23, PT_S7(sp)
> - REG_S x24, PT_S8(sp)
> - REG_S x25, PT_S9(sp)
> - REG_S x26, PT_S10(sp)
> - REG_S x27, PT_S11(sp)
> - REG_S x28, PT_T3(sp)
> - REG_S x29, PT_T4(sp)
> - REG_S x30, PT_T5(sp)
> - REG_S x31, PT_T6(sp)
> + save_gp
>
> /*
> * Disable user-mode memory access as it should only be set in the
> @@ -182,35 +155,8 @@ ENTRY(ret_from_exception)
> csrw CSR_STATUS, a0
>
> REG_L x1, PT_RA(sp)
> - REG_L x3, PT_GP(sp)
> REG_L x4, PT_TP(sp)
> - REG_L x5, PT_T0(sp)
> - REG_L x6, PT_T1(sp)
> - REG_L x7, PT_T2(sp)
> - REG_L x8, PT_S0(sp)
> - REG_L x9, PT_S1(sp)
> - REG_L x10, PT_A0(sp)
> - REG_L x11, PT_A1(sp)
> - REG_L x12, PT_A2(sp)
> - REG_L x13, PT_A3(sp)
> - REG_L x14, PT_A4(sp)
> - REG_L x15, PT_A5(sp)
> - REG_L x16, PT_A6(sp)
> - REG_L x17, PT_A7(sp)
> - REG_L x18, PT_S2(sp)
> - REG_L x19, PT_S3(sp)
> - REG_L x20, PT_S4(sp)
> - REG_L x21, PT_S5(sp)
> - REG_L x22, PT_S6(sp)
> - REG_L x23, PT_S7(sp)
> - REG_L x24, PT_S8(sp)
> - REG_L x25, PT_S9(sp)
> - REG_L x26, PT_S10(sp)
> - REG_L x27, PT_S11(sp)
> - REG_L x28, PT_T3(sp)
> - REG_L x29, PT_T4(sp)
> - REG_L x30, PT_T5(sp)
> - REG_L x31, PT_T6(sp)
> + restore_gp
>
> REG_L x2, PT_SP(sp)
>
> @@ -237,34 +183,7 @@ ENTRY(handle_kernel_stack_overflow)
>
> //save context to overflow stack
> REG_S x1, PT_RA(sp)
> - REG_S x3, PT_GP(sp)
> - REG_S x5, PT_T0(sp)
> - REG_S x6, PT_T1(sp)
> - REG_S x7, PT_T2(sp)
> - REG_S x8, PT_S0(sp)
> - REG_S x9, PT_S1(sp)
> - REG_S x10, PT_A0(sp)
> - REG_S x11, PT_A1(sp)
> - REG_S x12, PT_A2(sp)
> - REG_S x13, PT_A3(sp)
> - REG_S x14, PT_A4(sp)
> - REG_S x15, PT_A5(sp)
> - REG_S x16, PT_A6(sp)
> - REG_S x17, PT_A7(sp)
> - REG_S x18, PT_S2(sp)
> - REG_S x19, PT_S3(sp)
> - REG_S x20, PT_S4(sp)
> - REG_S x21, PT_S5(sp)
> - REG_S x22, PT_S6(sp)
> - REG_S x23, PT_S7(sp)
> - REG_S x24, PT_S8(sp)
> - REG_S x25, PT_S9(sp)
> - REG_S x26, PT_S10(sp)
> - REG_S x27, PT_S11(sp)
> - REG_S x28, PT_T3(sp)
> - REG_S x29, PT_T4(sp)
> - REG_S x30, PT_T5(sp)
> - REG_S x31, PT_T6(sp)
> + save_gp
>
> REG_L s0, TASK_TI_KERNEL_SP(tp)
> csrr s1, CSR_STATUS
> diff --git a/arch/riscv/kernel/mcount-dyn.S b/arch/riscv/kernel/mcount-dyn.S
> index d171eca623b6..1b4b0aecf4f5 100644
> --- a/arch/riscv/kernel/mcount-dyn.S
> +++ b/arch/riscv/kernel/mcount-dyn.S
> @@ -68,35 +68,8 @@
> REG_L x1, PT_EPC(sp)
>
> REG_S x2, PT_SP(sp)
> - REG_S x3, PT_GP(sp)
> REG_S x4, PT_TP(sp)
> - REG_S x5, PT_T0(sp)
> - REG_S x6, PT_T1(sp)
> - REG_S x7, PT_T2(sp)
> - REG_S x8, PT_S0(sp)
> - REG_S x9, PT_S1(sp)
> - REG_S x10, PT_A0(sp)
> - REG_S x11, PT_A1(sp)
> - REG_S x12, PT_A2(sp)
> - REG_S x13, PT_A3(sp)
> - REG_S x14, PT_A4(sp)
> - REG_S x15, PT_A5(sp)
> - REG_S x16, PT_A6(sp)
> - REG_S x17, PT_A7(sp)
> - REG_S x18, PT_S2(sp)
> - REG_S x19, PT_S3(sp)
> - REG_S x20, PT_S4(sp)
> - REG_S x21, PT_S5(sp)
> - REG_S x22, PT_S6(sp)
> - REG_S x23, PT_S7(sp)
> - REG_S x24, PT_S8(sp)
> - REG_S x25, PT_S9(sp)
> - REG_S x26, PT_S10(sp)
> - REG_S x27, PT_S11(sp)
> - REG_S x28, PT_T3(sp)
> - REG_S x29, PT_T4(sp)
> - REG_S x30, PT_T5(sp)
> - REG_S x31, PT_T6(sp)
> + save_gp
> .endm
>
> .macro RESTORE_ALL
> @@ -106,35 +79,8 @@
> addi sp, sp, -PT_SIZE_ON_STACK
> REG_L x1, PT_EPC(sp)
> REG_L x2, PT_SP(sp)
> - REG_L x3, PT_GP(sp)
> REG_L x4, PT_TP(sp)
> - REG_L x5, PT_T0(sp)
> - REG_L x6, PT_T1(sp)
> - REG_L x7, PT_T2(sp)
> - REG_L x8, PT_S0(sp)
> - REG_L x9, PT_S1(sp)
> - REG_L x10, PT_A0(sp)
> - REG_L x11, PT_A1(sp)
> - REG_L x12, PT_A2(sp)
> - REG_L x13, PT_A3(sp)
> - REG_L x14, PT_A4(sp)
> - REG_L x15, PT_A5(sp)
> - REG_L x16, PT_A6(sp)
> - REG_L x17, PT_A7(sp)
> - REG_L x18, PT_S2(sp)
> - REG_L x19, PT_S3(sp)
> - REG_L x20, PT_S4(sp)
> - REG_L x21, PT_S5(sp)
> - REG_L x22, PT_S6(sp)
> - REG_L x23, PT_S7(sp)
> - REG_L x24, PT_S8(sp)
> - REG_L x25, PT_S9(sp)
> - REG_L x26, PT_S10(sp)
> - REG_L x27, PT_S11(sp)
> - REG_L x28, PT_T3(sp)
> - REG_L x29, PT_T4(sp)
> - REG_L x30, PT_T5(sp)
> - REG_L x31, PT_T6(sp)
> + restore_gp
>
> addi sp, sp, PT_SIZE_ON_STACK
> addi sp, sp, SZREG
> --
> 2.34.1
>

--
Best Regards
Guo Ren

2022-09-29 16:14:30

by Jisheng Zhang

[permalink] [raw]

Subject: Re: [PATCH v2 4/4] riscv: entry: consolidate general regs saving into save_gp

On Thu, Sep 29, 2022 at 11:59:00AM +0800, Guo Ren wrote:
> On Thu, Sep 29, 2022 at 12:29 AM Jisheng Zhang <[email protected]> wrote:
> >
> > Consolidate the saving/restoring GPs(except ra, sp and tp) into
> > save_gp/restore_gp macro.
> >
> > No functional change intended.
> >
> > Signed-off-by: Jisheng Zhang <[email protected]>
> > ---
> > arch/riscv/include/asm/asm.h | 65 +++++++++++++++++++++++++
> > arch/riscv/kernel/entry.S | 87 ++--------------------------------
> > arch/riscv/kernel/mcount-dyn.S | 58 +----------------------
> > 3 files changed, 70 insertions(+), 140 deletions(-)
> >
> > diff --git a/arch/riscv/include/asm/asm.h b/arch/riscv/include/asm/asm.h
> > index 1b471ff73178..2f3b49536e9d 100644
> > --- a/arch/riscv/include/asm/asm.h
> > +++ b/arch/riscv/include/asm/asm.h
> > @@ -68,6 +68,7 @@
> > #endif
> >
> > #ifdef __ASSEMBLY__
> > +#include <asm/asm-offsets.h>
> >
> > /* Common assembly source macros */
> >
> > @@ -80,6 +81,70 @@
> > .endr
> > .endm
> >
> > + /* save all GPs except ra, sp and tp */
> > + .macro save_gp
> How about leave x3(gp) out of the macro, and define:
> .marco save_from_x5_to_x31
> .marco restore_from_x5_to_x31

Good idea, will do in next version.

Thanks

2022-10-19 03:17:34

by Guo Ren

[permalink] [raw]

Subject: Re: [PATCH v2 4/4] riscv: entry: consolidate general regs saving into save_gp

On Fri, Sep 30, 2022 at 12:11 AM Jisheng Zhang <[email protected]> wrote:
>
> On Thu, Sep 29, 2022 at 11:59:00AM +0800, Guo Ren wrote:
> > On Thu, Sep 29, 2022 at 12:29 AM Jisheng Zhang <[email protected]> wrote:
> > >
> > > Consolidate the saving/restoring GPs(except ra, sp and tp) into
> > > save_gp/restore_gp macro.
> > >
> > > No functional change intended.
> > >
> > > Signed-off-by: Jisheng Zhang <[email protected]>
> > > ---
> > > arch/riscv/include/asm/asm.h | 65 +++++++++++++++++++++++++
> > > arch/riscv/kernel/entry.S | 87 ++--------------------------------
> > > arch/riscv/kernel/mcount-dyn.S | 58 +----------------------
> > > 3 files changed, 70 insertions(+), 140 deletions(-)
> > >
> > > diff --git a/arch/riscv/include/asm/asm.h b/arch/riscv/include/asm/asm.h
> > > index 1b471ff73178..2f3b49536e9d 100644
> > > --- a/arch/riscv/include/asm/asm.h
> > > +++ b/arch/riscv/include/asm/asm.h
> > > @@ -68,6 +68,7 @@
> > > #endif
> > >
> > > #ifdef __ASSEMBLY__
> > > +#include <asm/asm-offsets.h>
> > >
> > > /* Common assembly source macros */
> > >
> > > @@ -80,6 +81,70 @@
> > > .endr
> > > .endm
> > >
> > > + /* save all GPs except ra, sp and tp */
> > > + .macro save_gp
> > How about leave x3(gp) out of the macro, and define:
> > .marco save_from_x5_to_x31
> > .marco restore_from_x5_to_x31
>
> Good idea, will do in next version.

Where is the next version?

I want to involve the patch in my generic entry series, it would help
in the coding convention of the entry code.

>
> Thanks

--
Best Regards
Guo Ren

2022-10-19 13:59:08

by Jisheng Zhang

[permalink] [raw]

Subject: Re: [PATCH v2 4/4] riscv: entry: consolidate general regs saving into save_gp

On Wed, Oct 19, 2022 at 10:55:09AM +0800, Guo Ren wrote:
> On Fri, Sep 30, 2022 at 12:11 AM Jisheng Zhang <[email protected]> wrote:
> >
> > On Thu, Sep 29, 2022 at 11:59:00AM +0800, Guo Ren wrote:
> > > On Thu, Sep 29, 2022 at 12:29 AM Jisheng Zhang <[email protected]> wrote:
> > > >
> > > > Consolidate the saving/restoring GPs(except ra, sp and tp) into
> > > > save_gp/restore_gp macro.
> > > >
> > > > No functional change intended.
> > > >
> > > > Signed-off-by: Jisheng Zhang <[email protected]>
> > > > ---
> > > > arch/riscv/include/asm/asm.h | 65 +++++++++++++++++++++++++
> > > > arch/riscv/kernel/entry.S | 87 ++--------------------------------
> > > > arch/riscv/kernel/mcount-dyn.S | 58 +----------------------
> > > > 3 files changed, 70 insertions(+), 140 deletions(-)
> > > >
> > > > diff --git a/arch/riscv/include/asm/asm.h b/arch/riscv/include/asm/asm.h
> > > > index 1b471ff73178..2f3b49536e9d 100644
> > > > --- a/arch/riscv/include/asm/asm.h
> > > > +++ b/arch/riscv/include/asm/asm.h
> > > > @@ -68,6 +68,7 @@
> > > > #endif
> > > >
> > > > #ifdef __ASSEMBLY__
> > > > +#include <asm/asm-offsets.h>
> > > >
> > > > /* Common assembly source macros */
> > > >
> > > > @@ -80,6 +81,70 @@
> > > > .endr
> > > > .endm
> > > >
> > > > + /* save all GPs except ra, sp and tp */
> > > > + .macro save_gp
> > > How about leave x3(gp) out of the macro, and define:
> > > .marco save_from_x5_to_x31
> > > .marco restore_from_x5_to_x31
> >
> > Good idea, will do in next version.
>
> Where is the next version?
>
> I want to involve the patch in my generic entry series, it would help
> in the coding convention of the entry code.

Hi,

Here is the v3:
https://lore.kernel.org/linux-riscv/[email protected]/T/#t

thanks very much