This patch series adds a new compatible for the Display SubSyetem
controller on TI's AM625 SoC. It further adds the required support for
the same in the tidss driver. The AM625-DSS is a newer version of the DSS
from the AM65X version with the major change being the addition of
another OLDI TX. With the help of 2 OLDI TXes, the AM625 DSS supports
OLDI displays with a resolution of upto 2K.
This patch set further adds support for the OLDI on AM625, and is, in
essence, the second version of the following patch series:
https://patchwork.kernel.org/project/dri-devel/list/?series=660970&state=%2A&archive=both
The changes in the above-mentioned series forced some re-works in this
series, and are better reviewed as a single set.
TODO:
- Support for OLDI Bridges that work on clone / dual-link modes is yet
to be added.
- The pixel clock for the OLDI VP passes through a clock divider, which
was being explicitly set in previous series, but that was not the
right way. That patch has been dropped and a newer implementation is
in works.
Note:
- Due to lack of hardware, only dual-link mode has been tested.
Changelog:
V5:
- Rebase for current merge window
- Add max DT ports in DSS features
- Combine the OLDI support series
(Changes from OLDI support series v1)
- Address Tomi Valkeinen's comments
1. Update the OLDI link detection approach
2. Add port #3 for 2nd OLDI TX
3. Configure 2 panel-bridges for cloned panels
4. Drop the OLDI clock set patch
5. Drop rgb565-to-888 patch
V4:
- Rebase for current merge window
- Add acked and reviewed by tags
V3:
- Change yaml enum in alphabetical order
- Correct a typo
V2:
- Remove redundant regsiter array
Aradhya Bhatia (6):
dt-bindings: display: ti,am65x-dss: Add am625 dss compatible
dt-bindings: display: ti: am65x-dss: Add new port for am625-dss
drm/tidss: Add support for AM625 DSS
drm/tidss: Add support to configure OLDI mode for am625-dss.
drm/tidss: Add IO CTRL and Power support for OLDI TX in am625
drm/tidss: Enable Dual and Duplicate Modes for OLDI
.../bindings/display/ti/ti,am65x-dss.yaml | 22 ++-
drivers/gpu/drm/tidss/tidss_dispc.c | 155 ++++++++++++++++--
drivers/gpu/drm/tidss/tidss_dispc.h | 11 ++
drivers/gpu/drm/tidss/tidss_dispc_regs.h | 6 +
drivers/gpu/drm/tidss/tidss_drv.c | 1 +
drivers/gpu/drm/tidss/tidss_drv.h | 3 +
drivers/gpu/drm/tidss/tidss_kms.c | 146 ++++++++++++++---
7 files changed, 304 insertions(+), 40 deletions(-)
--
2.37.0
The AM625 DSS IP contains 2 OLDI TXes which can work to enable 2
duplicated displays of smaller resolutions or enable a single Dual Link
display with a higher resolution (1920x1200).
Configure the necessary register to enable and disable the OLDI TXes
with necessary modes configurations.
Signed-off-by: Aradhya Bhatia <[email protected]>
---
drivers/gpu/drm/tidss/tidss_dispc.c | 28 ++++++++++++++++++++++++++--
1 file changed, 26 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c
index 68444e0cd8d7..fd7f49535f0c 100644
--- a/drivers/gpu/drm/tidss/tidss_dispc.c
+++ b/drivers/gpu/drm/tidss/tidss_dispc.c
@@ -1003,8 +1003,8 @@ static void dispc_enable_oldi(struct dispc_device *dispc, u32 hw_videoport,
int count = 0;
/*
- * For the moment DUALMODESYNC, MASTERSLAVE, MODE, and SRC
- * bits of DISPC_VP_DSS_OLDI_CFG are set statically to 0.
+ * For the moment MASTERSLAVE, and SRC bits of DISPC_VP_DSS_OLDI_CFG are
+ * set statically to 0.
*/
if (fmt->data_width == 24)
@@ -1021,6 +1021,30 @@ static void dispc_enable_oldi(struct dispc_device *dispc, u32 hw_videoport,
oldi_cfg |= BIT(0); /* ENABLE */
+ switch (dispc->oldi_mode) {
+ case OLDI_MODE_OFF:
+ oldi_cfg &= ~BIT(0); /* DISABLE */
+ break;
+
+ case OLDI_SINGLE_LINK_SINGLE_MODE:
+ /* All configuration is done for this mode. */
+ break;
+
+ case OLDI_SINGLE_LINK_CLONE_MODE:
+ oldi_cfg |= BIT(5); /* CLONE MODE */
+ break;
+
+ case OLDI_DUAL_LINK_MODE:
+ oldi_cfg |= BIT(11); /* DUALMODESYNC */
+ oldi_cfg |= BIT(3); /* data-mapping field also indicates dual-link mode */
+ break;
+
+ default:
+ dev_warn(dispc->dev, "%s: Incorrect oldi mode. Returning.\n",
+ __func__);
+ return;
+ }
+
dispc_vp_write(dispc, hw_videoport, DISPC_VP_DSS_OLDI_CFG, oldi_cfg);
while (!(oldi_reset_bit & dispc_read(dispc, DSS_SYSSTATUS)) &&
--
2.37.0
On 28/09/2022 20:52, Aradhya Bhatia wrote:
> The AM625 DSS IP contains 2 OLDI TXes which can work to enable 2
> duplicated displays of smaller resolutions or enable a single Dual Link
> display with a higher resolution (1920x1200).
>
> Configure the necessary register to enable and disable the OLDI TXes
> with necessary modes configurations.
>
> Signed-off-by: Aradhya Bhatia <[email protected]>
> ---
> drivers/gpu/drm/tidss/tidss_dispc.c | 28 ++++++++++++++++++++++++++--
> 1 file changed, 26 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c
> index 68444e0cd8d7..fd7f49535f0c 100644
> --- a/drivers/gpu/drm/tidss/tidss_dispc.c
> +++ b/drivers/gpu/drm/tidss/tidss_dispc.c
> @@ -1003,8 +1003,8 @@ static void dispc_enable_oldi(struct dispc_device *dispc, u32 hw_videoport,
> int count = 0;
>
> /*
> - * For the moment DUALMODESYNC, MASTERSLAVE, MODE, and SRC
> - * bits of DISPC_VP_DSS_OLDI_CFG are set statically to 0.
> + * For the moment MASTERSLAVE, and SRC bits of DISPC_VP_DSS_OLDI_CFG are
> + * set statically to 0.
> */
While at it, maybe say "are always set to 0". At least to me that's much
more understandable.
>
> if (fmt->data_width == 24)
> @@ -1021,6 +1021,30 @@ static void dispc_enable_oldi(struct dispc_device *dispc, u32 hw_videoport,
>
> oldi_cfg |= BIT(0); /* ENABLE */
>
> + switch (dispc->oldi_mode) {
> + case OLDI_MODE_OFF:
> + oldi_cfg &= ~BIT(0); /* DISABLE */
Hmm, do we call this if OLDI_MODE_OFF? The current code always enabled
OLDI here, so I presume we call this only when we actually want to
enable it.
> + break;
> +
> + case OLDI_SINGLE_LINK_SINGLE_MODE:
> + /* All configuration is done for this mode. */
> + break;
> +
> + case OLDI_SINGLE_LINK_CLONE_MODE:
> + oldi_cfg |= BIT(5); /* CLONE MODE */
> + break;
> +
> + case OLDI_DUAL_LINK_MODE:
> + oldi_cfg |= BIT(11); /* DUALMODESYNC */
> + oldi_cfg |= BIT(3); /* data-mapping field also indicates dual-link mode */
> + break;
> +
> + default:
> + dev_warn(dispc->dev, "%s: Incorrect oldi mode. Returning.\n",
> + __func__);
> + return;
> + }
> +
> dispc_vp_write(dispc, hw_videoport, DISPC_VP_DSS_OLDI_CFG, oldi_cfg);
>
> while (!(oldi_reset_bit & dispc_read(dispc, DSS_SYSSTATUS)) &&