Generally, riscv ISA extensions are fixed for any specific hardware
platform, that's to say, the hart features won't change any more
after booting, this chacteristic make it straightforward to use
static branch to check one specific ISA extension is supported or not
to optimize performance.
However, some ISA extensions such as SVPBMT and ZICBOM are handled
via. the alternative sequences.
Basically, for ease of maintenance, we prefer to use static branches
in C code, but recently, Samuel found that the static branch usage in
cpu_relax() breaks building with CONFIG_CC_OPTIMIZE_FOR_SIZE[1]. As
Samuel pointed out, "Having a static branch in cpu_relax() is
problematic because that function is widely inlined, including in some
quite complex functions like in the VDSO. A quick measurement shows
this static branch is responsible by itself for around 40% of the jump
table."
Samuel's findings pointed out one of a few downsides of static branches
usage in C code to handle ISA extensions detected at boot time:
static branch's metadata in the __jump_table section, which is not
discarded after ISA extensions are finalized, wastes some space.
I want to try to solve the issue for all possible dynamic handling of
ISA extensions at boot time. Inspired by Mark[2], this patch introduces
riscv_has_extension_*() helpers, which work like static branches but
are patched using alternatives, thus the metadata can be freed after
patching.
[1]https://lore.kernel.org/linux-riscv/[email protected]/
[2]https://lore.kernel.org/linux-arm-kernel/[email protected]/
Jisheng Zhang (8):
riscv: move riscv_noncoherent_supported() out of ZICBOM probe
riscv: cpufeature: detect RISCV_ALTERNATIVES_EARLY_BOOT earlier
riscv: hwcap: make ISA extension ids can be used in asm
riscv: cpufeature: extend riscv_cpufeature_patch_func to all ISA
extensions
riscv: introduce riscv_has_extension_[un]likely()
riscv: fpu: switch has_fpu() to riscv_has_extension_likely()
riscv: cpu_relax: switch to riscv_has_extension_likely()
riscv: remove riscv_isa_ext_keys[] array and related usage
arch/riscv/include/asm/errata_list.h | 9 +--
arch/riscv/include/asm/hwcap.h | 94 ++++++++++++++-----------
arch/riscv/include/asm/switch_to.h | 3 +-
arch/riscv/include/asm/vdso/processor.h | 2 +-
arch/riscv/kernel/cpufeature.c | 78 +++-----------------
arch/riscv/kernel/setup.c | 4 ++
6 files changed, 71 insertions(+), 119 deletions(-)
--
2.37.2
Switch cpu_relax() from statich branch to the new helper
riscv_has_extension_likely()
Signed-off-by: Jisheng Zhang <[email protected]>
---
arch/riscv/include/asm/vdso/processor.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/include/asm/vdso/processor.h b/arch/riscv/include/asm/vdso/processor.h
index 1e4f8b4aef79..fb30480f36a0 100644
--- a/arch/riscv/include/asm/vdso/processor.h
+++ b/arch/riscv/include/asm/vdso/processor.h
@@ -10,7 +10,7 @@
static inline void cpu_relax(void)
{
- if (!static_branch_likely(&riscv_isa_ext_keys[RISCV_ISA_EXT_KEY_ZIHINTPAUSE])) {
+ if (!riscv_has_extension_likely(RISCV_ISA_EXT_ZIHINTPAUSE)) {
#ifdef __riscv_muldiv
int dummy;
/* In lieu of a halt instruction, induce a long-latency stall. */
--
2.37.2
Hi Jisheng,
I love your patch! Yet something to improve:
[auto build test ERROR on linus/master]
[also build test ERROR on v6.0]
[cannot apply to next-20221006]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Jisheng-Zhang/riscv-improve-boot-time-isa-extensions-handling/20221006-152055
base: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 833477fce7a14d43ae4c07f8ddc32fa5119471a2
config: riscv-randconfig-r005-20221003
compiler: clang version 16.0.0 (https://github.com/llvm/llvm-project 791a7ae1ba3efd6bca96338e10ffde557ba83920)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install riscv cross compiling tool for clang build
# apt-get install binutils-riscv64-linux-gnu
# https://github.com/intel-lab-lkp/linux/commit/322e8b44d0cc6b6b2bd179469be16d70df012a1e
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Jisheng-Zhang/riscv-improve-boot-time-isa-extensions-handling/20221006-152055
git checkout 322e8b44d0cc6b6b2bd179469be16d70df012a1e
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=riscv prepare
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <[email protected]>
All errors (new ones prefixed by >>):
In file included from <built-in>:4:
In file included from lib/vdso/gettimeofday.c:5:
In file included from include/vdso/datapage.h:17:
In file included from include/vdso/processor.h:10:
In file included from arch/riscv/include/asm/vdso/processor.h:9:
>> arch/riscv/include/asm/hwcap.h:107:2: error: invalid operand for inline asm constraint 'i'
ALTERNATIVE("j %l[l_no]", "nop", 0, %[ext], 1)
^
arch/riscv/include/asm/alternative-macros.h:187:2: note: expanded from macro 'ALTERNATIVE'
_ALTERNATIVE_CFG(old_content, new_content, vendor_id, errata_id, CONFIG_k)
^
arch/riscv/include/asm/alternative-macros.h:113:2: note: expanded from macro '_ALTERNATIVE_CFG'
__ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, IS_ENABLED(CONFIG_k))
^
arch/riscv/include/asm/alternative-macros.h:103:2: note: expanded from macro '__ALTERNATIVE_CFG'
"886 :\n" \
^
In file included from <built-in>:4:
In file included from lib/vdso/gettimeofday.c:5:
In file included from include/vdso/datapage.h:17:
In file included from include/vdso/processor.h:10:
In file included from arch/riscv/include/asm/vdso/processor.h:9:
>> arch/riscv/include/asm/hwcap.h:107:2: error: invalid operand for inline asm constraint 'i'
arch/riscv/include/asm/alternative-macros.h:187:2: note: expanded from macro 'ALTERNATIVE'
_ALTERNATIVE_CFG(old_content, new_content, vendor_id, errata_id, CONFIG_k)
^
arch/riscv/include/asm/alternative-macros.h:113:2: note: expanded from macro '_ALTERNATIVE_CFG'
__ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, IS_ENABLED(CONFIG_k))
^
arch/riscv/include/asm/alternative-macros.h:103:2: note: expanded from macro '__ALTERNATIVE_CFG'
"886 :\n" \
^
2 errors generated.
make[2]: *** [scripts/Makefile.build:250: arch/riscv/kernel/vdso/vgettimeofday.o] Error 1
make[2]: Target 'include/generated/vdso-offsets.h' not remade because of errors.
make[1]: *** [arch/riscv/Makefile:128: vdso_prepare] Error 2
make[1]: Target 'prepare' not remade because of errors.
make: *** [Makefile:231: __sub-make] Error 2
make: Target 'prepare' not remade because of errors.
vim +/i +107 arch/riscv/include/asm/hwcap.h
c360cbec351103 Jisheng Zhang 2022-05-22 99
ab85f9f404c012 Jisheng Zhang 2022-10-06 100 static __always_inline bool
ab85f9f404c012 Jisheng Zhang 2022-10-06 101 riscv_has_extension_likely(const unsigned long ext)
ab85f9f404c012 Jisheng Zhang 2022-10-06 102 {
ab85f9f404c012 Jisheng Zhang 2022-10-06 103 compiletime_assert(ext < RISCV_ISA_EXT_ID_MAX,
ab85f9f404c012 Jisheng Zhang 2022-10-06 104 "ext must be < RISCV_ISA_EXT_ID_MAX");
ab85f9f404c012 Jisheng Zhang 2022-10-06 105
ab85f9f404c012 Jisheng Zhang 2022-10-06 106 asm_volatile_goto(
ab85f9f404c012 Jisheng Zhang 2022-10-06 @107 ALTERNATIVE("j %l[l_no]", "nop", 0, %[ext], 1)
ab85f9f404c012 Jisheng Zhang 2022-10-06 108 :
ab85f9f404c012 Jisheng Zhang 2022-10-06 109 : [ext] "i" (ext)
ab85f9f404c012 Jisheng Zhang 2022-10-06 110 :
ab85f9f404c012 Jisheng Zhang 2022-10-06 111 : l_no);
ab85f9f404c012 Jisheng Zhang 2022-10-06 112
ab85f9f404c012 Jisheng Zhang 2022-10-06 113 return true;
ab85f9f404c012 Jisheng Zhang 2022-10-06 114 l_no:
ab85f9f404c012 Jisheng Zhang 2022-10-06 115 return false;
ab85f9f404c012 Jisheng Zhang 2022-10-06 116 }
ab85f9f404c012 Jisheng Zhang 2022-10-06 117
--
0-DAY CI Kernel Test Service
https://01.org/lkp
On Thu, Oct 06, 2022 at 03:08:17PM +0800, Jisheng Zhang wrote:
> Switch cpu_relax() from statich branch to the new helper
> riscv_has_extension_likely()
>
> Signed-off-by: Jisheng Zhang <[email protected]>
> ---
> arch/riscv/include/asm/vdso/processor.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/riscv/include/asm/vdso/processor.h b/arch/riscv/include/asm/vdso/processor.h
> index 1e4f8b4aef79..fb30480f36a0 100644
> --- a/arch/riscv/include/asm/vdso/processor.h
> +++ b/arch/riscv/include/asm/vdso/processor.h
> @@ -10,7 +10,7 @@
>
> static inline void cpu_relax(void)
> {
> - if (!static_branch_likely(&riscv_isa_ext_keys[RISCV_ISA_EXT_KEY_ZIHINTPAUSE])) {
> + if (!riscv_has_extension_likely(RISCV_ISA_EXT_ZIHINTPAUSE)) {
> #ifdef __riscv_muldiv
> int dummy;
> /* In lieu of a halt instruction, induce a long-latency stall. */
> --
> 2.37.2
>
Reviewed-by: Andrew Jones <[email protected]>
Am Donnerstag, 6. Oktober 2022, 09:08:17 CEST schrieb Jisheng Zhang:
> Switch cpu_relax() from statich branch to the new helper
> riscv_has_extension_likely()
>
> Signed-off-by: Jisheng Zhang <[email protected]>
Reviewed-by: Heiko Stuebner <[email protected]>
Hi Jisheng,
I love your patch! Yet something to improve:
[auto build test ERROR on linus/master]
[also build test ERROR on v6.0]
[cannot apply to next-20221007]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Jisheng-Zhang/riscv-improve-boot-time-isa-extensions-handling/20221006-152055
base: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 833477fce7a14d43ae4c07f8ddc32fa5119471a2
config: riscv-randconfig-r003-20221003
compiler: clang version 16.0.0 (https://github.com/llvm/llvm-project 791a7ae1ba3efd6bca96338e10ffde557ba83920)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install riscv cross compiling tool for clang build
# apt-get install binutils-riscv64-linux-gnu
# https://github.com/intel-lab-lkp/linux/commit/322e8b44d0cc6b6b2bd179469be16d70df012a1e
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Jisheng-Zhang/riscv-improve-boot-time-isa-extensions-handling/20221006-152055
git checkout 322e8b44d0cc6b6b2bd179469be16d70df012a1e
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=riscv prepare
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <[email protected]>
All errors (new ones prefixed by >>):
>> ld.lld: error: relocation R_RISCV_64 cannot be used against symbol '.Ltmp0'; recompile with -fPIC
>>> defined in arch/riscv/kernel/vdso/vgettimeofday.o
>>> referenced by vgettimeofday.c
>>> arch/riscv/kernel/vdso/vgettimeofday.o:(.alternative+0x0)
--
>> ld.lld: error: relocation R_RISCV_64 cannot be used against symbol '.Ltmp2'; recompile with -fPIC
>>> defined in arch/riscv/kernel/vdso/vgettimeofday.o
>>> referenced by vgettimeofday.c
>>> arch/riscv/kernel/vdso/vgettimeofday.o:(.alternative+0x8)
--
>> ld.lld: error: relocation R_RISCV_64 cannot be used against symbol '.Ltmp20'; recompile with -fPIC
>>> defined in arch/riscv/kernel/vdso/vgettimeofday.o
>>> referenced by vgettimeofday.c
>>> arch/riscv/kernel/vdso/vgettimeofday.o:(.alternative+0xB4)
--
>> ld.lld: error: relocation R_RISCV_64 cannot be used against symbol '.Ltmp22'; recompile with -fPIC
>>> defined in arch/riscv/kernel/vdso/vgettimeofday.o
>>> referenced by vgettimeofday.c
>>> arch/riscv/kernel/vdso/vgettimeofday.o:(.alternative+0xBC)
--
>> ld.lld: error: relocation R_RISCV_64 cannot be used against symbol '.Ltmp4'; recompile with -fPIC
>>> defined in arch/riscv/kernel/vdso/vgettimeofday.o
>>> referenced by vgettimeofday.c
>>> arch/riscv/kernel/vdso/vgettimeofday.o:(.alternative+0x24)
--
>> ld.lld: error: relocation R_RISCV_64 cannot be used against symbol '.Ltmp6'; recompile with -fPIC
>>> defined in arch/riscv/kernel/vdso/vgettimeofday.o
>>> referenced by vgettimeofday.c
>>> arch/riscv/kernel/vdso/vgettimeofday.o:(.alternative+0x2C)
--
>> ld.lld: error: relocation R_RISCV_64 cannot be used against symbol '.Ltmp8'; recompile with -fPIC
>>> defined in arch/riscv/kernel/vdso/vgettimeofday.o
>>> referenced by vgettimeofday.c
>>> arch/riscv/kernel/vdso/vgettimeofday.o:(.alternative+0x48)
--
>> ld.lld: error: relocation R_RISCV_64 cannot be used against symbol '.Ltmp10'; recompile with -fPIC
>>> defined in arch/riscv/kernel/vdso/vgettimeofday.o
>>> referenced by vgettimeofday.c
>>> arch/riscv/kernel/vdso/vgettimeofday.o:(.alternative+0x50)
--
>> ld.lld: error: relocation R_RISCV_64 cannot be used against symbol '.Ltmp12'; recompile with -fPIC
>>> defined in arch/riscv/kernel/vdso/vgettimeofday.o
>>> referenced by vgettimeofday.c
>>> arch/riscv/kernel/vdso/vgettimeofday.o:(.alternative+0x6C)
--
>> ld.lld: error: relocation R_RISCV_64 cannot be used against symbol '.Ltmp14'; recompile with -fPIC
>>> defined in arch/riscv/kernel/vdso/vgettimeofday.o
>>> referenced by vgettimeofday.c
>>> arch/riscv/kernel/vdso/vgettimeofday.o:(.alternative+0x74)
--
>> ld.lld: error: relocation R_RISCV_64 cannot be used against symbol '.Ltmp16'; recompile with -fPIC
>>> defined in arch/riscv/kernel/vdso/vgettimeofday.o
>>> referenced by vgettimeofday.c
>>> arch/riscv/kernel/vdso/vgettimeofday.o:(.alternative+0x90)
..
--
0-DAY CI Kernel Test Service
https://01.org/lkp
On Thu, Oct 06, 2022 at 03:08:10PM +0800, Jisheng Zhang wrote:
> Generally, riscv ISA extensions are fixed for any specific hardware
> platform, that's to say, the hart features won't change any more
> after booting, this chacteristic make it straightforward to use
> static branch to check one specific ISA extension is supported or not
> to optimize performance.
>
> However, some ISA extensions such as SVPBMT and ZICBOM are handled
> via. the alternative sequences.
>
> Basically, for ease of maintenance, we prefer to use static branches
> in C code, but recently, Samuel found that the static branch usage in
> cpu_relax() breaks building with CONFIG_CC_OPTIMIZE_FOR_SIZE[1]. As
> Samuel pointed out, "Having a static branch in cpu_relax() is
> problematic because that function is widely inlined, including in some
> quite complex functions like in the VDSO. A quick measurement shows
> this static branch is responsible by itself for around 40% of the jump
> table."
>
> Samuel's findings pointed out one of a few downsides of static branches
> usage in C code to handle ISA extensions detected at boot time:
> static branch's metadata in the __jump_table section, which is not
> discarded after ISA extensions are finalized, wastes some space.
>
> I want to try to solve the issue for all possible dynamic handling of
> ISA extensions at boot time. Inspired by Mark[2], this patch introduces
> riscv_has_extension_*() helpers, which work like static branches but
> are patched using alternatives, thus the metadata can be freed after
> patching.
>
> [1]https://lore.kernel.org/linux-riscv/[email protected]/
> [2]https://lore.kernel.org/linux-arm-kernel/[email protected]/
>
>
> Jisheng Zhang (8):
> riscv: move riscv_noncoherent_supported() out of ZICBOM probe
> riscv: cpufeature: detect RISCV_ALTERNATIVES_EARLY_BOOT earlier
> riscv: hwcap: make ISA extension ids can be used in asm
> riscv: cpufeature: extend riscv_cpufeature_patch_func to all ISA
> extensions
> riscv: introduce riscv_has_extension_[un]likely()
> riscv: fpu: switch has_fpu() to riscv_has_extension_likely()
> riscv: cpu_relax: switch to riscv_has_extension_likely()
> riscv: remove riscv_isa_ext_keys[] array and related usage
>
> arch/riscv/include/asm/errata_list.h | 9 +--
> arch/riscv/include/asm/hwcap.h | 94 ++++++++++++++-----------
> arch/riscv/include/asm/switch_to.h | 3 +-
> arch/riscv/include/asm/vdso/processor.h | 2 +-
> arch/riscv/kernel/cpufeature.c | 78 +++-----------------
> arch/riscv/kernel/setup.c | 4 ++
> 6 files changed, 71 insertions(+), 119 deletions(-)
>
> --
> 2.37.2
>
This series also needs a KVM patch like below.
Thanks,
drew
From 7069a6fa488ec4efad190884fe5fcf4a1c37753a Mon Sep 17 00:00:00 2001
From: Andrew Jones <[email protected]>
Date: Thu, 13 Oct 2022 18:16:10 +0200
Subject: [PATCH] riscv: KVM: Switch has_svinval() to
riscv_has_extension_unlikely()
Content-type: text/plain
Switch has_svinval() from static branch to the new helper
riscv_has_extension_unlikely().
Signed-off-by: Andrew Jones <[email protected]>
---
arch/riscv/kvm/tlb.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/riscv/kvm/tlb.c b/arch/riscv/kvm/tlb.c
index 309d79b3e5cd..aa3da18ad873 100644
--- a/arch/riscv/kvm/tlb.c
+++ b/arch/riscv/kvm/tlb.c
@@ -15,8 +15,7 @@
#include <asm/hwcap.h>
#include <asm/insn-def.h>
-#define has_svinval() \
- static_branch_unlikely(&riscv_isa_ext_keys[RISCV_ISA_EXT_KEY_SVINVAL])
+#define has_svinval() riscv_has_extension_unlikely(RISCV_ISA_EXT_SVINVAL)
void kvm_riscv_local_hfence_gvma_vmid_gpa(unsigned long vmid,
gpa_t gpa, gpa_t gpsz,
--
2.37.3
On Thu, Oct 06, 2022 at 03:08:10PM +0800, Jisheng Zhang wrote:
> Generally, riscv ISA extensions are fixed for any specific hardware
> platform, that's to say, the hart features won't change any more
> after booting, this chacteristic make it straightforward to use
> static branch to check one specific ISA extension is supported or not
> to optimize performance.
>
> However, some ISA extensions such as SVPBMT and ZICBOM are handled
> via. the alternative sequences.
>
> Basically, for ease of maintenance, we prefer to use static branches
> in C code, but recently, Samuel found that the static branch usage in
> cpu_relax() breaks building with CONFIG_CC_OPTIMIZE_FOR_SIZE[1]. As
> Samuel pointed out, "Having a static branch in cpu_relax() is
> problematic because that function is widely inlined, including in some
> quite complex functions like in the VDSO. A quick measurement shows
> this static branch is responsible by itself for around 40% of the jump
> table."
>
> Samuel's findings pointed out one of a few downsides of static branches
> usage in C code to handle ISA extensions detected at boot time:
> static branch's metadata in the __jump_table section, which is not
> discarded after ISA extensions are finalized, wastes some space.
>
> I want to try to solve the issue for all possible dynamic handling of
> ISA extensions at boot time. Inspired by Mark[2], this patch introduces
> riscv_has_extension_*() helpers, which work like static branches but
> are patched using alternatives, thus the metadata can be freed after
> patching.
>
> [1]https://lore.kernel.org/linux-riscv/[email protected]/
> [2]https://lore.kernel.org/linux-arm-kernel/[email protected]/
>
>
> Jisheng Zhang (8):
> riscv: move riscv_noncoherent_supported() out of ZICBOM probe
> riscv: cpufeature: detect RISCV_ALTERNATIVES_EARLY_BOOT earlier
> riscv: hwcap: make ISA extension ids can be used in asm
> riscv: cpufeature: extend riscv_cpufeature_patch_func to all ISA
> extensions
> riscv: introduce riscv_has_extension_[un]likely()
> riscv: fpu: switch has_fpu() to riscv_has_extension_likely()
> riscv: cpu_relax: switch to riscv_has_extension_likely()
> riscv: remove riscv_isa_ext_keys[] array and related usage
>
> arch/riscv/include/asm/errata_list.h | 9 +--
> arch/riscv/include/asm/hwcap.h | 94 ++++++++++++++-----------
> arch/riscv/include/asm/switch_to.h | 3 +-
> arch/riscv/include/asm/vdso/processor.h | 2 +-
> arch/riscv/kernel/cpufeature.c | 78 +++-----------------
> arch/riscv/kernel/setup.c | 4 ++
> 6 files changed, 71 insertions(+), 119 deletions(-)
>
> --
> 2.37.2
>
Hi Jisheng,
I just tried building this with LLVM=1 and fails to compile with messages
like
ld.lld: error: relocation R_RISCV_64 cannot be used against symbol '.Ltmp1'; recompile with -fPIC
>>> defined in arch/riscv/kernel/vdso/vgettimeofday.o
>>> referenced by vgettimeofday.c
>>> arch/riscv/kernel/vdso/vgettimeofday.o:(.alternative+0x0)
It does compile and boot with CC=clang and binutils 2.39, where my clang
version is 14.0.5 (Fedora 14.0.5-1.fc36).
Thanks,
drew
On Sat, Oct 29, 2022 at 11:56:09AM +0200, Andrew Jones wrote:
> On Thu, Oct 06, 2022 at 03:08:10PM +0800, Jisheng Zhang wrote:
> > Generally, riscv ISA extensions are fixed for any specific hardware
> > platform, that's to say, the hart features won't change any more
> > after booting, this chacteristic make it straightforward to use
> > static branch to check one specific ISA extension is supported or not
> > to optimize performance.
> >
> > However, some ISA extensions such as SVPBMT and ZICBOM are handled
> > via. the alternative sequences.
> >
> > Basically, for ease of maintenance, we prefer to use static branches
> > in C code, but recently, Samuel found that the static branch usage in
> > cpu_relax() breaks building with CONFIG_CC_OPTIMIZE_FOR_SIZE[1]. As
> > Samuel pointed out, "Having a static branch in cpu_relax() is
> > problematic because that function is widely inlined, including in some
> > quite complex functions like in the VDSO. A quick measurement shows
> > this static branch is responsible by itself for around 40% of the jump
> > table."
> >
> > Samuel's findings pointed out one of a few downsides of static branches
> > usage in C code to handle ISA extensions detected at boot time:
> > static branch's metadata in the __jump_table section, which is not
> > discarded after ISA extensions are finalized, wastes some space.
> >
> > I want to try to solve the issue for all possible dynamic handling of
> > ISA extensions at boot time. Inspired by Mark[2], this patch introduces
> > riscv_has_extension_*() helpers, which work like static branches but
> > are patched using alternatives, thus the metadata can be freed after
> > patching.
> >
> > [1]https://lore.kernel.org/linux-riscv/[email protected]/
> > [2]https://lore.kernel.org/linux-arm-kernel/[email protected]/
> >
> >
> > Jisheng Zhang (8):
> > riscv: move riscv_noncoherent_supported() out of ZICBOM probe
> > riscv: cpufeature: detect RISCV_ALTERNATIVES_EARLY_BOOT earlier
> > riscv: hwcap: make ISA extension ids can be used in asm
> > riscv: cpufeature: extend riscv_cpufeature_patch_func to all ISA
> > extensions
> > riscv: introduce riscv_has_extension_[un]likely()
> > riscv: fpu: switch has_fpu() to riscv_has_extension_likely()
> > riscv: cpu_relax: switch to riscv_has_extension_likely()
> > riscv: remove riscv_isa_ext_keys[] array and related usage
> >
> > arch/riscv/include/asm/errata_list.h | 9 +--
> > arch/riscv/include/asm/hwcap.h | 94 ++++++++++++++-----------
> > arch/riscv/include/asm/switch_to.h | 3 +-
> > arch/riscv/include/asm/vdso/processor.h | 2 +-
> > arch/riscv/kernel/cpufeature.c | 78 +++-----------------
> > arch/riscv/kernel/setup.c | 4 ++
> > 6 files changed, 71 insertions(+), 119 deletions(-)
> >
> > --
> > 2.37.2
> >
>
> Hi Jisheng,
Hi Andrew,
>
> I just tried building this with LLVM=1 and fails to compile with messages
> like
>
> ld.lld: error: relocation R_RISCV_64 cannot be used against symbol '.Ltmp1'; recompile with -fPIC
> >>> defined in arch/riscv/kernel/vdso/vgettimeofday.o
> >>> referenced by vgettimeofday.c
> >>> arch/riscv/kernel/vdso/vgettimeofday.o:(.alternative+0x0)
>
> It does compile and boot with CC=clang and binutils 2.39, where my clang
> version is 14.0.5 (Fedora 14.0.5-1.fc36).
Thanks for the information, I also noticed that lkp reported similar
error. I'm investigating the issue.
Thanks
On Sat, Oct 29, 2022 at 11:56:09AM +0200, Andrew Jones wrote:
> On Thu, Oct 06, 2022 at 03:08:10PM +0800, Jisheng Zhang wrote:
> > Generally, riscv ISA extensions are fixed for any specific hardware
> > platform, that's to say, the hart features won't change any more
> > after booting, this chacteristic make it straightforward to use
> > static branch to check one specific ISA extension is supported or not
> > to optimize performance.
> >
> > However, some ISA extensions such as SVPBMT and ZICBOM are handled
> > via. the alternative sequences.
> >
> > Basically, for ease of maintenance, we prefer to use static branches
> > in C code, but recently, Samuel found that the static branch usage in
> > cpu_relax() breaks building with CONFIG_CC_OPTIMIZE_FOR_SIZE[1]. As
> > Samuel pointed out, "Having a static branch in cpu_relax() is
> > problematic because that function is widely inlined, including in some
> > quite complex functions like in the VDSO. A quick measurement shows
> > this static branch is responsible by itself for around 40% of the jump
> > table."
> >
> > Samuel's findings pointed out one of a few downsides of static branches
> > usage in C code to handle ISA extensions detected at boot time:
> > static branch's metadata in the __jump_table section, which is not
> > discarded after ISA extensions are finalized, wastes some space.
> >
> > I want to try to solve the issue for all possible dynamic handling of
> > ISA extensions at boot time. Inspired by Mark[2], this patch introduces
> > riscv_has_extension_*() helpers, which work like static branches but
> > are patched using alternatives, thus the metadata can be freed after
> > patching.
> >
> > [1]https://lore.kernel.org/linux-riscv/[email protected]/
> > [2]https://lore.kernel.org/linux-arm-kernel/[email protected]/
> >
> >
> > Jisheng Zhang (8):
> > riscv: move riscv_noncoherent_supported() out of ZICBOM probe
> > riscv: cpufeature: detect RISCV_ALTERNATIVES_EARLY_BOOT earlier
> > riscv: hwcap: make ISA extension ids can be used in asm
> > riscv: cpufeature: extend riscv_cpufeature_patch_func to all ISA
> > extensions
> > riscv: introduce riscv_has_extension_[un]likely()
> > riscv: fpu: switch has_fpu() to riscv_has_extension_likely()
> > riscv: cpu_relax: switch to riscv_has_extension_likely()
> > riscv: remove riscv_isa_ext_keys[] array and related usage
> >
> > arch/riscv/include/asm/errata_list.h | 9 +--
> > arch/riscv/include/asm/hwcap.h | 94 ++++++++++++++-----------
> > arch/riscv/include/asm/switch_to.h | 3 +-
> > arch/riscv/include/asm/vdso/processor.h | 2 +-
> > arch/riscv/kernel/cpufeature.c | 78 +++-----------------
> > arch/riscv/kernel/setup.c | 4 ++
> > 6 files changed, 71 insertions(+), 119 deletions(-)
> >
> > --
> > 2.37.2
> >
>
> Hi Jisheng,
>
> I just tried building this with LLVM=1 and fails to compile with messages
> like
>
> ld.lld: error: relocation R_RISCV_64 cannot be used against symbol '.Ltmp1'; recompile with -fPIC
> >>> defined in arch/riscv/kernel/vdso/vgettimeofday.o
> >>> referenced by vgettimeofday.c
> >>> arch/riscv/kernel/vdso/vgettimeofday.o:(.alternative+0x0)
>
> It does compile and boot with CC=clang and binutils 2.39, where my clang
> version is 14.0.5 (Fedora 14.0.5-1.fc36).
Hi Andrew,
Below is a quick fix.
PS: I think I need add two or more patches to apply alternatives in the
vDSO. But currently only Zihintpause is affected.
Will send out a new version.
diff --git a/arch/riscv/kernel/vdso/Makefile b/arch/riscv/kernel/vdso/Makefile
index f2e065671e4d..522b78477bab 100644
--- a/arch/riscv/kernel/vdso/Makefile
+++ b/arch/riscv/kernel/vdso/Makefile
@@ -44,7 +44,7 @@ $(obj)/vdso.o: $(obj)/vdso.so
# link rule for the .so file, .lds has to be first
$(obj)/vdso.so.dbg: $(obj)/vdso.lds $(obj-vdso) FORCE
$(call if_changed,vdsold)
-LDFLAGS_vdso.so.dbg = -shared -S -soname=linux-vdso.so.1 \
+LDFLAGS_vdso.so.dbg = -shared -z notext -S -soname=linux-vdso.so.1 \
>
> Thanks,
> drew