Hi,
Changes since v3
================
1. All patches with subject: "use common TLMM schema":
Drop properties and required items which are already provided by common TLMM
schema.
The change against v3 is non-trivial, however I retained reviewed-by tags.
2. Add Rb tags.
Changes since v2
================
1. ipq6018-cp01-c1: do not switch to blsp1 (Robert).
2. pinctrl: qcom,ipq6018: correct BLSP6->BLSP0 functions: new patch.
3. Drop quotes from $ref when not needed (Rob).
4. Add Rb tags. Few patches from v1 got review from Rob, but I changed them in
v2 significantly, so I did not keep these Rb tags.
Changes since v1
================
v1: https://lore.kernel.org/linux-devicetree/[email protected]/T/#t
1. As Stephan suggested, move check for function on non-GPIO pins to common
TLMM schema. This affects few commits in the set named:
"use common TLMM schema"
"do not require function on non-GPIOs"
Overview
========
This is the third, independent patchset around Qualcomm pinctrl in recent days:
1. First round of TLMM fixes: merged
2. LPASS fixes:
https://lore.kernel.org/linux-devicetree/[email protected]/T/#t
3. ARMv7 TLMM fixes: *THIS PATCHSET*
4. ARMv8 remaining TLMM fixes: v2 send:
https://lore.kernel.org/linux-devicetree/[email protected]/
Dependencies
============
1. No dependencies.
2. dt-bindings are independent of DTS patches.
Best regards,
Krzysztof
Krzysztof Kozlowski (34):
arm64: dts: qcom: ipq6018-cp01-c1: use BLSPI1 pins
arm64: dts: qcom: ipq6018: align TLMM pin configuration with DT schema
ARM: dts: qcom: sdx55: add gpio-ranges to TLMM pinctrl
ARM: dts: qcom: sdx55: align TLMM pin configuration with DT schema
ARM: dts: qcom: msm8226: align TLMM pin configuration with DT schema
ARM: dts: qcom: msm8974: align TLMM pin configuration with DT schema
dt-bindings: pinctrl: qcom,tlmm-common: add common check for function
dt-bindings: pinctrl: qcom,ipq6018: add qpic_pad function
dt-bindings: pinctrl: qcom,ipq6018: correct BLSP6->BLSP0 functions
dt-bindings: pinctrl: qcom,ipq6018: increase number of pins in pinmux
dt-bindings: pinctrl: qcom,ipq6018: fix matching pin config
dt-bindings: pinctrl: qcom,ipq6018: use common TLMM schema
dt-bindings: pinctrl: qcom,ipq6018: fix indentation in example
dt-bindings: pinctrl: qcom,msm8226: fix matching pin config
dt-bindings: pinctrl: qcom,msm8226: use common TLMM schema
dt-bindings: pinctrl: qcom,msm8226: add functions and input-enable
dt-bindings: pinctrl: qcom,msm8226: fix indentation in example
dt-bindings: pinctrl: qcom,msm8909-tlmm: fix matching pin config
dt-bindings: pinctrl: qcom,msm8909-tlmm: do not require function on
non-GPIOs
dt-bindings: pinctrl: qcom,msm8909-tlmm: fix indentation in example
dt-bindings: pinctrl: qcom,msm8953: fix matching pin config
dt-bindings: pinctrl: qcom,msm8953: use common TLMM schema
dt-bindings: pinctrl: qcom,msm8953: fix indentation in example
dt-bindings: pinctrl: qcom,mdm9607: do not require function on
non-GPIOs
dt-bindings: pinctrl: qcom,mdm9607: fix indentation in example
dt-bindings: pinctrl: qcom,qcm2290: fix matching pin config
dt-bindings: pinctrl: qcom,qcm2290: use common TLMM schema
dt-bindings: pinctrl: qcom,sdx55: fix matching pin config
dt-bindings: pinctrl: qcom,sdx55: use common TLMM schema
dt-bindings: pinctrl: qcom,sdx55: fix indentation in example
dt-bindings: pinctrl: qcom,sdx65: fix matching pin config
dt-bindings: pinctrl: qcom,sdx65: use common TLMM schema
dt-bindings: pinctrl: qcom,sc7280: fix matching pin config
dt-bindings: pinctrl: qcom,sc8280xp: fix indentation in example
(remaining piece)
.../pinctrl/qcom,ipq6018-pinctrl.yaml | 95 ++++++++-----------
.../pinctrl/qcom,mdm9607-pinctrl.yaml | 23 +++--
.../pinctrl/qcom,msm8226-pinctrl.yaml | 91 ++++++++----------
.../bindings/pinctrl/qcom,msm8909-tlmm.yaml | 64 ++++++-------
.../pinctrl/qcom,msm8953-pinctrl.yaml | 81 +++++++---------
.../pinctrl/qcom,qcm2290-pinctrl.yaml | 41 ++------
.../bindings/pinctrl/qcom,sc7280-pinctrl.yaml | 14 ++-
.../pinctrl/qcom,sc8280xp-pinctrl.yaml | 4 +-
.../bindings/pinctrl/qcom,sdx55-pinctrl.yaml | 79 +++++++--------
.../bindings/pinctrl/qcom,sdx65-pinctrl.yaml | 39 +++-----
.../bindings/pinctrl/qcom,tlmm-common.yaml | 20 +++-
arch/arm/boot/dts/qcom-apq8026-lg-lenok.dts | 6 +-
arch/arm/boot/dts/qcom-msm8226.dtsi | 24 ++---
.../qcom-msm8974-lge-nexus5-hammerhead.dts | 30 +++---
.../boot/dts/qcom-sdx55-telit-fn980-tlb.dts | 45 +++------
arch/arm/boot/dts/qcom-sdx55.dtsi | 1 +
arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 6 +-
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 4 +-
18 files changed, 290 insertions(+), 377 deletions(-)
--
2.34.1
Add required gpio-ranges property to TLMM pinctrl node:
qcom-sdx55-mtp.dtb: pinctrl@f100000: 'gpio-ranges' is a required property
Signed-off-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Bjorn Andersson <[email protected]>
Reviewed-by: Konrad Dybcio <[email protected]>
---
arch/arm/boot/dts/qcom-sdx55.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi
index c72540223fa9..f1c0dab40992 100644
--- a/arch/arm/boot/dts/qcom-sdx55.dtsi
+++ b/arch/arm/boot/dts/qcom-sdx55.dtsi
@@ -559,6 +559,7 @@ tlmm: pinctrl@f100000 {
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
+ gpio-ranges = <&tlmm 0 0 109>;
};
sram@1468f000 {
--
2.34.1
The pin controller driver has BLSP functions from 0 to 5, not 1 to 6.
Add missing blsp0_i2c, blsp0_spi (already used in ipq6018-cp01-c1) and
blsp0_uart. Drop blsp6_i2c and blsp6_spi.
This fixes dtbs_check warning:
ipq6018-cp01-c1.dtb: pinctrl@1000000: spi-0-state: 'oneOf' conditional failed, one must be fixed:
'bias-pull-down', 'drive-strength', 'function', 'pins' do not match any of the regexes: '-pins$', 'pinctrl-[0-9]+'
'blsp0_spi' is not one of ['adsp_ext', 'alsp_int', .....
Signed-off-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
.../devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.yaml | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.yaml
index 0bd1aded132d..76698cd97e8c 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.yaml
@@ -72,12 +72,12 @@ patternProperties:
enum: [ adsp_ext, alsp_int, atest_bbrx0, atest_bbrx1, atest_char,
atest_char0, atest_char1, atest_char2, atest_char3, atest_combodac,
atest_gpsadc0, atest_gpsadc1, atest_tsens, atest_wlan0,
- atest_wlan1, backlight_en, bimc_dte0, bimc_dte1, blsp1_i2c,
- blsp2_i2c, blsp3_i2c, blsp4_i2c, blsp5_i2c, blsp6_i2c, blsp1_spi,
+ atest_wlan1, backlight_en, bimc_dte0, bimc_dte1, blsp0_i2c, blsp1_i2c,
+ blsp2_i2c, blsp3_i2c, blsp4_i2c, blsp5_i2c, blsp0_spi, blsp1_spi,
blsp1_spi_cs1, blsp1_spi_cs2, blsp1_spi_cs3, blsp2_spi,
blsp2_spi_cs1, blsp2_spi_cs2, blsp2_spi_cs3, blsp3_spi,
blsp3_spi_cs1, blsp3_spi_cs2, blsp3_spi_cs3, blsp4_spi, blsp5_spi,
- blsp6_spi, blsp1_uart, blsp2_uart, blsp1_uim, blsp2_uim, cam1_rst,
+ blsp0_uart, blsp1_uart, blsp2_uart, blsp1_uim, blsp2_uim, cam1_rst,
cam1_standby, cam_mclk0, cam_mclk1, cci_async, cci_i2c, cci_timer0,
cci_timer1, cci_timer2, cdc_pdm0, codec_mad, dbg_out, display_5v,
dmic0_clk, dmic0_data, dsi_rst, ebi0_wrcdc, euro_us, ext_lpass,
--
2.34.1
DT schema expects TLMM pin configuration nodes to be named with
'-state' suffix and their optional children with '-pins' suffix.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Bjorn Andersson <[email protected]>
Reviewed-by: Konrad Dybcio <[email protected]>
---
.../qcom-msm8974-lge-nexus5-hammerhead.dts | 30 +++++++++----------
1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts
index 6daceaa87802..8138f37233aa 100644
--- a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts
+++ b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts
@@ -573,43 +573,43 @@ bcrmf@1 {
};
&tlmm {
- sdc1_on: sdc1-on {
- clk {
+ sdc1_on: sdc1-on-state {
+ clk-pins {
pins = "sdc1_clk";
drive-strength = <16>;
bias-disable;
};
- cmd-data {
+ cmd-data-pins {
pins = "sdc1_cmd", "sdc1_data";
drive-strength = <10>;
bias-pull-up;
};
};
- sdc2_on: sdc2-on {
- clk {
+ sdc2_on: sdc2-on-state {
+ clk-pins {
pins = "sdc2_clk";
drive-strength = <6>;
bias-disable;
};
- cmd-data {
+ cmd-data-pins {
pins = "sdc2_cmd", "sdc2_data";
drive-strength = <6>;
bias-pull-up;
};
};
- mpu6515_pin: mpu6515 {
+ mpu6515_pin: mpu6515-state {
pins = "gpio73";
function = "gpio";
bias-disable;
input-enable;
};
- touch_pin: touch {
- int {
+ touch_pin: touch-state {
+ int-pins {
pins = "gpio5";
function = "gpio";
@@ -618,7 +618,7 @@ int {
input-enable;
};
- reset {
+ reset-pins {
pins = "gpio8";
function = "gpio";
@@ -627,25 +627,25 @@ reset {
};
};
- panel_pin: panel {
+ panel_pin: panel-state {
pins = "gpio12";
function = "mdp_vsync";
drive-strength = <2>;
bias-disable;
};
- bt_pin: bt {
- hostwake {
+ bt_pin: bt-state {
+ hostwake-pins {
pins = "gpio42";
function = "gpio";
};
- devwake {
+ devwake-pins {
pins = "gpio62";
function = "gpio";
};
- shutdown {
+ shutdown-pins {
pins = "gpio41";
function = "gpio";
};
--
2.34.1
The TLMM pin controller follows generic pin-controller bindings, so
should have subnodes with '-state' and '-pins'. Otherwise the subnodes
(level one and two) are not properly matched. This method also unifies
the bindings with other Qualcomm TLMM and LPASS pinctrl bindings.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Bjorn Andersson <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
.../bindings/pinctrl/qcom,ipq6018-pinctrl.yaml | 15 +++++++++++----
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.yaml
index 7202e2af200b..735a8786cb13 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.yaml
@@ -42,10 +42,17 @@ properties:
gpio-ranges:
maxItems: 1
-#PIN CONFIGURATION NODES
patternProperties:
- '-pinmux$':
- type: object
+ "-state$":
+ oneOf:
+ - $ref: "#/$defs/qcom-ipq6018-tlmm-state"
+ - patternProperties:
+ "-pins$":
+ $ref: "#/$defs/qcom-ipq6018-tlmm-state"
+ additionalProperties: false
+
+$defs:
+ qcom-ipq6018-tlmm-state:
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
@@ -146,7 +153,7 @@ examples:
#gpio-cells = <2>;
gpio-ranges = <&tlmm 0 0 80>;
- serial3-pinmux {
+ serial3-state {
pins = "gpio44", "gpio45";
function = "blsp2_uart";
drive-strength = <8>;
--
2.34.1
Reference common Qualcomm TLMM pin controller schema, to bring common
properties, other pinctrl schemas and additional checks, like function
required only for GPIOs.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Bjorn Andersson <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
Changes since v3:
1. Drop properties and required items which are already provided by
common TLMM schema.
---
.../pinctrl/qcom,ipq6018-pinctrl.yaml | 34 ++++---------------
1 file changed, 6 insertions(+), 28 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.yaml
index 735a8786cb13..e02bc15e0ad5 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.yaml
@@ -20,27 +20,12 @@ properties:
reg:
maxItems: 1
- interrupts:
- description: Specifies the TLMM summary IRQ
- maxItems: 1
-
+ interrupts: true
interrupt-controller: true
-
- '#interrupt-cells':
- description:
- Specifies the PIN numbers and Flags, as defined in defined in
- include/dt-bindings/interrupt-controller/irq.h
- const: 2
-
+ "#interrupt-cells": true
gpio-controller: true
-
- '#gpio-cells':
- description: Specifying the pin number and flags, as defined in
- include/dt-bindings/gpio/gpio.h
- const: 2
-
- gpio-ranges:
- maxItems: 1
+ "#gpio-cells": true
+ gpio-ranges: true
patternProperties:
"-state$":
@@ -56,7 +41,7 @@ $defs:
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
- $ref: "/schemas/pinctrl/pincfg-node.yaml"
+ $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
properties:
pins:
@@ -121,22 +106,15 @@ $defs:
required:
- pins
- - function
additionalProperties: false
allOf:
- - $ref: "pinctrl.yaml#"
+ - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
required:
- compatible
- reg
- - interrupts
- - interrupt-controller
- - '#interrupt-cells'
- - gpio-controller
- - '#gpio-cells'
- - gpio-ranges
additionalProperties: false
--
2.34.1
Bindings example should be indented with 4-spaces.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Bjorn Andersson <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
.../pinctrl/qcom,ipq6018-pinctrl.yaml | 34 +++++++++----------
1 file changed, 17 insertions(+), 17 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.yaml
index e02bc15e0ad5..bf84649593ef 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.yaml
@@ -120,21 +120,21 @@ additionalProperties: false
examples:
- |
- #include <dt-bindings/interrupt-controller/arm-gic.h>
- tlmm: pinctrl@1000000 {
- compatible = "qcom,ipq6018-pinctrl";
- reg = <0x01000000 0x300000>;
- interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-controller;
- #interrupt-cells = <2>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&tlmm 0 0 80>;
-
- serial3-state {
- pins = "gpio44", "gpio45";
- function = "blsp2_uart";
- drive-strength = <8>;
- bias-pull-down;
- };
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ tlmm: pinctrl@1000000 {
+ compatible = "qcom,ipq6018-pinctrl";
+ reg = <0x01000000 0x300000>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&tlmm 0 0 80>;
+
+ serial3-state {
+ pins = "gpio44", "gpio45";
+ function = "blsp2_uart";
+ drive-strength = <8>;
+ bias-pull-down;
};
+ };
--
2.34.1
The IPQ6018 pinctrl driver supports qpic_pad and DTS already uses it:
'qpic_pad' is not one of ['adsp_ext', 'alsp_int', 'atest_bbrx0', ...
Signed-off-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Bjorn Andersson <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
.../devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.yaml | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.yaml
index 9c6e2cb0c6a5..0bd1aded132d 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.yaml
@@ -92,9 +92,9 @@ patternProperties:
qdss_ctitrig_in_b0, qdss_ctitrig_in_b1, qdss_ctitrig_out_a0,
qdss_ctitrig_out_a1, qdss_ctitrig_out_b0, qdss_ctitrig_out_b1,
qdss_traceclk_a, qdss_traceclk_b, qdss_tracectl_a, qdss_tracectl_b,
- qdss_tracedata_a, qdss_tracedata_b, reset_n, sd_card, sd_write,
- sec_mi2s, smb_int, ssbi_wtr0, ssbi_wtr1, uim1, uim2, uim3,
- uim_batt, wcss_bt, wcss_fm, wcss_wlan, webcam1_rst ]
+ qdss_tracedata_a, qdss_tracedata_b, qpic_pad, reset_n, sd_card,
+ sd_write, sec_mi2s, smb_int, ssbi_wtr0, ssbi_wtr1, uim1, uim2,
+ uim3, uim_batt, wcss_bt, wcss_fm, wcss_wlan, webcam1_rst ]
drive-strength:
enum: [2, 4, 6, 8, 10, 12, 14, 16]
--
2.34.1
One pinxmux node can have more than 4 pins to configure:
['gpio1', 'gpio3', 'gpio4', 'gpio5', 'gpio6', 'gpio7', 'gpio8', 'gpio10', 'gpio11', 'gpio12', 'gpio13', 'gpio14', 'gpio15', 'gpio17'] is too long
Signed-off-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Bjorn Andersson <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
.../devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.yaml
index 76698cd97e8c..7202e2af200b 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.yaml
@@ -63,7 +63,7 @@ patternProperties:
sdc2_data, qdsd_cmd, qdsd_data0, qdsd_data1, qdsd_data2,
qdsd_data3 ]
minItems: 1
- maxItems: 4
+ maxItems: 16
function:
description:
--
2.34.1
Reference common Qualcomm TLMM pin controller schema, to bring common
properties, other pinctrl schemas and additional checks, like function
required only for GPIOs.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Bjorn Andersson <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
Changes since v3:
1. Drop properties and required items which are already provided by
common TLMM schema.
---
.../pinctrl/qcom,msm8953-pinctrl.yaml | 35 ++++---------------
1 file changed, 6 insertions(+), 29 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8953-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8953-pinctrl.yaml
index c162796ab604..a0e3c61fffe4 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8953-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8953-pinctrl.yaml
@@ -20,29 +20,13 @@ properties:
reg:
maxItems: 1
- interrupts:
- description: Specifies the TLMM summary IRQ
- maxItems: 1
-
+ interrupts: true
interrupt-controller: true
-
- '#interrupt-cells':
- description:
- Specifies the PIN numbers and Flags, as defined in defined in
- include/dt-bindings/interrupt-controller/irq.h
- const: 2
-
+ "#interrupt-cells": true
gpio-controller: true
-
gpio-reserved-ranges: true
-
- '#gpio-cells':
- description: Specifying the pin number and flags, as defined in
- include/dt-bindings/gpio/gpio.h
- const: 2
-
- gpio-ranges:
- maxItems: 1
+ "#gpio-cells": true
+ gpio-ranges: true
patternProperties:
"-state$":
@@ -59,7 +43,7 @@ $defs:
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
- $ref: "/schemas/pinctrl/pincfg-node.yaml"
+ $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
properties:
pins:
@@ -139,22 +123,15 @@ $defs:
required:
- pins
- - function
additionalProperties: false
allOf:
- - $ref: "pinctrl.yaml#"
+ - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
required:
- compatible
- reg
- - interrupts
- - interrupt-controller
- - '#interrupt-cells'
- - gpio-controller
- - '#gpio-cells'
- - gpio-ranges
additionalProperties: false
--
2.34.1
The TLMM pin controller follows generic pin-controller bindings, so
should have subnodes with '-state' and '-pins'. Otherwise the subnodes
(level one and two) are not properly matched. This method also unifies
the bindings with other Qualcomm TLMM and LPASS pinctrl bindings.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Bjorn Andersson <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
.../bindings/pinctrl/qcom,msm8226-pinctrl.yaml | 14 +++++++++++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml
index ab4a2b4cfda2..ecb90c77f666 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml
@@ -45,9 +45,17 @@ properties:
gpio-reserved-ranges:
maxItems: 1
-#PIN CONFIGURATION NODES
patternProperties:
- '-pins$':
+ "-state$":
+ oneOf:
+ - $ref: "#/$defs/qcom-msm8226-tlmm-state"
+ - patternProperties:
+ "-pins$":
+ $ref: "#/$defs/qcom-msm8226-tlmm-state"
+ additionalProperties: false
+
+$defs:
+ qcom-msm8226-tlmm-state:
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
@@ -126,7 +134,7 @@ examples:
#interrupt-cells = <2>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
- serial-pins {
+ serial-state {
pins = "gpio8", "gpio9";
function = "blsp_uart3";
drive-strength = <8>;
--
2.34.1
Bindings example should be indented with 4-spaces.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Bjorn Andersson <[email protected]>
Reviewed-by: Stephan Gerhold <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
.../bindings/pinctrl/qcom,msm8909-tlmm.yaml | 60 +++++++++----------
1 file changed, 30 insertions(+), 30 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8909-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8909-tlmm.yaml
index 08e2dd5cbebe..9c647e24fa9a 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8909-tlmm.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8909-tlmm.yaml
@@ -118,35 +118,35 @@ $defs:
examples:
- |
- #include <dt-bindings/interrupt-controller/arm-gic.h>
-
- pinctrl@1000000 {
- compatible = "qcom,msm8909-tlmm";
- reg = <0x1000000 0x300000>;
- interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&tlmm 0 0 117>;
- interrupt-controller;
- #interrupt-cells = <2>;
-
- gpio-wo-subnode-state {
- pins = "gpio1";
- function = "gpio";
- };
-
- uart-w-subnodes-state {
- rx-pins {
- pins = "gpio4";
- function = "blsp_uart1";
- bias-pull-up;
- };
-
- tx-pins {
- pins = "gpio5";
- function = "blsp_uart1";
- bias-disable;
- };
- };
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ pinctrl@1000000 {
+ compatible = "qcom,msm8909-tlmm";
+ reg = <0x1000000 0x300000>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&tlmm 0 0 117>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ gpio-wo-subnode-state {
+ pins = "gpio1";
+ function = "gpio";
};
+
+ uart-w-subnodes-state {
+ rx-pins {
+ pins = "gpio4";
+ function = "blsp_uart1";
+ bias-pull-up;
+ };
+
+ tx-pins {
+ pins = "gpio5";
+ function = "blsp_uart1";
+ bias-disable;
+ };
+ };
+ };
...
--
2.34.1
Bindings example should be indented with 4-spaces.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Bjorn Andersson <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
.../pinctrl/qcom,mdm9607-pinctrl.yaml | 22 +++++++++----------
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,mdm9607-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,mdm9607-pinctrl.yaml
index 57a4fed55de7..a37b358715a3 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,mdm9607-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,mdm9607-pinctrl.yaml
@@ -120,14 +120,14 @@ patternProperties:
examples:
- |
- #include <dt-bindings/interrupt-controller/arm-gic.h>
- tlmm: pinctrl@1000000 {
- compatible = "qcom,mdm9607-tlmm";
- reg = <0x01000000 0x300000>;
- interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- gpio-ranges = <&msmgpio 0 0 80>;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ tlmm: pinctrl@1000000 {
+ compatible = "qcom,mdm9607-tlmm";
+ reg = <0x01000000 0x300000>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ gpio-ranges = <&msmgpio 0 0 80>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
--
2.34.1
Bindings example should be indented with 4-spaces. Previous adjustment
missefd one spot.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Bjorn Andersson <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
.../devicetree/bindings/pinctrl/qcom,sc8280xp-pinctrl.yaml | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-pinctrl.yaml
index b9ab130cd558..0b251caaebf2 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-pinctrl.yaml
@@ -139,8 +139,8 @@ examples:
gpio-ranges = <&tlmm 0 0 230>;
gpio-wo-subnode-state {
- pins = "gpio1";
- function = "gpio";
+ pins = "gpio1";
+ function = "gpio";
};
uart-w-subnodes-state {
--
2.34.1
The TLMM pin controller follows generic pin-controller bindings, so
should have subnodes with '-state' and '-pins'. Otherwise the subnodes
(level one and two) are not properly matched. This method also unifies
the bindings with other Qualcomm TLMM and LPASS pinctrl bindings.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Bjorn Andersson <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
.../bindings/pinctrl/qcom,msm8953-pinctrl.yaml | 14 +++++++++++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8953-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8953-pinctrl.yaml
index d4da558cde54..c162796ab604 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8953-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8953-pinctrl.yaml
@@ -44,9 +44,17 @@ properties:
gpio-ranges:
maxItems: 1
-#PIN CONFIGURATION NODES
patternProperties:
- '-pins$':
+ "-state$":
+ oneOf:
+ - $ref: "#/$defs/qcom-msm8953-tlmm-state"
+ - patternProperties:
+ "-pins$":
+ $ref: "#/$defs/qcom-msm8953-tlmm-state"
+ additionalProperties: false
+
+$defs:
+ qcom-msm8953-tlmm-state:
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
@@ -163,7 +171,7 @@ examples:
#gpio-cells = <2>;
gpio-ranges = <&tlmm 0 0 142>;
- serial_default: serial-pins {
+ serial_default: serial-state {
pins = "gpio4", "gpio5";
function = "blsp_uart2";
drive-strength = <2>;
--
2.34.1
The TLMM pin controller follows generic pin-controller bindings, so
should have subnodes with '-state' and '-pins'. Otherwise the subnodes
(level one and two) are not properly matched. This method also unifies
the bindings with other Qualcomm TLMM and LPASS pinctrl bindings.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Bjorn Andersson <[email protected]>
Reviewed-by: Stephan Gerhold <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
.../devicetree/bindings/pinctrl/qcom,msm8909-tlmm.yaml | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8909-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8909-tlmm.yaml
index e03530091478..b1735918fa90 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8909-tlmm.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8909-tlmm.yaml
@@ -43,8 +43,9 @@ patternProperties:
oneOf:
- $ref: "#/$defs/qcom-msm8909-tlmm-state"
- patternProperties:
- ".*":
+ "-pins$":
$ref: "#/$defs/qcom-msm8909-tlmm-state"
+ additionalProperties: false
$defs:
qcom-msm8909-tlmm-state:
@@ -136,13 +137,13 @@ examples:
};
uart-w-subnodes-state {
- rx {
+ rx-pins {
pins = "gpio4";
function = "blsp_uart1";
bias-pull-up;
};
- tx {
+ tx-pins {
pins = "gpio5";
function = "blsp_uart1";
bias-disable;
--
2.34.1
Certain pins, like SDcard related, do not have functions and such should
not be required.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Bjorn Andersson <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
.../devicetree/bindings/pinctrl/qcom,mdm9607-pinctrl.yaml | 1 -
1 file changed, 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,mdm9607-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,mdm9607-pinctrl.yaml
index f7bd4be1739e..57a4fed55de7 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,mdm9607-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,mdm9607-pinctrl.yaml
@@ -115,7 +115,6 @@ patternProperties:
required:
- pins
- - function
additionalProperties: false
--
2.34.1
Reference common Qualcomm TLMM pin controller schema, to bring common
properties, other pinctrl schemas and additional checks, like function
required only for GPIOs.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Bjorn Andersson <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
Changes since v3:
1. Drop properties and required items which are already provided by
common TLMM schema.
---
.../pinctrl/qcom,qcm2290-pinctrl.yaml | 32 +++----------------
1 file changed, 5 insertions(+), 27 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,qcm2290-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,qcm2290-pinctrl.yaml
index 5324b61eb4f7..0d73abeea715 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,qcm2290-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,qcm2290-pinctrl.yaml
@@ -20,28 +20,12 @@ properties:
reg:
maxItems: 1
- interrupts:
- description: Specifies the TLMM summary IRQ
- maxItems: 1
-
+ interrupts: true
interrupt-controller: true
-
- '#interrupt-cells':
- description:
- Specifies the PIN numbers and Flags, as defined in defined in
- include/dt-bindings/interrupt-controller/irq.h
- const: 2
-
+ "#interrupt-cells": true
gpio-controller: true
-
- '#gpio-cells':
- description: Specifying the pin number and flags, as defined in
- include/dt-bindings/gpio/gpio.h
- const: 2
-
- gpio-ranges:
- maxItems: 1
-
+ "#gpio-cells": true
+ gpio-ranges: true
wakeup-parent: true
#PIN CONFIGURATION NODES
@@ -119,17 +103,11 @@ patternProperties:
additionalProperties: false
allOf:
- - $ref: "pinctrl.yaml#"
+ - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
required:
- compatible
- reg
- - interrupts
- - interrupt-controller
- - '#interrupt-cells'
- - gpio-controller
- - '#gpio-cells'
- - gpio-ranges
additionalProperties: false
--
2.34.1
Reference common Qualcomm TLMM pin controller schema, to bring common
properties, other pinctrl schemas and additional checks, like function
required only for GPIOs.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Bjorn Andersson <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
Changes since v3:
1. Drop properties and required items which are already provided by
common TLMM schema.
---
.../bindings/pinctrl/qcom,sdx55-pinctrl.yaml | 33 ++++---------------
1 file changed, 6 insertions(+), 27 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdx55-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sdx55-pinctrl.yaml
index fff57abf4fbc..e02590daf7bd 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,sdx55-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdx55-pinctrl.yaml
@@ -21,26 +21,12 @@ properties:
description: Specifies the base address and size of the TLMM register space
maxItems: 1
- interrupts:
- description: Specifies the TLMM summary IRQ
- maxItems: 1
-
+ interrupts: true
interrupt-controller: true
-
- '#interrupt-cells':
- description: Specifies the PIN numbers and Flags, as defined in
- include/dt-bindings/interrupt-controller/irq.h
- const: 2
-
+ "#interrupt-cells": true
gpio-controller: true
-
- '#gpio-cells':
- description: Specifying the pin number and flags, as defined in
- include/dt-bindings/gpio/gpio.h
- const: 2
-
- gpio-ranges:
- maxItems: 1
+ "#gpio-cells": true
+ gpio-ranges: true
gpio-reserved-ranges:
maxItems: 1
@@ -60,7 +46,7 @@ $defs:
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
- $ref: "/schemas/pinctrl/pincfg-node.yaml"
+ $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
properties:
pins:
@@ -122,22 +108,15 @@ $defs:
required:
- pins
- - function
additionalProperties: false
allOf:
- - $ref: "pinctrl.yaml#"
+ - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
required:
- compatible
- reg
- - interrupts
- - interrupt-controller
- - '#interrupt-cells'
- - gpio-controller
- - '#gpio-cells'
- - gpio-ranges
additionalProperties: false
--
2.34.1
Bindings example should be indented with 4-spaces.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Bjorn Andersson <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
.../bindings/pinctrl/qcom,sdx55-pinctrl.yaml | 34 +++++++++----------
1 file changed, 17 insertions(+), 17 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdx55-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sdx55-pinctrl.yaml
index e02590daf7bd..2d7097edfb40 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,sdx55-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdx55-pinctrl.yaml
@@ -122,23 +122,23 @@ additionalProperties: false
examples:
- |
- #include <dt-bindings/interrupt-controller/arm-gic.h>
- tlmm: pinctrl@1f00000 {
- compatible = "qcom,sdx55-pinctrl";
- reg = <0x0f100000 0x300000>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&tlmm 0 0 108>;
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
-
- serial-state {
- pins = "gpio8", "gpio9";
- function = "blsp_uart3";
- drive-strength = <8>;
- bias-disable;
- };
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ tlmm: pinctrl@1f00000 {
+ compatible = "qcom,sdx55-pinctrl";
+ reg = <0x0f100000 0x300000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&tlmm 0 0 108>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
+
+ serial-state {
+ pins = "gpio8", "gpio9";
+ function = "blsp_uart3";
+ drive-strength = <8>;
+ bias-disable;
};
+ };
...
--
2.34.1
The TLMM pin controller follows generic pin-controller bindings, so
should have subnodes with '-state' and '-pins'. Otherwise the subnodes
(level one and two) are not properly matched. This method also unifies
the bindings with other Qualcomm TLMM and LPASS pinctrl bindings.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Bjorn Andersson <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
.../bindings/pinctrl/qcom,qcm2290-pinctrl.yaml | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,qcm2290-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,qcm2290-pinctrl.yaml
index 3f4f1c0360b5..5324b61eb4f7 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,qcm2290-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,qcm2290-pinctrl.yaml
@@ -50,8 +50,9 @@ patternProperties:
oneOf:
- $ref: "#/$defs/qcom-qcm2290-tlmm-state"
- patternProperties:
- ".*":
+ "-pins$":
$ref: "#/$defs/qcom-qcm2290-tlmm-state"
+ additionalProperties: false
'$defs':
qcom-qcm2290-tlmm-state:
@@ -146,19 +147,19 @@ examples:
gpio-ranges = <&tlmm 0 0 127>;
sdc2_on_state: sdc2-on-state {
- clk {
+ clk-pins {
pins = "sdc2_clk";
bias-disable;
drive-strength = <16>;
};
- cmd {
+ cmd-pins {
pins = "sdc2_cmd";
bias-pull-up;
drive-strength = <10>;
};
- data {
+ data-pins {
pins = "sdc2_data";
bias-pull-up;
drive-strength = <10>;
--
2.34.1
The MSM8226 pinctrl driver supports input-enable, blsp_i2c4, blsp_uart4
and sdc3 functions and DTS already uses it:
qcom-msm8226-samsung-s3ve3g.dtb: pinctrl@fd510000: 'blsp1-i2c1', 'blsp1-i2c2', 'blsp1-i2c3', 'blsp1-i2c4', 'blsp1-i2c5' ...
qcom-apq8026-lg-lenok.dtb: pinctrl@fd510000: touch-state: 'oneOf' conditional failed, one must be fixed:
'input-enable' does not match any of the regexes: 'pinctrl-[0-9]+'
Signed-off-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Bjorn Andersson <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
.../bindings/pinctrl/qcom,msm8226-pinctrl.yaml | 10 ++++------
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml
index 158c9a50101e..c6f15c8da999 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml
@@ -65,9 +65,10 @@ $defs:
Specify the alternative function to be configured for the specified
pins. Functions are only valid for gpio pins.
enum: [ gpio, cci_i2c0, blsp_uim1, blsp_uim2, blsp_uim3, blsp_uim5,
- blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c5, blsp_spi1,
+ blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c4, blsp_i2c5, blsp_spi1,
blsp_spi2, blsp_spi3, blsp_spi5, blsp_uart1, blsp_uart2,
- blsp_uart3, blsp_uart5, cam_mclk0, cam_mclk1, wlan ]
+ blsp_uart3, blsp_uart4, blsp_uart5, cam_mclk0, cam_mclk1, sdc3,
+ wlan ]
drive-strength:
enum: [2, 4, 6, 8, 10, 12, 14, 16]
@@ -76,13 +77,10 @@ $defs:
Selects the drive strength for the specified pins, in mA.
bias-pull-down: true
-
bias-pull-up: true
-
bias-disable: true
-
+ input-enable: true
output-high: true
-
output-low: true
required:
--
2.34.1
Reference common Qualcomm TLMM pin controller schema, to bring common
properties, other pinctrl schemas and additional checks, like function
required only for GPIOs.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Bjorn Andersson <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
Changes since v3:
1. Drop properties and required items which are already provided by
common TLMM schema.
---
.../bindings/pinctrl/qcom,sdx65-pinctrl.yaml | 31 +++++--------------
1 file changed, 7 insertions(+), 24 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdx65-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sdx65-pinctrl.yaml
index 0f796f1f0104..ad1a2446a8af 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,sdx65-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdx65-pinctrl.yaml
@@ -20,25 +20,12 @@ properties:
reg:
maxItems: 1
- interrupts:
- maxItems: 1
-
+ interrupts: true
interrupt-controller: true
-
- '#interrupt-cells':
- description: Specifies the PIN numbers and Flags, as defined in
- include/dt-bindings/interrupt-controller/irq.h
- const: 2
-
+ "#interrupt-cells": true
gpio-controller: true
-
- '#gpio-cells':
- description: Specifying the pin number and flags, as defined in
- include/dt-bindings/gpio/gpio.h
- const: 2
-
- gpio-ranges:
- maxItems: 1
+ "#gpio-cells": true
+ gpio-ranges: true
gpio-reserved-ranges:
maxItems: 1
@@ -142,19 +129,15 @@ patternProperties:
required:
- pins
- - function
additionalProperties: false
+allOf:
+ - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
+
required:
- compatible
- reg
- - interrupts
- - interrupt-controller
- - '#interrupt-cells'
- - gpio-controller
- - '#gpio-cells'
- - gpio-ranges
additionalProperties: false
--
2.34.1
Certain pins, like SDcard related, do not have functions and such should
not be required. Add a check for this in common Qualcomm TLMM pin
controller schema.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Bjorn Andersson <[email protected]>
Reviewed-by: Stephan Gerhold <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
.../bindings/pinctrl/qcom,tlmm-common.yaml | 20 +++++++++++++++----
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml
index c88c8dcb69d9..e1354f0c64f8 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml
@@ -65,10 +65,6 @@ additionalProperties: true
$defs:
qcom-tlmm-state:
- allOf:
- - $ref: pincfg-node.yaml#
- - $ref: pinmux-node.yaml#
-
properties:
drive-strength:
enum: [2, 4, 6, 8, 10, 12, 14, 16]
@@ -82,5 +78,21 @@ $defs:
output-high: true
output-low: true
+ allOf:
+ - $ref: pincfg-node.yaml#
+ - $ref: pinmux-node.yaml#
+
+ - if:
+ properties:
+ pins:
+ items:
+ pattern: "^gpio"
+ then:
+ required:
+ - function
+ else:
+ properties:
+ function: false
+
additionalProperties: true
...
--
2.34.1
Bindings example should be indented with 4-spaces.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Bjorn Andersson <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
.../pinctrl/qcom,msm8953-pinctrl.yaml | 34 +++++++++----------
1 file changed, 17 insertions(+), 17 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8953-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8953-pinctrl.yaml
index a0e3c61fffe4..19d16cc9d749 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8953-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8953-pinctrl.yaml
@@ -137,21 +137,21 @@ additionalProperties: false
examples:
- |
- #include <dt-bindings/interrupt-controller/arm-gic.h>
- tlmm: pinctrl@1000000 {
- compatible = "qcom,msm8953-pinctrl";
- reg = <0x01000000 0x300000>;
- interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-controller;
- #interrupt-cells = <2>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&tlmm 0 0 142>;
-
- serial_default: serial-state {
- pins = "gpio4", "gpio5";
- function = "blsp_uart2";
- drive-strength = <2>;
- bias-disable;
- };
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ tlmm: pinctrl@1000000 {
+ compatible = "qcom,msm8953-pinctrl";
+ reg = <0x01000000 0x300000>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&tlmm 0 0 142>;
+
+ serial_default: serial-state {
+ pins = "gpio4", "gpio5";
+ function = "blsp_uart2";
+ drive-strength = <2>;
+ bias-disable;
};
+ };
--
2.34.1
Bindings example should be indented with 4-spaces.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Bjorn Andersson <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
.../pinctrl/qcom,msm8226-pinctrl.yaml | 36 +++++++++----------
1 file changed, 18 insertions(+), 18 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml
index c6f15c8da999..23868cdf4e03 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml
@@ -99,22 +99,22 @@ additionalProperties: false
examples:
- |
- #include <dt-bindings/interrupt-controller/arm-gic.h>
- msmgpio: pinctrl@fd510000 {
- compatible = "qcom,msm8226-pinctrl";
- reg = <0xfd510000 0x4000>;
-
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&msmgpio 0 0 117>;
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
-
- serial-state {
- pins = "gpio8", "gpio9";
- function = "blsp_uart3";
- drive-strength = <8>;
- bias-disable;
- };
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ msmgpio: pinctrl@fd510000 {
+ compatible = "qcom,msm8226-pinctrl";
+ reg = <0xfd510000 0x4000>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&msmgpio 0 0 117>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+
+ serial-state {
+ pins = "gpio8", "gpio9";
+ function = "blsp_uart3";
+ drive-strength = <8>;
+ bias-disable;
};
+ };
--
2.34.1
Certain pins, like SDcard related, do not have functions and such should
not be required.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Bjorn Andersson <[email protected]>
Reviewed-by: Stephan Gerhold <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
Documentation/devicetree/bindings/pinctrl/qcom,msm8909-tlmm.yaml | 1 -
1 file changed, 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8909-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8909-tlmm.yaml
index b1735918fa90..08e2dd5cbebe 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8909-tlmm.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8909-tlmm.yaml
@@ -113,7 +113,6 @@ $defs:
required:
- pins
- - function
additionalProperties: false
--
2.34.1
DT schema expects TLMM pin configuration nodes to be named with
'-state' suffix and their optional children with '-pins' suffix.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Bjorn Andersson <[email protected]>
Reviewed-by: Konrad Dybcio <[email protected]>
---
arch/arm/boot/dts/qcom-apq8026-lg-lenok.dts | 6 +++---
arch/arm/boot/dts/qcom-msm8226.dtsi | 24 ++++++++++-----------
2 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-apq8026-lg-lenok.dts b/arch/arm/boot/dts/qcom-apq8026-lg-lenok.dts
index 193569f0ca5f..02bef5870526 100644
--- a/arch/arm/boot/dts/qcom-apq8026-lg-lenok.dts
+++ b/arch/arm/boot/dts/qcom-apq8026-lg-lenok.dts
@@ -299,8 +299,8 @@ bluetooth_default_state: bluetooth-default-state {
input-enable;
};
- touch_pins: touch {
- irq {
+ touch_pins: touch-state {
+ irq-pins {
pins = "gpio17";
function = "gpio";
@@ -309,7 +309,7 @@ irq {
input-enable;
};
- reset {
+ reset-pins {
pins = "gpio16";
function = "gpio";
diff --git a/arch/arm/boot/dts/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom-msm8226.dtsi
index cf2d56929428..3b6e746a4af9 100644
--- a/arch/arm/boot/dts/qcom-msm8226.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8226.dtsi
@@ -354,35 +354,35 @@ tlmm: pinctrl@fd510000 {
#interrupt-cells = <2>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
- blsp1_i2c1_pins: blsp1-i2c1 {
+ blsp1_i2c1_pins: blsp1-i2c1-state {
pins = "gpio2", "gpio3";
function = "blsp_i2c1";
drive-strength = <2>;
bias-disable;
};
- blsp1_i2c2_pins: blsp1-i2c2 {
+ blsp1_i2c2_pins: blsp1-i2c2-state {
pins = "gpio6", "gpio7";
function = "blsp_i2c2";
drive-strength = <2>;
bias-disable;
};
- blsp1_i2c3_pins: blsp1-i2c3 {
+ blsp1_i2c3_pins: blsp1-i2c3-state {
pins = "gpio10", "gpio11";
function = "blsp_i2c3";
drive-strength = <2>;
bias-disable;
};
- blsp1_i2c4_pins: blsp1-i2c4 {
+ blsp1_i2c4_pins: blsp1-i2c4-state {
pins = "gpio14", "gpio15";
function = "blsp_i2c4";
drive-strength = <2>;
bias-disable;
};
- blsp1_i2c5_pins: blsp1-i2c5 {
+ blsp1_i2c5_pins: blsp1-i2c5-state {
pins = "gpio18", "gpio19";
function = "blsp_i2c5";
drive-strength = <2>;
@@ -390,13 +390,13 @@ blsp1_i2c5_pins: blsp1-i2c5 {
};
sdhc1_default_state: sdhc1-default-state {
- clk {
+ clk-pins {
pins = "sdc1_clk";
drive-strength = <10>;
bias-disable;
};
- cmd-data {
+ cmd-data-pins {
pins = "sdc1_cmd", "sdc1_data";
drive-strength = <10>;
bias-pull-up;
@@ -404,13 +404,13 @@ cmd-data {
};
sdhc2_default_state: sdhc2-default-state {
- clk {
+ clk-pins {
pins = "sdc2_clk";
drive-strength = <10>;
bias-disable;
};
- cmd-data {
+ cmd-data-pins {
pins = "sdc2_cmd", "sdc2_data";
drive-strength = <10>;
bias-pull-up;
@@ -418,21 +418,21 @@ cmd-data {
};
sdhc3_default_state: sdhc3-default-state {
- clk {
+ clk-pins {
pins = "gpio44";
function = "sdc3";
drive-strength = <8>;
bias-disable;
};
- cmd {
+ cmd-pins {
pins = "gpio43";
function = "sdc3";
drive-strength = <8>;
bias-pull-up;
};
- data {
+ data-pins {
pins = "gpio39", "gpio40", "gpio41", "gpio42";
function = "sdc3";
drive-strength = <8>;
--
2.34.1
Reference common Qualcomm TLMM pin controller schema, to bring common
properties, other pinctrl schemas and additional checks, like function
required only for GPIOs.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Bjorn Andersson <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
Changes since v3:
1. Drop properties and required items which are already provided by
common TLMM schema.
---
.../pinctrl/qcom,msm8226-pinctrl.yaml | 33 ++++---------------
1 file changed, 6 insertions(+), 27 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml
index ecb90c77f666..158c9a50101e 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml
@@ -21,26 +21,12 @@ properties:
description: Specifies the base address and size of the TLMM register space
maxItems: 1
- interrupts:
- description: Specifies the TLMM summary IRQ
- maxItems: 1
-
+ interrupts: true
interrupt-controller: true
-
- '#interrupt-cells':
- description: Specifies the PIN numbers and Flags, as defined in
- include/dt-bindings/interrupt-controller/irq.h
- const: 2
-
+ "#interrupt-cells": true
gpio-controller: true
-
- '#gpio-cells':
- description: Specifying the pin number and flags, as defined in
- include/dt-bindings/gpio/gpio.h
- const: 2
-
- gpio-ranges:
- maxItems: 1
+ "#gpio-cells": true
+ gpio-ranges: true
gpio-reserved-ranges:
maxItems: 1
@@ -60,7 +46,7 @@ $defs:
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
- $ref: "/schemas/pinctrl/pincfg-node.yaml"
+ $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
properties:
pins:
@@ -101,22 +87,15 @@ $defs:
required:
- pins
- - function
additionalProperties: false
allOf:
- - $ref: "pinctrl.yaml#"
+ - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
required:
- compatible
- reg
- - interrupts
- - interrupt-controller
- - '#interrupt-cells'
- - gpio-controller
- - '#gpio-cells'
- - gpio-ranges
additionalProperties: false
--
2.34.1
DT schema expects TLMM pin configuration nodes to be named with
'-state' suffix and their optional children with '-pins' suffix. Schema
also requires 'function' property, so two nodes for the same gpio (mux
and config) should be merged into one.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Bjorn Andersson <[email protected]>
Reviewed-by: Konrad Dybcio <[email protected]>
---
.../boot/dts/qcom-sdx55-telit-fn980-tlb.dts | 45 +++++++------------
1 file changed, 15 insertions(+), 30 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts b/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts
index a4fa468a095f..ac8b4626ae9a 100644
--- a/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts
+++ b/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts
@@ -282,40 +282,25 @@ &remoteproc_mpss {
};
&tlmm {
- pcie_ep_clkreq_default: pcie_ep_clkreq_default {
- mux {
- pins = "gpio56";
- function = "pcie_clkreq";
- };
- config {
- pins = "gpio56";
- drive-strength = <2>;
- bias-disable;
- };
+ pcie_ep_clkreq_default: pcie-ep-clkreq-default-state {
+ pins = "gpio56";
+ function = "pcie_clkreq";
+ drive-strength = <2>;
+ bias-disable;
};
- pcie_ep_perst_default: pcie_ep_perst_default {
- mux {
- pins = "gpio57";
- function = "gpio";
- };
- config {
- pins = "gpio57";
- drive-strength = <2>;
- bias-pull-down;
- };
+ pcie_ep_perst_default: pcie-ep-perst-default-state {
+ pins = "gpio57";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
};
- pcie_ep_wake_default: pcie_ep_wake_default {
- mux {
- pins = "gpio53";
- function = "gpio";
- };
- config {
- pins = "gpio53";
- drive-strength = <2>;
- bias-disable;
- };
+ pcie_ep_wake_default: pcie-ep-wake-default-state {
+ pins = "gpio53";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
};
};
--
2.34.1
The TLMM pin controller follows generic pin-controller bindings, so
should have subnodes with '-state' and '-pins'. Otherwise the subnodes
(level one and two) are not properly matched. This method also unifies
the bindings with other Qualcomm TLMM and LPASS pinctrl bindings.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Bjorn Andersson <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
.../devicetree/bindings/pinctrl/qcom,sdx65-pinctrl.yaml | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdx65-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sdx65-pinctrl.yaml
index cdfcf29dffee..0f796f1f0104 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,sdx65-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdx65-pinctrl.yaml
@@ -49,8 +49,10 @@ patternProperties:
oneOf:
- $ref: "#/$defs/qcom-sdx65-tlmm-state"
- patternProperties:
- ".*":
+ "-pins$":
$ref: "#/$defs/qcom-sdx65-tlmm-state"
+ additionalProperties: false
+
'$defs':
qcom-sdx65-tlmm-state:
type: object
@@ -175,13 +177,13 @@ examples:
};
uart-w-subnodes-state {
- rx {
+ rx-pins {
pins = "gpio4";
function = "blsp_uart1";
bias-pull-up;
};
- tx {
+ tx-pins {
pins = "gpio5";
function = "blsp_uart1";
bias-disable;
--
2.34.1
The TLMM pin controller follows generic pin-controller bindings, so
should have subnodes with '-state' and '-pins'. Otherwise the subnodes
(level one and two) are not properly matched.
qcom-sdx55-telit-fn980-tlb.dtb: pinctrl@f100000: 'pcie_ep_clkreq_default', 'pcie_ep_perst_default', 'pcie_ep_wake_default' do not match any of the regexes: '-pins$', 'pinctrl-[0-9]+'
This method also unifies the bindings with other Qualcomm TLMM and LPASS
pinctrl bindings.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Bjorn Andersson <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
.../bindings/pinctrl/qcom,sdx55-pinctrl.yaml | 14 +++++++++++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdx55-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sdx55-pinctrl.yaml
index a38090b14aab..fff57abf4fbc 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,sdx55-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdx55-pinctrl.yaml
@@ -45,9 +45,17 @@ properties:
gpio-reserved-ranges:
maxItems: 1
-#PIN CONFIGURATION NODES
patternProperties:
- '-pins$':
+ "-state$":
+ oneOf:
+ - $ref: "#/$defs/qcom-sdx55-tlmm-state"
+ - patternProperties:
+ "-pins$":
+ $ref: "#/$defs/qcom-sdx55-tlmm-state"
+ additionalProperties: false
+
+$defs:
+ qcom-sdx55-tlmm-state:
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
@@ -146,7 +154,7 @@ examples:
#interrupt-cells = <2>;
interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
- serial-pins {
+ serial-state {
pins = "gpio8", "gpio9";
function = "blsp_uart3";
drive-strength = <8>;
--
2.34.1
DT schema expects TLMM pin configuration nodes to be named with
'-state' suffix and their optional children with '-pins' suffix.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Bjorn Andersson <[email protected]>
Reviewed-by: Konrad Dybcio <[email protected]>
---
arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 4 ++--
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
index 6a716c83e5f1..ec999f972360 100644
--- a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
+++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
@@ -51,13 +51,13 @@ flash@0 {
};
&tlmm {
- i2c_1_pins: i2c-1-pins {
+ i2c_1_pins: i2c-1-state {
pins = "gpio42", "gpio43";
function = "blsp2_i2c";
drive-strength = <8>;
};
- spi_0_pins: spi-0-pins {
+ spi_0_pins: spi-0-state {
pins = "gpio38", "gpio39", "gpio40", "gpio41";
function = "blsp0_spi";
drive-strength = <8>;
diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
index a7c7ca980a71..9b9f778090e1 100644
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -218,14 +218,14 @@ tlmm: pinctrl@1000000 {
interrupt-controller;
#interrupt-cells = <2>;
- serial_3_pins: serial3-pinmux {
+ serial_3_pins: serial3-state {
pins = "gpio44", "gpio45";
function = "blsp2_uart";
drive-strength = <8>;
bias-pull-down;
};
- qpic_pins: qpic-pins {
+ qpic_pins: qpic-state {
pins = "gpio1", "gpio3", "gpio4",
"gpio5", "gpio6", "gpio7",
"gpio8", "gpio10", "gpio11",
--
2.34.1
The TLMM pin controller follows generic pin-controller bindings, so
should have subnodes with '-state' and '-pins'. Otherwise the subnodes
(level one and two) are not properly matched. This method also unifies
the bindings with other Qualcomm TLMM and LPASS pinctrl bindings.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Bjorn Andersson <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
.../bindings/pinctrl/qcom,sc7280-pinctrl.yaml | 14 +++++++++++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-pinctrl.yaml
index ad3496784678..4606ca980dc4 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-pinctrl.yaml
@@ -47,9 +47,17 @@ properties:
wakeup-parent: true
-#PIN CONFIGURATION NODES
patternProperties:
- '-pins$':
+ "-state$":
+ oneOf:
+ - $ref: "#/$defs/qcom-sc7280-tlmm-state"
+ - patternProperties:
+ "-pins$":
+ $ref: "#/$defs/qcom-sc7280-tlmm-state"
+ additionalProperties: false
+
+$defs:
+ qcom-sc7280-tlmm-state:
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
@@ -162,7 +170,7 @@ examples:
gpio-ranges = <&tlmm 0 0 175>;
wakeup-parent = <&pdc>;
- qup_uart5_default: qup-uart5-pins {
+ qup_uart5_default: qup-uart5-state {
pins = "gpio46", "gpio47";
function = "qup13";
drive-strength = <2>;
--
2.34.1
On Thu, 6 Oct 2022 14:46:25 +0200, Krzysztof Kozlowski wrote:
> Changes since v3
> ================
> 1. All patches with subject: "use common TLMM schema":
> Drop properties and required items which are already provided by common TLMM
> schema.
> The change against v3 is non-trivial, however I retained reviewed-by tags.
> 2. Add Rb tags.
>
> [...]
Applied, thanks!
[03/34] ARM: dts: qcom: sdx55: add gpio-ranges to TLMM pinctrl
commit: 0139f183bcddcf5b36f805254bb0f0625963f783
[04/34] ARM: dts: qcom: sdx55: align TLMM pin configuration with DT schema
commit: bda79af488a3e75769433fb961800c39bb07b29c
[05/34] ARM: dts: qcom: msm8226: align TLMM pin configuration with DT schema
commit: df9c86025510c45a6d90669347129e8000e1bbbc
[06/34] ARM: dts: qcom: msm8974: align TLMM pin configuration with DT schema
commit: 6cd72414abc7345e277fcab5e1c763c3a017dc6a
Best regards,
--
Bjorn Andersson <[email protected]>