2022-10-06 23:05:26

by Jim Quinlan

Subject: [PATCH v1 0/5] PCI: brcmstb: Add Multi-MSI and some improvements

One commit brings Multi-MSI functionality to the Broadcom STB PCIe.
The other four commits are unrelated minor improvements.

Jim Quinlan (5):
PCI: brcmstb: Enable Multi-MSI
PCI: brcmstb: Wait for 100ms following PERST# deassert
PCI: brcmstb: Replace status loops with read_poll_timeout_atomic()
PCI: brcmstb: Functions needlessly specified as "inline"
PCI: brcmstb: Set RCB_{MPS,64B}_MODE bits

drivers/pci/controller/pcie-brcmstb.c | 85 +++++++++++++++------------
1 file changed, 48 insertions(+), 37 deletions(-)


base-commit: 833477fce7a14d43ae4c07f8ddc32fa5119471a2
--
2.17.1

2022-10-06 23:07:54

by Jim Quinlan

Subject: [PATCH v1 5/5] PCI: brcmstb: Set RCB_{MPS,64B}_MODE bits

Set RCB_MPS mode bit so that data for PCIe read requests up to the size of
the Maximum Payload Size (MPS) are returned in one completion, and data for
PCIe read requests greater than the MPS are split at the specified Read
Completion Boundary setting.

Set RCB_64B so that read compeletion boudnary is 64B.

Signed-off-by: Jim Quinlan <[email protected]>
---
drivers/pci/controller/pcie-brcmstb.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
index e3045f1eadbc..edf283e2b5dd 100644
--- a/drivers/pci/controller/pcie-brcmstb.c
+++ b/drivers/pci/controller/pcie-brcmstb.c
@@ -53,6 +53,8 @@
#define PCIE_RC_DL_MDIO_RD_DATA 0x1108

#define PCIE_MISC_MISC_CTRL 0x4008
+#define PCIE_MISC_MISC_CTRL_PCIE_RCB_64B_MODE_MASK 0x80
+#define PCIE_MISC_MISC_CTRL_PCIE_RCB_MPS_MODE_MASK 0x400
#define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000
#define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000
#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000
@@ -900,11 +902,16 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
else
burst = 0x2; /* 512 bytes */

- /* Set SCB_MAX_BURST_SIZE, CFG_READ_UR_MODE, SCB_ACCESS_EN */
+ /*
+ * Set SCB_MAX_BURST_SIZE, CFG_READ_UR_MODE, SCB_ACCESS_EN,
+ * RCB_MPS_MODE, RCB_64B_MODE
+ */
tmp = readl(base + PCIE_MISC_MISC_CTRL);
u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK);
u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK);
u32p_replace_bits(&tmp, burst, PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK);
+ u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_PCIE_RCB_MPS_MODE_MASK);
+ u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_PCIE_RCB_64B_MODE_MASK);
writel(tmp, base + PCIE_MISC_MISC_CTRL);

ret = brcm_pcie_get_rc_bar2_size_and_offset(pcie, &rc_bar2_size,
--
2.17.1

2022-10-07 20:08:31

by Bjorn Helgaas

Subject: Re: [PATCH v1 5/5] PCI: brcmstb: Set RCB_{MPS,64B}_MODE bits

On Thu, Oct 06, 2022 at 06:03:21PM -0400, Jim Quinlan wrote:
> Set RCB_MPS mode bit so that data for PCIe read requests up to the size of
> the Maximum Payload Size (MPS) are returned in one completion,

> and data for
> PCIe read requests greater than the MPS are split at the specified Read
> Completion Boundary setting.

I think this second part is required by PCIe r6.0, sec 2.3.1.1,
regardless of the setting of RCB_MPS, isn't it?

> Set RCB_64B so that read compeletion boudnary is 64B.

To match usage in spec and above and fix typos,

s/that read compeletion boudnary/the Read Completion Boundary/

Bjorn