2022-10-09 23:53:14

by Lad, Prabhakar

[permalink] [raw]
Subject: [PATCH] clk: renesas: r9a07g044: Drop WDT2 clock and reset entry

From: Lad Prabhakar <[email protected]>

WDT CH2 is specifically to check the operation of Cortex-M33 CPU and if
used from CA55 CPU would result in an unexpected behaviour. Hence drop
WDT2 clock and reset entries.

Signed-off-by: Lad Prabhakar <[email protected]>
---
Note, this patch applies on top of [0].

[0] https://patchwork.kernel.org/project/linux-renesas-soc/patch/[email protected]/
---
drivers/clk/renesas/r9a07g044-cpg.c | 7 +------
1 file changed, 1 insertion(+), 6 deletions(-)

diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index 12b1a83625cb..f5550fccb029 100644
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -182,7 +182,7 @@ static const struct {
};

static const struct {
- struct rzg2l_mod_clk common[77];
+ struct rzg2l_mod_clk common[75];
#ifdef CONFIG_CLK_R9A07G054
struct rzg2l_mod_clk drp[0];
#endif
@@ -224,10 +224,6 @@ static const struct {
0x548, 2),
DEF_MOD("wdt1_clk", R9A07G044_WDT1_CLK, R9A07G044_OSCCLK,
0x548, 3),
- DEF_MOD("wdt2_pclk", R9A07G044_WDT2_PCLK, R9A07G044_CLK_P0,
- 0x548, 4),
- DEF_MOD("wdt2_clk", R9A07G044_WDT2_CLK, R9A07G044_OSCCLK,
- 0x548, 5),
DEF_MOD("spi_clk2", R9A07G044_SPI_CLK2, R9A07G044_CLK_SPI1,
0x550, 0),
DEF_MOD("spi_clk", R9A07G044_SPI_CLK, R9A07G044_CLK_SPI0,
@@ -366,7 +362,6 @@ static struct rzg2l_reset r9a07g044_resets[] = {
DEF_RST(R9A07G044_POEG_D_RST, 0x844, 3),
DEF_RST(R9A07G044_WDT0_PRESETN, 0x848, 0),
DEF_RST(R9A07G044_WDT1_PRESETN, 0x848, 1),
- DEF_RST(R9A07G044_WDT2_PRESETN, 0x848, 2),
DEF_RST(R9A07G044_SPI_RST, 0x850, 0),
DEF_RST(R9A07G044_SDHI0_IXRST, 0x854, 0),
DEF_RST(R9A07G044_SDHI1_IXRST, 0x854, 1),
--
2.25.1


2022-10-10 07:06:00

by Wolfram Sang

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Subject: Re: [PATCH] clk: renesas: r9a07g044: Drop WDT2 clock and reset entry

On Mon, Oct 10, 2022 at 12:10:13AM +0100, Prabhakar wrote:
> From: Lad Prabhakar <[email protected]>
>
> WDT CH2 is specifically to check the operation of Cortex-M33 CPU and if
> used from CA55 CPU would result in an unexpected behaviour. Hence drop
> WDT2 clock and reset entries.
>
> Signed-off-by: Lad Prabhakar <[email protected]>

Reviewed-by: Wolfram Sang <[email protected]>


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2022-10-11 08:51:51

by Geert Uytterhoeven

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Subject: Re: [PATCH] clk: renesas: r9a07g044: Drop WDT2 clock and reset entry

On Mon, Oct 10, 2022 at 1:10 AM Prabhakar <[email protected]> wrote:
> From: Lad Prabhakar <[email protected]>
>
> WDT CH2 is specifically to check the operation of Cortex-M33 CPU and if
> used from CA55 CPU would result in an unexpected behaviour. Hence drop
> WDT2 clock and reset entries.
>
> Signed-off-by: Lad Prabhakar <[email protected]>

Reviewed-by: Geert Uytterhoeven <[email protected]>
i.e. will queue in renesas-clk-for-v6.2.

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds