With reference to FSD SoC HW UM, there are some deviations in the
drive strength macros names and macro values. Also the IPs are not
using the default drive strength values as recommended by HW UM.
FSD SoC pinctrl has following four levels of drive-strength and their
corresponding values:
Level-1 <-> 0
Level-2 <-> 1
Level-4 <-> 2
Level-6 <-> 3
The commit 684dac402f21 ("arm64: dts: fsd: Add initial pinctrl support")
used drive strength macros defined for Exynos4 SoC family. For some IPs
the macros values of Exynos4 matched and worked well, but Exynos4 SoC
family drive-strength (names and values) is not exactly matching with
FSD SoC.
The intention of this patch series is to:
1. Fix the drive strength macros to reflect actual names and values given
in FSD HW UM.
2. Ensure that the existing peripherals in device tree file is using
default drive strength values recommended in FSD HW UM.
Padmanabhan Rajanbabu (4):
arm64: dts: fix drive strength macros as per FSD HW UM
arm64: dts: fix HSI2C drive strength values as per FSD HW UM
arm64: dts: fix UART drive strength values as per FSD HW UM
arm64: dts: fix SPI drive strength values as per FSD HW UM
arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi | 34 +++++++++++-----------
arch/arm64/boot/dts/tesla/fsd-pinctrl.h | 6 ++--
2 files changed, 20 insertions(+), 20 deletions(-)
--
2.17.1
On 13/10/2022 06:40, Padmanabhan Rajanbabu wrote:
> Padmanabhan Rajanbabu (4):
> arm64: dts: fix drive strength macros as per FSD HW UM
> arm64: dts: fix HSI2C drive strength values as per FSD HW UM
> arm64: dts: fix UART drive strength values as per FSD HW UM
> arm64: dts: fix SPI drive strength values as per FSD HW UM
>
Use subject prefixes matching the subsystem (git log --oneline -- ...).
>
Best regards,
Krzysztof
On Thu, 13 Oct 2022 16:10:20 +0530, Padmanabhan Rajanbabu wrote:
> With reference to FSD SoC HW UM, there are some deviations in the
> drive strength macros names and macro values. Also the IPs are not
> using the default drive strength values as recommended by HW UM.
>
> FSD SoC pinctrl has following four levels of drive-strength and their
> corresponding values:
> Level-1 <-> 0
> Level-2 <-> 1
> Level-4 <-> 2
> Level-6 <-> 3
>
> [...]
Applied, thanks!
[1/4] arm64: dts: fix drive strength macros as per FSD HW UM
https://git.kernel.org/krzk/linux/c/3a27bce7e13e3b5368377c9a518927e197a4afb1
[2/4] arm64: dts: fix HSI2C drive strength values as per FSD HW UM
https://git.kernel.org/krzk/linux/c/bb997d949e5a835f626facfd67b1768fd4492398
[3/4] arm64: dts: fix UART drive strength values as per FSD HW UM
https://git.kernel.org/krzk/linux/c/8aa0323c14d546a14cb1d39e38673bda20699f7e
[4/4] arm64: dts: fix SPI drive strength values as per FSD HW UM
https://git.kernel.org/krzk/linux/c/54e628d4fb24f54d70aa423da485bf5f5ab7260b
Best regards,
--
Krzysztof Kozlowski <[email protected]>
On 18/10/2022 09:21, Krzysztof Kozlowski wrote:
> On Thu, 13 Oct 2022 16:10:20 +0530, Padmanabhan Rajanbabu wrote:
>> With reference to FSD SoC HW UM, there are some deviations in the
>> drive strength macros names and macro values. Also the IPs are not
>> using the default drive strength values as recommended by HW UM.
>>
>> FSD SoC pinctrl has following four levels of drive-strength and their
>> corresponding values:
>> Level-1 <-> 0
>> Level-2 <-> 1
>> Level-4 <-> 2
>> Level-6 <-> 3
>>
>> [...]
>
> Applied, thanks!
>
> [1/4] arm64: dts: fix drive strength macros as per FSD HW UM
> https://git.kernel.org/krzk/linux/c/3a27bce7e13e3b5368377c9a518927e197a4afb1
> [2/4] arm64: dts: fix HSI2C drive strength values as per FSD HW UM
> https://git.kernel.org/krzk/linux/c/bb997d949e5a835f626facfd67b1768fd4492398
Fixed subject and squashed last two commits into this one.
Best regards,
Krzysztof