Hi,
This is the v12 series to introduce i.MX8qm/qxp Display Processing Unit(DPU)
DRM support.
DPU is comprised of a blit engine for 2D graphics, a display controller
and a command sequencer. Outside of DPU, optional prefetch engines can
fetch data from memory prior to some DPU fetchunits of blit engine and
display controller. The pre-fetchers support linear formats and Vivante
GPU tile formats.
Reference manual can be found at:
https://www.nxp.com/webapp/Download?colCode=IMX8DQXPRM
This patch set adds kernel modesetting support for the display controller part.
It supports two CRTCs per display controller, several planes, prefetch
engines and some properties of CRTC and plane. Currently, the registers of
the controller is accessed without command sequencer involved, instead just by
using CPU. DRM connectors would be created from the DPU KMS driver.
Patch 1 ~ 3 add dt-bindings for DPU and prefetch engines.
Patch 4 is a minor improvement of a macro to suppress warning as the KMS driver
uses it.
Patch 5 introduces the DPU DRM support.
Patch 6 updates MAINTAINERS.
Welcome comments, thanks.
v11->v12:
* Rebase the series upon v6.1-rc1.
* Minor update on Kconfigs, struct names and macro names for patch 5/6
due to the rebase.
v10->v11:
* Rebase the series upon v6.0-rc1.
* Include drm_blend.h and drm_framebuffer.h in dpu-kms.c and dpu-plane.c
to fix build errors due to the rebase.
* Fix a checkpatch warning for dpu-crtc.c.
* Properly use dev_err_probe() to return it's return value directly where
possible.
v9->v10:
* Rebase the series upon v5.18-rc1.
* Make 'checkpatch.pl --strict' happier for patch 5/6.
* Add Rob's R-b tag on patch 3/6.
* Add Laurentiu's R-b tag on patch 5/6.
* Add Laurentiu's A-b tag on patch 6/6.
v8->v9:
* Use drm_atomic_get_new_plane_state() in dpu_plane_atomic_update() for
patch 5/6. (Laurentiu)
* Drop getting DPU DT alias ID for patch 5/6, as it is unused.
* Reference 'interrupts-extended' schema instead of 'interrupts' for patch 3/6
to require an additional DPR interrupt(r_rtram_stall) because the reference
manual does mention it, though the driver doesn't get/use it for now.
Reference 'interrupt-names' schema to define the two DPR interrupt names -
'dpr_wrap' and 'r_rtram_stall'. Accordingly, patch 5/6 gets the 'dpr_wrap'
interrupt by name.
* Drop Rob's R-b tag on patch 3/6, as review is needed.
v7->v8:
* Rebase this series up onto the latest drm-misc-next branch, due to DRM plane
helper functions API change(atomic_check and atomic_update) from DRM atomic
core. So, dpu_plane_atomic_check() and dpu_plane_atomic_update() are updated
accordingly in patch 5/6. Also, rename plane->state variables and relevant
DPU plane state variables in those two functions to reflect they are new
states, like the patch 'drm: Rename plane->state variables in atomic update
and disable' recently landed in drm-misc-next.
* Replace drm_gem_fb_prepare_fb() with drm_gem_plane_helper_prepare_fb() in
patch 5/6, due to DRM core API change.
* Improve DPR burst length for GPU standard tile and 32bpp GPU super tile in
patch 5/6 to align with the latest version of internal HW documention.
v6->v7:
* Fix return value of dpu_get_irqs() if platform_get_irq() fails. (Laurentiu)
* Use the function array dpu_irq_handler[] to store individual DPU irq handlers.
(Laurentiu)
* Call get/put() hooks directly to get/put DPU fetchunits for DPU plane groups.
(Laurentiu)
* Shorten the names of individual DPU irq handlers by using DPU unit abbrev
names to make writing dpu_irq_handler[] easier.
* Add Rob's R-b tag back on DPU dt-binding patch as change in v6 was reviewed.
v5->v6:
* Use graph schema in the DPU dt-binding.
* Do not use macros where possible in the DPU DRM driver. (Laurentiu)
* Break dpu_plane_atomic_check() into some smaller functions. (Laurentiu)
* Address some minor comments from Laurentiu on the DPU DRM driver.
* Add dpu_crtc_err() helper marco in the DPU DRM driver to tell dmesg
which CRTC generates error.
* Drop calling dev_set_drvdata() from dpu_drm_bind/unbind() in the DPU DRM
driver as it is done in dpu_drm_probe().
* Some trivial tweaks.
v4->v5:
* Rebase up onto the latest drm-misc-next branch and remove the hook to
drm_atomic_helper_legacy_gamma_set() from patch 5/6, because it was dropped
by the newly landed commit 'drm: automatic legacy gamma support'.
* Remove a redundant blank line from dpu_plane_atomic_update() in patch 5/6.
v3->v4:
* Improve compatible properties in DPU and prefetch engines' dt bindings
by using enum instead of oneOf+const.
* Add Rob's R-b tags on dt binding patches(patch 1/6, 2/6 and 3/6).
* Add Daniel's A-b tag on patch 4/6.
v2->v3:
* Fix DPU DRM driver build warnings which are
Reported-by: kernel test robot <[email protected]>.
* Drop DPU DRM driver build dependency on IMX_SCU, as dummy SCU functions have
been added in header files by the patch 'firmware: imx: add dummy functions'
which has landed in linux-next/master branch.
* Add a missing blank line in include/drm/drm_atomic.h.
v1->v2:
* Test this patch set also with i.MX8qm LVDS displays.
* Drop the device tree patches because we'll use new dt binding way to
support i.MX8qm/qxp clocks. This depends on a not-yet-landed patch set
to do basic conversions for the platforms.
* Fix dt binding yamllint warnings.
* Require bypass0 and bypass1 clocks for both i.MX8qxp and i.MX8qm in DPU's
dt binding documentation.
* Use new dt binding way to add clocks in the dt binding examples.
* Address several comments from Laurentiu on the DPU DRM patch.
Liu Ying (6):
dt-bindings: display: imx: Add i.MX8qxp/qm DPU binding
dt-bindings: display: imx: Add i.MX8qxp/qm PRG binding
dt-bindings: display: imx: Add i.MX8qxp/qm DPR channel binding
drm/atomic: Avoid unused-but-set-variable warning on
for_each_old_plane_in_state
drm/imx: Introduce i.MX8qm/qxp DPU DRM
MAINTAINERS: add maintainer for i.MX8qxp DPU DRM driver
.../display/imx/fsl,imx8qxp-dprc.yaml | 100 ++
.../bindings/display/imx/fsl,imx8qxp-dpu.yaml | 387 ++++++
.../bindings/display/imx/fsl,imx8qxp-prg.yaml | 60 +
MAINTAINERS | 9 +
drivers/gpu/drm/imx/Kconfig | 1 +
drivers/gpu/drm/imx/Makefile | 1 +
drivers/gpu/drm/imx/dpu/Kconfig | 9 +
drivers/gpu/drm/imx/dpu/Makefile | 10 +
drivers/gpu/drm/imx/dpu/dpu-constframe.c | 171 +++
drivers/gpu/drm/imx/dpu/dpu-core.c | 1044 +++++++++++++++++
drivers/gpu/drm/imx/dpu/dpu-crtc.c | 969 +++++++++++++++
drivers/gpu/drm/imx/dpu/dpu-crtc.h | 72 ++
drivers/gpu/drm/imx/dpu/dpu-disengcfg.c | 117 ++
drivers/gpu/drm/imx/dpu/dpu-dprc.c | 715 +++++++++++
drivers/gpu/drm/imx/dpu/dpu-dprc.h | 40 +
drivers/gpu/drm/imx/dpu/dpu-drv.c | 292 +++++
drivers/gpu/drm/imx/dpu/dpu-drv.h | 28 +
drivers/gpu/drm/imx/dpu/dpu-extdst.c | 299 +++++
drivers/gpu/drm/imx/dpu/dpu-fetchdecode.c | 292 +++++
drivers/gpu/drm/imx/dpu/dpu-fetcheco.c | 224 ++++
drivers/gpu/drm/imx/dpu/dpu-fetchlayer.c | 152 +++
drivers/gpu/drm/imx/dpu/dpu-fetchunit.c | 610 ++++++++++
drivers/gpu/drm/imx/dpu/dpu-fetchunit.h | 195 +++
drivers/gpu/drm/imx/dpu/dpu-fetchwarp.c | 248 ++++
drivers/gpu/drm/imx/dpu/dpu-framegen.c | 395 +++++++
drivers/gpu/drm/imx/dpu/dpu-gammacor.c | 223 ++++
drivers/gpu/drm/imx/dpu/dpu-hscaler.c | 275 +++++
drivers/gpu/drm/imx/dpu/dpu-kms.c | 542 +++++++++
drivers/gpu/drm/imx/dpu/dpu-kms.h | 23 +
drivers/gpu/drm/imx/dpu/dpu-layerblend.c | 348 ++++++
drivers/gpu/drm/imx/dpu/dpu-plane.c | 804 +++++++++++++
drivers/gpu/drm/imx/dpu/dpu-plane.h | 59 +
drivers/gpu/drm/imx/dpu/dpu-prg.c | 433 +++++++
drivers/gpu/drm/imx/dpu/dpu-prg.h | 45 +
drivers/gpu/drm/imx/dpu/dpu-prv.h | 231 ++++
drivers/gpu/drm/imx/dpu/dpu-tcon.c | 250 ++++
drivers/gpu/drm/imx/dpu/dpu-vscaler.c | 308 +++++
drivers/gpu/drm/imx/dpu/dpu.h | 385 ++++++
include/drm/drm_atomic.h | 5 +-
39 files changed, 10370 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dprc.yaml
create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dpu.yaml
create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-prg.yaml
create mode 100644 drivers/gpu/drm/imx/dpu/Kconfig
create mode 100644 drivers/gpu/drm/imx/dpu/Makefile
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-constframe.c
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-core.c
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-crtc.c
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-crtc.h
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-disengcfg.c
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-dprc.c
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-dprc.h
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-drv.c
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-drv.h
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-extdst.c
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-fetchdecode.c
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-fetcheco.c
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-fetchlayer.c
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-fetchunit.c
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-fetchunit.h
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-fetchwarp.c
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-framegen.c
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-gammacor.c
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-hscaler.c
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-kms.c
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-kms.h
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-layerblend.c
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-plane.c
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-plane.h
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-prg.c
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-prg.h
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-prv.h
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-tcon.c
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-vscaler.c
create mode 100644 drivers/gpu/drm/imx/dpu/dpu.h
--
2.37.1
Add myself as the maintainer of the i.MX8qxp DPU DRM driver.
Acked-by: Laurentiu Palcu <[email protected]>
Signed-off-by: Liu Ying <[email protected]>
---
v11->v12:
* No change.
v10->v11:
* Rebase upon v6.0-rc1.
v9->v10:
* Add Laurentiu's A-b tag.
v1->v9:
* No change.
MAINTAINERS | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index cf0f18502372..a882de9ed4cb 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6902,6 +6902,15 @@ F: Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml
F: Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pxl2dpi.yaml
F: drivers/gpu/drm/bridge/imx/
+DRM DRIVERS FOR FREESCALE i.MX8QXP
+M: Liu Ying <[email protected]>
+L: [email protected]
+S: Maintained
+F: Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dprc.yaml
+F: Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dpu.yaml
+F: Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-prg.yaml
+F: drivers/gpu/drm/imx/dpu/
+
DRM DRIVERS FOR GMA500 (Poulsbo, Moorestown and derivative chipsets)
M: Patrik Jakobsson <[email protected]>
L: [email protected]
--
2.37.1
This patch adds bindings for i.MX8qxp/qm Display Processing Unit.
Reviewed-by: Rob Herring <[email protected]>
Signed-off-by: Liu Ying <[email protected]>
---
v7->v12:
* No change.
v6->v7:
* Add Rob's R-b tag back.
v5->v6:
* Use graph schema. So, drop Rob's R-b tag as review is needed.
v4->v5:
* No change.
v3->v4:
* Improve compatible property by using enum instead of oneOf+const. (Rob)
* Add Rob's R-b tag.
v2->v3:
* No change.
v1->v2:
* Fix yamllint warnings.
* Require bypass0 and bypass1 clocks for both i.MX8qxp and i.MX8qm, as the
display controller subsystem spec does say that they exist.
* Use new dt binding way to add clocks in the example.
* Trivial tweaks for the example.
.../bindings/display/imx/fsl,imx8qxp-dpu.yaml | 387 ++++++++++++++++++
1 file changed, 387 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dpu.yaml
diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dpu.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dpu.yaml
new file mode 100644
index 000000000000..6b05c586cd9d
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dpu.yaml
@@ -0,0 +1,387 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dpu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8qm/qxp Display Processing Unit
+
+maintainers:
+ - Liu Ying <[email protected]>
+
+description: |
+ The Freescale i.MX8qm/qxp Display Processing Unit(DPU) is comprised of two
+ main components that include a blit engine for 2D graphics accelerations
+ and a display controller for display output processing, as well as a command
+ sequencer.
+
+properties:
+ compatible:
+ enum:
+ - fsl,imx8qxp-dpu
+ - fsl,imx8qm-dpu
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ items:
+ - description: |
+ store9 shadow load interrupt(blit engine)
+ - description: |
+ store9 frame complete interrupt(blit engine)
+ - description: |
+ store9 sequence complete interrupt(blit engine)
+ - description: |
+ extdst0 shadow load interrupt
+ (display controller, content stream 0)
+ - description: |
+ extdst0 frame complete interrupt
+ (display controller, content stream 0)
+ - description: |
+ extdst0 sequence complete interrupt
+ (display controller, content stream 0)
+ - description: |
+ extdst4 shadow load interrupt
+ (display controller, safety stream 0)
+ - description: |
+ extdst4 frame complete interrupt
+ (display controller, safety stream 0)
+ - description: |
+ extdst4 sequence complete interrupt
+ (display controller, safety stream 0)
+ - description: |
+ extdst1 shadow load interrupt
+ (display controller, content stream 1)
+ - description: |
+ extdst1 frame complete interrupt
+ (display controller, content stream 1)
+ - description: |
+ extdst1 sequence complete interrupt
+ (display controller, content stream 1)
+ - description: |
+ extdst5 shadow load interrupt
+ (display controller, safety stream 1)
+ - description: |
+ extdst5 frame complete interrupt
+ (display controller, safety stream 1)
+ - description: |
+ extdst5 sequence complete interrupt
+ (display controller, safety stream 1)
+ - description: |
+ disengcfg0 shadow load interrupt
+ (display controller, display stream 0)
+ - description: |
+ disengcfg0 frame complete interrupt
+ (display controller, display stream 0)
+ - description: |
+ disengcfg0 sequence complete interrupt
+ (display controller, display stream 0)
+ - description: |
+ framegen0 programmable interrupt0
+ (display controller, display stream 0)
+ - description: |
+ framegen0 programmable interrupt1
+ (display controller, display stream 0)
+ - description: |
+ framegen0 programmable interrupt2
+ (display controller, display stream 0)
+ - description: |
+ framegen0 programmable interrupt3
+ (display controller, display stream 0)
+ - description: |
+ signature0 shadow load interrupt
+ (display controller, display stream 0)
+ - description: |
+ signature0 measurement valid interrupt
+ (display controller, display stream 0)
+ - description: |
+ signature0 error condition interrupt
+ (display controller, display stream 0)
+ - description: |
+ disengcfg1 shadow load interrupt
+ (display controller, display stream 1)
+ - description: |
+ disengcfg1 frame complete interrupt
+ (display controller, display stream 1)
+ - description: |
+ disengcfg1 sequence complete interrupt
+ (display controller, display stream 1)
+ - description: |
+ framegen1 programmable interrupt0
+ (display controller, display stream 1)
+ - description: |
+ framegen1 programmable interrupt1
+ (display controller, display stream 1)
+ - description: |
+ framegen1 programmable interrupt2
+ (display controller, display stream 1)
+ - description: |
+ framegen1 programmable interrupt3
+ (display controller, display stream 1)
+ - description: |
+ signature1 shadow load interrupt
+ (display controller, display stream 1)
+ - description: |
+ signature1 measurement valid interrupt
+ (display controller, display stream 1)
+ - description: |
+ signature1 error condition interrupt
+ (display controller, display stream 1)
+ - description: |
+ command sequencer error condition interrupt(command sequencer)
+ - description: |
+ common control software interrupt0(common control)
+ - description: |
+ common control software interrupt1(common control)
+ - description: |
+ common control software interrupt2(common control)
+ - description: |
+ common control software interrupt3(common control)
+ - description: |
+ framegen0 synchronization status activated interrupt
+ (display controller, safety stream 0)
+ - description: |
+ framegen0 synchronization status deactivated interrupt
+ (display controller, safety stream 0)
+ - description: |
+ framegen0 synchronization status activated interrupt
+ (display controller, content stream 0)
+ - description: |
+ framegen0 synchronization status deactivated interrupt
+ (display controller, content stream 0)
+ - description: |
+ framegen1 synchronization status activated interrupt
+ (display controller, safety stream 1)
+ - description: |
+ framegen1 synchronization status deactivated interrupt
+ (display controller, safety stream 1)
+ - description: |
+ framegen1 synchronization status activated interrupt
+ (display controller, content stream 1)
+ - description: |
+ framegen1 synchronization status deactivated interrupt
+ (display controller, content stream 1)
+
+ interrupt-names:
+ items:
+ - const: store9_shdload
+ - const: store9_framecomplete
+ - const: store9_seqcomplete
+ - const: extdst0_shdload
+ - const: extdst0_framecomplete
+ - const: extdst0_seqcomplete
+ - const: extdst4_shdload
+ - const: extdst4_framecomplete
+ - const: extdst4_seqcomplete
+ - const: extdst1_shdload
+ - const: extdst1_framecomplete
+ - const: extdst1_seqcomplete
+ - const: extdst5_shdload
+ - const: extdst5_framecomplete
+ - const: extdst5_seqcomplete
+ - const: disengcfg_shdload0
+ - const: disengcfg_framecomplete0
+ - const: disengcfg_seqcomplete0
+ - const: framegen0_int0
+ - const: framegen0_int1
+ - const: framegen0_int2
+ - const: framegen0_int3
+ - const: sig0_shdload
+ - const: sig0_valid
+ - const: sig0_error
+ - const: disengcfg_shdload1
+ - const: disengcfg_framecomplete1
+ - const: disengcfg_seqcomplete1
+ - const: framegen1_int0
+ - const: framegen1_int1
+ - const: framegen1_int2
+ - const: framegen1_int3
+ - const: sig1_shdload
+ - const: sig1_valid
+ - const: sig1_error
+ - const: cmdseq_error
+ - const: comctrl_sw0
+ - const: comctrl_sw1
+ - const: comctrl_sw2
+ - const: comctrl_sw3
+ - const: framegen0_primsync_on
+ - const: framegen0_primsync_off
+ - const: framegen0_secsync_on
+ - const: framegen0_secsync_off
+ - const: framegen1_primsync_on
+ - const: framegen1_primsync_off
+ - const: framegen1_secsync_on
+ - const: framegen1_secsync_off
+
+ clocks:
+ maxItems: 8
+
+ clock-names:
+ items:
+ - const: axi
+ - const: cfg
+ - const: pll0
+ - const: pll1
+ - const: bypass0
+ - const: bypass1
+ - const: disp0
+ - const: disp1
+
+ power-domains:
+ items:
+ - description: DC power-domain
+ - description: PLL0 power-domain
+ - description: PLL1 power-domain
+
+ power-domain-names:
+ items:
+ - const: dc
+ - const: pll0
+ - const: pll1
+
+ fsl,dpr-channels:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ List of phandle which points to DPR channels associated with
+ this DPU instance.
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: The DPU output port node from display stream0.
+
+ port@1:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: The DPU output port node from display stream1.
+
+ required:
+ - port@0
+ - port@1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-names
+ - clocks
+ - clock-names
+ - power-domains
+ - power-domain-names
+ - fsl,dpr-channels
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx8-lpcg.h>
+ #include <dt-bindings/firmware/imx/rsrc.h>
+ dpu@56180000 {
+ compatible = "fsl,imx8qxp-dpu";
+ reg = <0x56180000 0x40000>;
+ interrupt-parent = <&dc0_irqsteer>;
+ interrupts = <448>, <449>, <450>, <64>,
+ <65>, <66>, <67>, <68>,
+ <69>, <70>, <193>, <194>,
+ <195>, <196>, <197>, <72>,
+ <73>, <74>, <75>, <76>,
+ <77>, <78>, <79>, <80>,
+ <81>, <199>, <200>, <201>,
+ <202>, <203>, <204>, <205>,
+ <206>, <207>, <208>, <0>,
+ <1>, <2>, <3>, <4>,
+ <82>, <83>, <84>, <85>,
+ <209>, <210>, <211>, <212>;
+ interrupt-names = "store9_shdload",
+ "store9_framecomplete",
+ "store9_seqcomplete",
+ "extdst0_shdload",
+ "extdst0_framecomplete",
+ "extdst0_seqcomplete",
+ "extdst4_shdload",
+ "extdst4_framecomplete",
+ "extdst4_seqcomplete",
+ "extdst1_shdload",
+ "extdst1_framecomplete",
+ "extdst1_seqcomplete",
+ "extdst5_shdload",
+ "extdst5_framecomplete",
+ "extdst5_seqcomplete",
+ "disengcfg_shdload0",
+ "disengcfg_framecomplete0",
+ "disengcfg_seqcomplete0",
+ "framegen0_int0",
+ "framegen0_int1",
+ "framegen0_int2",
+ "framegen0_int3",
+ "sig0_shdload",
+ "sig0_valid",
+ "sig0_error",
+ "disengcfg_shdload1",
+ "disengcfg_framecomplete1",
+ "disengcfg_seqcomplete1",
+ "framegen1_int0",
+ "framegen1_int1",
+ "framegen1_int2",
+ "framegen1_int3",
+ "sig1_shdload",
+ "sig1_valid",
+ "sig1_error",
+ "cmdseq_error",
+ "comctrl_sw0",
+ "comctrl_sw1",
+ "comctrl_sw2",
+ "comctrl_sw3",
+ "framegen0_primsync_on",
+ "framegen0_primsync_off",
+ "framegen0_secsync_on",
+ "framegen0_secsync_off",
+ "framegen1_primsync_on",
+ "framegen1_primsync_off",
+ "framegen1_secsync_on",
+ "framegen1_secsync_off";
+ clocks = <&dc0_dpu_lpcg IMX_LPCG_CLK_5>,
+ <&dc0_dpu_lpcg IMX_LPCG_CLK_4>,
+ <&clk IMX_SC_R_DC_0_PLL_0 IMX_SC_PM_CLK_PLL>,
+ <&clk IMX_SC_R_DC_0_PLL_1 IMX_SC_PM_CLK_PLL>,
+ <&clk IMX_SC_R_DC_0_VIDEO0 IMX_SC_PM_CLK_BYPASS>,
+ <&clk IMX_SC_R_DC_0_VIDEO1 IMX_SC_PM_CLK_BYPASS>,
+ <&dc0_disp_lpcg IMX_LPCG_CLK_0>,
+ <&dc0_disp_lpcg IMX_LPCG_CLK_1>;
+ clock-names = "axi", "cfg",
+ "pll0", "pll1", "bypass0", "bypass1",
+ "disp0", "disp1";
+ power-domains = <&pd IMX_SC_R_DC_0>,
+ <&pd IMX_SC_R_DC_0_PLL_0>,
+ <&pd IMX_SC_R_DC_0_PLL_1>;
+ power-domain-names = "dc", "pll0", "pll1";
+ fsl,dpr-channels = <&dc0_dpr1_channel1>,
+ <&dc0_dpr1_channel2>,
+ <&dc0_dpr1_channel3>,
+ <&dc0_dpr2_channel1>,
+ <&dc0_dpr2_channel2>,
+ <&dc0_dpr2_channel3>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dpu0_disp0_pixel_combiner0_ch0: endpoint {
+ remote-endpoint = <&pixel_combiner0_ch0_dpu0_disp0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dpu0_disp1_pixel_combiner0_ch1: endpoint {
+ remote-endpoint = <&pixel_combiner0_ch1_dpu0_disp1>;
+ };
+ };
+ };
+ };
--
2.37.1
This patch adds bindings for i.MX8qxp/qm Display Prefetch Resolve Channel.
Reviewed-by: Rob Herring <[email protected]>
Signed-off-by: Liu Ying <[email protected]>
---
v10->v12:
* No change.
v9->v10:
* Add Rob's R-b tag.
v8->v9:
* Reference 'interrupts-extended' schema instead of 'interrupts' to require
an additional interrupt(r_rtram_stall) because the reference manual does
mention it, though the driver doesn't get/use it for now.
Reference 'interrupt-names' schema to define the two interrupt names -
'dpr_wrap' and 'r_rtram_stall'.
* Drop Rob's R-b tag, as review is needed.
v4->v8:
* No change.
v3->v4:
* Improve compatible property by using enum instead of oneOf+const. (Rob)
* Add Rob's R-b tag.
v2->v3:
* No change.
v1->v2:
* Use new dt binding way to add clocks in the example.
.../display/imx/fsl,imx8qxp-dprc.yaml | 100 ++++++++++++++++++
1 file changed, 100 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dprc.yaml
diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dprc.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dprc.yaml
new file mode 100644
index 000000000000..bd94254c1288
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dprc.yaml
@@ -0,0 +1,100 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dprc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8qm/qxp Display Prefetch Resolve Channel
+
+maintainers:
+ - Liu Ying <[email protected]>
+
+description: |
+ The i.MX8qm/qxp Display Prefetch Resolve Channel(DPRC) is an engine which
+ fetches display data before the display pipeline needs the data to drive
+ pixels in the active display region. This data is transformed, or resolved,
+ from a variety of tiled buffer formats into linear format, if needed.
+ The DPR works with a double bank memory structure. This memory structure is
+ implemented in the Resolve Tile Memory(RTRAM) and the banks are referred to
+ as A and B. Each bank is either 4 or 8 lines high depending on the source
+ frame buffer format.
+
+properties:
+ compatible:
+ enum:
+ - fsl,imx8qxp-dpr-channel
+ - fsl,imx8qm-dpr-channel
+
+ reg:
+ maxItems: 1
+
+ interrupts-extended:
+ items:
+ - description: DPR wrap interrupt
+ - description: |
+ 'r_rtram_stall' interrupt which indicates relevant i.MX8qm/qxp
+ Prefetch Resolve Gasket(PRG) or PRGs are forcing an underflow
+ condition in the RTRAM.
+
+ interrupt-names:
+ items:
+ - const: dpr_wrap
+ - const: r_rtram_stall
+
+ clocks:
+ items:
+ - description: apb clock
+ - description: b clock
+ - description: rtram clock
+
+ clock-names:
+ items:
+ - const: apb
+ - const: b
+ - const: rtram
+
+ fsl,sc-resource:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: The SCU resource ID associated with this DPRC instance.
+
+ fsl,prgs:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ List of phandle which points to PRG or PRGs associated with
+ this DPRC instance.
+
+ power-domains:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts-extended
+ - interrupt-names
+ - clocks
+ - clock-names
+ - fsl,sc-resource
+ - fsl,prgs
+ - power-domains
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx8-lpcg.h>
+ #include <dt-bindings/firmware/imx/rsrc.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ dpr-channel@56100000 {
+ compatible = "fsl,imx8qxp-dpr-channel";
+ reg = <0x56100000 0x10000>;
+ interrupts-extended = <&gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
+ <&dc0_irqsteer 324>;
+ interrupt-names = "dpr_wrap", "r_rtram_stall";
+ clocks = <&dc0_dpr1_lpcg IMX_LPCG_CLK_4>,
+ <&dc0_dpr1_lpcg IMX_LPCG_CLK_5>,
+ <&dc0_rtram1_lpcg IMX_LPCG_CLK_0>;
+ clock-names = "apb", "b", "rtram";
+ fsl,sc-resource = <IMX_SC_R_DC_0_VIDEO0>;
+ fsl,prgs = <&dc0_prg4>, <&dc0_prg5>;
+ power-domains = <&pd IMX_SC_R_DC_0>;
+ };
--
2.37.1