2022-10-20 08:49:08

by Anup Patel

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Subject: [PATCH v5 0/4] Add PMEM support for RISC-V

The Linux NVDIMM PEM drivers require arch support to map and access the
persistent memory device. This series adds RISC-V PMEM support using
recently added Svpbmt and Zicbom support.

First two patches are fixes and remaining two patches add the required
PMEM support for Linux RISC-V.

These patches can also be found in riscv_pmem_v5 branch at:
https://github.com/avpatel/linux.git

Changes since v4:
- Simplify PATCH2 by implementing RISC-V specific arch_memremap_wb()

Changes since v3:
- Pickup correct version of Drew's patch as PATCH1

Changes since v2:
- Rebased on Linux-6.1-rc1
- Replaced PATCH1 with the patch proposed by Drew

Changes since v1:
- Fix error reported by test bot
https://lore.kernel.org/all/[email protected]/

Andrew Jones (1):
RISC-V: Fix compilation without RISCV_ISA_ZICBOM

Anup Patel (3):
RISC-V: Fix MEMREMAP_WB for systems with Svpbmt
RISC-V: Implement arch specific PMEM APIs
RISC-V: Enable PMEM drivers

arch/riscv/Kconfig | 1 +
arch/riscv/configs/defconfig | 1 +
arch/riscv/include/asm/cacheflush.h | 8 ------
arch/riscv/include/asm/io.h | 5 ++++
arch/riscv/mm/Makefile | 1 +
arch/riscv/mm/cacheflush.c | 38 ++++++++++++++++++++++++++
arch/riscv/mm/dma-noncoherent.c | 41 -----------------------------
arch/riscv/mm/pmem.c | 21 +++++++++++++++
8 files changed, 67 insertions(+), 49 deletions(-)
create mode 100644 arch/riscv/mm/pmem.c

--
2.34.1


2022-10-20 08:51:11

by Anup Patel

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Subject: [PATCH v5 4/4] RISC-V: Enable PMEM drivers

We now have PMEM arch support available in RISC-V kernel so let us
enable relevant drivers in defconfig.

Signed-off-by: Anup Patel <[email protected]>
---
arch/riscv/configs/defconfig | 1 +
1 file changed, 1 insertion(+)

diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index 05fd5fcf24f9..462da9f7410d 100644
--- a/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@ -159,6 +159,7 @@ CONFIG_VIRTIO_MMIO=y
CONFIG_RPMSG_CHAR=y
CONFIG_RPMSG_CTRL=y
CONFIG_RPMSG_VIRTIO=y
+CONFIG_LIBNVDIMM=y
CONFIG_EXT4_FS=y
CONFIG_EXT4_FS_POSIX_ACL=y
CONFIG_EXT4_FS_SECURITY=y
--
2.34.1

2022-10-20 08:53:10

by Anup Patel

[permalink] [raw]
Subject: [PATCH v5 2/4] RISC-V: Fix MEMREMAP_WB for systems with Svpbmt

Currently, the memremap() called with MEMREMAP_WB maps memory using
the generic ioremap() function which breaks on system with Svpbmt
because memory mapped using _PAGE_IOREMAP page attributes is treated
as strongly-ordered non-cacheable IO memory.

To address this, we implement RISC-V specific arch_memremap_wb()
which maps memory using _PAGE_KERNEL page attributes resulting in
write-back cacheable mapping on systems with Svpbmt.

Fixes: ff689fd21cb1 ("riscv: add RISC-V Svpbmt extension support")
Co-developed-by: Mayuresh Chitale <[email protected]>
Signed-off-by: Mayuresh Chitale <[email protected]>
Signed-off-by: Anup Patel <[email protected]>
---
arch/riscv/include/asm/io.h | 5 +++++
1 file changed, 5 insertions(+)

diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h
index 92080a227937..42497d487a17 100644
--- a/arch/riscv/include/asm/io.h
+++ b/arch/riscv/include/asm/io.h
@@ -135,4 +135,9 @@ __io_writes_outs(outs, u64, q, __io_pbr(), __io_paw())

#include <asm-generic/io.h>

+#ifdef CONFIG_MMU
+#define arch_memremap_wb(addr, size) \
+ ((__force void *)ioremap_prot((addr), (size), _PAGE_KERNEL))
+#endif
+
#endif /* _ASM_RISCV_IO_H */
--
2.34.1

2022-10-24 23:05:03

by Conor Dooley

[permalink] [raw]
Subject: Re: [PATCH v5 2/4] RISC-V: Fix MEMREMAP_WB for systems with Svpbmt

On Thu, Oct 20, 2022 at 01:28:44PM +0530, Anup Patel wrote:
> Currently, the memremap() called with MEMREMAP_WB maps memory using
> the generic ioremap() function which breaks on system with Svpbmt
> because memory mapped using _PAGE_IOREMAP page attributes is treated
> as strongly-ordered non-cacheable IO memory.
>
> To address this, we implement RISC-V specific arch_memremap_wb()
> which maps memory using _PAGE_KERNEL page attributes resulting in
> write-back cacheable mapping on systems with Svpbmt.
>
> Fixes: ff689fd21cb1 ("riscv: add RISC-V Svpbmt extension support")
> Co-developed-by: Mayuresh Chitale <[email protected]>
> Signed-off-by: Mayuresh Chitale <[email protected]>
> Signed-off-by: Anup Patel <[email protected]>

Hey Arnd,
Does this look okay to you now?
Thanks,
Conor.

> ---
> arch/riscv/include/asm/io.h | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h
> index 92080a227937..42497d487a17 100644
> --- a/arch/riscv/include/asm/io.h
> +++ b/arch/riscv/include/asm/io.h
> @@ -135,4 +135,9 @@ __io_writes_outs(outs, u64, q, __io_pbr(), __io_paw())
>
> #include <asm-generic/io.h>
>
> +#ifdef CONFIG_MMU
> +#define arch_memremap_wb(addr, size) \
> + ((__force void *)ioremap_prot((addr), (size), _PAGE_KERNEL))
> +#endif
> +
> #endif /* _ASM_RISCV_IO_H */
> --
> 2.34.1
>